Sundance SMT368 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Unit / Module Description: Virtex 4 FPGA module
Unit / Module Number: SMT368
Document Issue Number: 2.5
Issue Date:
Original Author: Sebastien Maury
User Manual
for
Form : QCF42
Date : 6 July 2006
SMT368
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
User Manual SMT368 Last Edited: 31/12/2008 13:53:00
Revision History
Issue Changes Made Date Initials
2.0 New release 04/09/2006 SM
2.1 Added: weight characteristic 21/09/2006 SM
2.2 Added detailed ZBT banks arrangement 04/10/06 E.P
2.3 Corrected wrong sw1 positions for flash
configuration
2.4 Added section about programming the Xilinx
PROM
2.5 Added positioning and names of switches on
SW1 and SW2 in figure 13, PCB top view
03/04/07 E.P
28/11/07 E.P
31/12/08 E.P
User Manual SMT368 Page 2 of 24 Last Edited: 31/12/2008 13:53:00
Table of Contents
1 Introduction............................................................................................... 6
2 Related Documents ....................................................................................6
2.1 Referenced Documents ..................................................................................................6
2.2 Applicable Documents....................................................................................................6
3 Acronyms, Abbreviations and Definitions.................................................. 7
3.1 Acronyms and Abbreviations.........................................................................................7
3.2 Definitions ......................................................................................................................7
4 Functional Description...............................................................................8
4.1 Block Diagram ................................................................................................................8
4.1.1 Major features............................................................................................................8
4.1.2 Communication resources.........................................................................................8
4.1.3 FPGA ..........................................................................................................................9
4.1.4 CPLD ..........................................................................................................................9
4.1.5 PROM.........................................................................................................................9
4.1.6 ZBTRAM ....................................................................................................................9
4.1.7 Sundance High-speed bus.......................................................................................10
4.1.8 Sundance Low voltage differential signals Bus........................................................11
4.1.9 TIM Connectors .......................................................................................................12
4.1.10 DIP Switches ............................................................................................................12
4.1.11 Clocking scheme ......................................................................................................12
4.1.12 LEDs.........................................................................................................................13
4.1.13 I/Os ..........................................................................................................................13
4.2 Module Description......................................................................................................13
4.2.1 FPGA Configuration ................................................................................................13
4.2.2 FPGA Reset Scheme.................................................................................................14
4.2.3 TIM config................................................................................................................ 15
4.3 Interface Description.................................................................................................... 15
4.3.1 Mechanical Interface ...............................................................................................15
4.3.2 Electrical Interface................................................................................................... 15
4.3.3 Programming the Xilinx PROM ..............................................................................16
5 Footprint..................................................................................................20
5.1 Top View ...................................................................................................................... 20
5.2 Bottom View..................................................................................................................21
6 Pinout .......................................................................................................21
6.1 DIP switch SW2............................................................................................................21
6.2 SHB Header ..................................................................................................................21
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6.3 JTAG Header ................................................................................................................21
6.4 I/Os Header..................................................................................................................23
6.5 Fan Header ...................................................................................................................23
7 Support Packages..................................................................................... 23
8 Physical Properties .................................................................................. 24
9 Safety .......................................................................................................24
10 EMC ......................................................................................................... 24
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Table of Figures and Tables
Figure 1: Block Diagram................................................................................................................8
Figure 2:FPGA connections to Bank1 of ZBT...............................................................................9
Figure 3: ZBT Constraints file signal names ..............................................................................10
Figure 4: SHB Constraints file control signal names.................................................................10
Figure 5: SHB Constraints file data signal names ......................................................................11
Figure 6: ComPort Constraints file signal names ......................................................................12
Figure 7: Schematics of the External Clock I/O......................................................................... 13
Figure 8: CPLD state machine....................................................................................................14
Figure 9: PROM file selection.....................................................................................................16
Figure 10: Program Options .......................................................................................................17
Figure 11: PROM programming..................................................................................................18
Figure 12: Programming succeeded ...........................................................................................19
Figure 13: PCB – Top view......................................................................................................... 20
Figure 14: PCB – Bottom view....................................................................................................21
Figure 15: Pinout JTAG header – JP1 ........................................................................................22
Figure 16: Pinout JTAG header – JP1 ........................................................................................22
Figure 17: Boundary JTAG chain (Xilinx iMPACT)...................................................................23
Figure 18: Pinout TTL I/Os – JP3..............................................................................................23
Figure 19: Pinout TTL I/Os– JP3...............................................................................................23
Table 1: External Clock specification.......................................................................................... 12
Table 2: LEDs connections .........................................................................................................13
Table 3: SW1 DIP switch for the configuration mode selection ................................................14
Table 4: SW1 DIP switch for the configuration mode selection................................................ 15
Table 5:SW2 DIP switch settings................................................................................................ 21
User Manual SMT368 Page 5 of 24 Last Edited: 31/12/2008 13:53:00
1 Introduction
The SMT368 is a single-size module based on a Virtex-4 FPGA (XC4VSX35) and provides the
following features:
• On-board ZBTRAM memory,
• Four Sundance High-speed Bus connections,
• One Sundance LVDS Bus connections allowing pairing with daughter modules,
• Four ComPort connections,
• One external clock I/O,
• LEDs and user defined I/O pins.
This variety of connectors and interfaces provides a wide range of development opti ons for
designers to explore the capabilities of the comprehensive family of Sundan ce modules and
carrier boards.
2 Related Documents
2.1 Referenced Documents
Sundance help file
Sundance SHB specification document
Sundance SDB specification document
Sundance SLB specification document
Sundance SDL specification document
TI TIM specification & user’s guide
Sundance’s documentation and user guides
2.2 Applicable Documents
Texas Instruments specification & user’s guide
ComPort specification document (Refer to Chapter 12)
Xilinx PROM XCF32PVOG48C
SAMSUNG ZBTRAM datasheet
XC2C128 CoolRunner-II CPLD
Virtex-4 user guide
Xilinx Xapp136
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3 Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
TIM Texas Instruments Module
DSP Digital Signal Processor
FPGA Field Programmable Gate Array
NtRAM No Turnaround Random Access Memory
ZBTRAM Zero Bus Turnaround Random Access Memory
CP ComPort, Communication interface
SDB Sundance Digital Bus, Communication interface
SHB Sundance High-Speed Bus, Communication interface
SLB Sundance LVDS Bus, Communication interface
3.2 Definitions
DSP Module
FPGA-only Module A TIM with no on-board DSP, where the FPGA provides all functionality
Firmware A proprietary FPGA design providing some sort of functionality.
A TIM module hosting a TI DSP, and a Xilinx FPGA
Sundance Firmware is the firmware running into a FPGA of a DSP
module.
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4 Functional Description
The module is conformed to the Texas Instruments Module standard for single-size modules.
It sits on a carrier board that provides electrical connections (power, ground) and
communication links (ComPort) between all the modules fitted. It is also a pathway to the
host, for a non stand-alone system.
4.1 Block Diagram
Figure 1: Block Diagram
4.1.1 Major features
• Block1: Xilinx Virtex-4 XC4VSX35, configuration and reset schemes,
• Block2: ZBTRAM memory,
• Block3: I/O connectors for general purpose or dedicated interfaces,
• Block4: Clocking scheme,
• Block5: LEDs for development, in-use monitoring and general purpose use.
4.1.2 Communication resources
Please refer to the
from the TIM to the carrier board and the external world interfacing.
Please refer to the Sundance
resources provided by Sundance and available onto the SMT368.
User Manual SMT368 Page 8 of 24 Last Edited: 31/12/2008 13:53:00
Sundance help file for the general description of the Sundance’s boards
SMT6400 help file for the description of the communication
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