Sundance SMT365G User Manual

SMT365G

User Manual

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

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Revision History

Date Comments Engineer Version

23/09/04 First rev, based on 365 user manual (v1.1.3) J.V. 1.0.0

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Table of Contents

Revision History ....................................................................................................... 2

Contacting Sundance............................................................................................... 4

Notational Conventions ................................................Error! Bookmark not defined.

C60 ......................................................................................................................... 4

SDB ........................................................................................................................ 4

Outline Description .................................................................................................. 6

Architecture Description.......................................................................................... 7

TMS320C6416 ........................................................................................................... 8

Boot Mode............................................................................................................... 8

Flash Boot.......................................................................................................... 8

HPI Boot ............................................................................................................. 8

EMIF Control Registers........................................................................................... 9

ZBTRAM ............................................................................................................... 10

FLASH .................................................................................................................. 10

Virtex FPGA ..................................................................................................... 11

Reprogramming the firmware and boot code ...................................................... 12

Interrupts................................................................................................................. 13

SDL/Communication ports .................................................................................... 13

SHB.......................................................................................................................... 13

SHB-Half Word (16-bits SDB) firmware version.................................................... 13

SDB Clock selection .......................................................................................... 13

SHB-Word (SHB32x) firmware version ....................Error! Bookmark not defined.

Compatibility 16/32 bits ........................................Error! Bookmark not defined.

SDB Clock selection.............................................Error! Bookmark not defined.

Global bus............................................................................................................... 14

LED Setting ............................................................................................................. 14

CONFIG & NMI ........................................................................................................ 14

Timer........................................................................................................................ 14

IIOF interrupt........................................................................................................... 14

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FPGA space availability ......................................................................................... 15

Code Composer...................................................................................................... 15

Application Development..............................................Error! Bookmark not defined.

Operating Conditions............................................................................................. 15

Safety.................................................................................................................... 15

EMC...................................................................................................................... 15

General Requirements.......................................................................................... 16

Power Consumption.............................................................................................. 16

Weight................................................................................................................... 16

Connector Positions .............................................................................................. 17

Serial Ports & Other C60 I/O .................................................................................. 18

FPGA and CPLD JTAG........................................................................................... 18

Virtex Memory Map................................................................................................. 19

SHB pin-out............................................................................................................. 21

16-bits SDB interface: ..............................................Error! Bookmark not defined.

32-bits SDB interface: ..............................................Error! Bookmark not defined.

FPGA Pin-Out.................................................................Error! Bookmark not defined.

Bibliography............................................................................................................ 22

Index ........................................................................................................................ 23

Contacting Sundance

You can contact Sundance for additional information by login onto the support system

C60

The terms C60, C64xx and TMS320C64xx will be used interchangeably throughout this document.

SDB

support.sundance.com

The term SDB will be used throughout this document to refer to a 16 bit data bus carried by either an SDB connector or an SHB connector. The SHB connector can carry two such SDB buses.

Register Descriptions

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The format of registers is described using diagrams of the following form:

31–24 23–16 15–8 7–0

OFLAGLEVEL

R,00000000 RW,10000000 R,00000000 R,10000000

The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields. The bottom row describes what may be done to the field and its value after reset. Shaded fields are reserved and should only ever be written with zeroes.

R Readable by the CPU

W Writeable by the CPU

RW Readable and writeable by the CPU

Binary digits indicate the value of the field after reset.

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Outline Description

The SMT365G is a C64xx-based size 1 TIM offering the following features:

 TMS320C6416T processor running at 1GHz

 Six 20MB/s communication ports (ComPort)

 8MB of ZBTRAM (133MHz)

 8MByte Flash ROM for boot code and FPGA programming

 Global expansion connector

 High bandwidth data I/O via Sundance Digital Buses (SDB) or Sundance High

Speed Buses (SHB).

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Block Diagram

Architecture Description

The SMT365G TIM consists of a Texas Instruments TMS320C6416T running at up to 1GHz. Modules are populated with 8MBytes of zero bus turnaround RAM (ZBTRAM).

A Field Programmable Gate Array (FPGA) is used to manage global bus accesses and implement six communication ports and four Sundance Digital Buses. This is a Xilinx VirtexII device.

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