Sundance SMT365E User Manual

SMT365E

User Manual

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

Version 2.1 Page 2 of 26 SMT365e User Manual

Revision History

Date Comments Engineer Version

18/07/02 First rev, based on 361 GP 1.0.0 06/01/03 User manual updated, 2 SHBs YC 1.0.1 16/01/03 Changed flash to 4Mbyte GP 1.0.2 20/01/03 Added FPGA pin-out GP 1.0.3 31/01/03 Changed CPLD hdr pin-out.

GP 1.0.4

Set DSP clk=600, emif clk=100 24/02/03 No more SDBs clock selection JPA 1.0.5 17/03/03 Added location of SDBs on the board.

JPA 1.0.6

Updated FPGA memory mapping. 24/04/03 Updated Data Sheets (Hyperlinks) section JPA 1.0.7 19/09/03 Updated Data Sheets (Hyperlinks) section

JPA 1.0.8

Updated Reprogramming chapter 09/08/05 Update: the user manual supports the new

SM 2.0 firmware implementation V3.0 (XC2V6000) and the firmware V1.0 (XC2V8000)

25/01/06 Errata: Flash ROM access SM 2.1 16/02/06 Update: the user manual supports the new

AL 2.2 firmware implementation for 2xSDBs, 32bits V3.12 (XC2V6000)

Version 2.1 Page 3 of 26 SMT365e User Manual

Table of Contents

Revision History....................................................................................................... 2

Contacting Sundance............................................................................................... 4

Notational Conventions ........................................................................................... 5

DSP ........................................................................................................................ 5

SDB ........................................................................................................................ 5

SHB ........................................................................................................................ 5

Outline Description .................................................................................................. 6

Intended Audience ................................................................................................... 6

Block Diagram .......................................................................................................... 7

Architecture Description.......................................................................................... 8

DSP............................................................................................................................ 8

Boot Mode............................................................................................................... 8

EMIF Control Registers........................................................................................... 9

SDRAM................................................................................................................... 9

FLASH .................................................................................................................. 10

Virtex FPGA............................................................................................................. 11

Version control...................................................................................................... 11

Firmware versions.................................................................................................. 11

Reprogramming the firmware and boot code ...................................................... 11

Comports................................................................................................................. 12

SHB.......................................................................................................................... 12

Global bus............................................................................................................... 12

LED Setting............................................................................................................. 13

LED Register......................................................................................................... 13

CONFIG & NMI ........................................................................................................ 14

Config Register..................................................................................................... 14

Timer........................................................................................................................ 15

Timer Control Register.......................................................................................... 15

IIOF interrupt........................................................................................................... 16

Code Composer...................................................................................................... 17

Version 2.1 Page 4 of 26 SMT365e User Manual

Application Development....................................................................................... 17

SMT6400 .............................................................................................................. 17

3L Diamond........................................................................................................... 17

SMT6500 .............................................................................................................. 17

Operating Conditions............................................................................................. 18

Safety.................................................................................................................... 18

EMC...................................................................................................................... 18

General Requirements.......................................................................................... 18

Power Consumption.............................................................................................. 18

Connector Positions .............................................................................................. 19

Serial Ports & Other C60 I/O.................................................................................. 20

FPGA and CPLD JTAG........................................................................................... 20

Virtex Memory Map................................................................................................. 21

SHB pin-out........................................................................................................... 23

SHB generic pin-out.............................................................................................. 23

FPGA PROG Pin Control (JP7 connector)............................................................ 24

DSP Boot Mode Control (JP6 connector).............................................................. 24

Bibliography............................................................................................................ 25

INDEX ...................................................................................................................... 26

Contacting Sundance

You can contact Sundance for additional information by login onto the Sundance

support forum.

Version 2.1 Page 5 of 26 SMT365e User Manual

Notational Conventions

DSP

The terms DSP, C64xx and TMS320C64xx will be used interchangeably throughout this document.

SDB

The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface.

SHB

The term SHB will be used throughout this document to refer to the Sundance Highspeed Bus interface.

The format of registers is described using diagrams of the following form:

31–24 23–16 15–8 7–0

OFLAGLEVEL

R,00000000 RW,10000000 R,00000000 R,10000000

The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields. The bottom row describes what may be done to the field and its value after reset. Shaded fields are reserved and should only ever be written with zeroes.

R Readable by the CPU W Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset

Version 2.1 Page 6 of 26 SMT365e User Manual

Outline Description

The SMT365 is a DSP module, size 2 TIM offering the following features:

 TMS320C6416 processor running at 600MHz  Six comports  256MB of SDRAM (100MHz)  4MB of Flash ROM  Global Bus connector  6 SHB connectors for high-speed data transfer

Intended Audience

There are two existing versions of the firmware for the SMT365e. For each of the versions of the different firmware is loaded in the FPGA:

- Firmware version 1.1 or

- Firmware version 1.2

This user manual covers the version 1.2 of the firmware for the SMT365e implemented with the model described in the SMT6500 help file.

Refer to section Firmware versions.

Version 2.1 Page 7 of 26 SMT365e User Manual

Block Diagram

The following drawing shows the block diagram of the SMT365e module. The main components of the SMT365e are:

- A Texas Instruments DSP

- One Xilinx FPGA Virtex-II device

- 256MB of SDRAM

DC-DC Converters for DSP

and FPGA cores

JTAG Header

X-Checker Header

4 LEDs &

4 I/O pins

Sundance High-speed Bus

60-way Samtec x 6

360 pins

J1 Top Primary TIM

Connector

Comm -Port 0 & 3

26 I/O pins

Timer,& Control

2x Comm-Ports/SDL

FPG A C ontroller

Virtex-II, FF1152

824 I/O pins - Used 776

XC2V6000

1.5V

15 I/O pins

171 pins

McBSP/Utopia/

GPIO

'C6416

DSP

525 pins

256Mbytes SDRAM

Flash

4 LEDs + GPIO

Oscillator

74 I/O pins

Global Bus

J3 Global Expansion Connector

J2 Botto m P r imary

Comm -Port 1;2;5;4

52 I/O pins

4x Comm-Port/SDL

TIM Connector

Version 2.1 Page 8 of 26 SMT365e User Manual

Architecture Description DSP

The Texas Instruments DSP can run at up to 600MHz. The DSP is doted of 256MB of Synchronous DRAM (SDRAM).

The DSP is a TMS320C6416 type. This is a fixed-point digital signal processor provided by Texas Instruments. The

processor will run with zero wait states from internal SRAM. The internal memory is 1MB in size and can be partitioned between normal SRAM and L2 cache.

An on-board crystal oscillator provides the clock used for the DSP which them multiplies this by twelve internally.

Boot Mode

The DSP is connected to the on-board flash ROM that contains the Sundance bootloader and the FPGA bitstream.

Following reset, the DSP will automatically load the data from the flash ROM into its internal program memory at address 0 and then start executing from there. All this code is the Sundance bootloader, and it is made up of two parts: FPGA configuration and processor configuration. FPGA configuration uses data in the ROM to configure the FPGA. A processor configuration sets the processor into a standard state by writing into the DSP internal registers of the EMIF. Then it configures the FPGA from the data held in the flash ROM.

The bootloader is executed. It will continually check the six comports until data appears on one of them. This will next load a program in boot format from this comport. Note that the bootloader will not read data arriving on other comports. Finally the control is passed to the loaded DSP application.

The DSP will take approximately about 46s to configure the FPGA following reset, assuming a 600MHz clock. The external devices implemented in the FPGA (such as comports) must not be used during this configuration.

It is safest to wait for the configuration to complete. Note that comports will appear to be "not ready" until the FPGA has been configured.

The FPGA programming algorithm is not described here. It can be found in the boot code.

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Sundance SMT365E User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual