Sundance SMT365 User Manual

SMT365

User Manual

User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001

Version 2.3 Page 2 of 28 SMT365 User Manual

Revision History

Date Comments Engineer Version

18/7/02 First rev, based on 361 GP 1.0.0

06/01/03 User manual updated, 2 SHBs YC 1.0.1

16/1/03 Revised board layout, control registers, paging GP 1.0.2 20/1/03 Added FPGA pin-out GP 1.0.3

27/01/03 Updated interrupt registers, global status register JPA 1.0.4

30/01/03 Corrected CPLD header pin-out. GP 1.0.5 14/03/03 Added location of SDBs on the board JPA 1.0.6 11/04/03 Corrected I/O connector block pin-out GP 1.0.7 08/05/03 Added link to General firmware specification, SHB and

SDB specification, added fpga pinout convention

19/08/03 Page 30: NSDRAMCS mapped on emif_ctrl<5>

Updated Reprogramming chapter

20/10/03 Added information about SHB-Word (SHB32x) firmware

version.

01/12/03 SHB-Word (SHB32x) firmware version available for both

SMT365-1 and –2 modules SDL interface availability FPGA space availability

11/03/04 Updated Flash section

Added board’s weight

04/05/04 Corrected figure 1 (Flash logical sections).

Updated EMIFB CE3 space control register value. Updated EMIFA CE1 address range.

Updated FPGA space availability section. 25/10/04 Create the FPGA configuration section SM 1.1.4 04/08/05 Update: the user manual supports the new firmware

implementation

JPA 1.0.8

JPA 1.0.9

JPA 1.1.0

JPA 1.1.1

JPA 1.1.2

JPA 1.1.3

SM 2.0

13/12/05 Details added on EMIF registers settings JV 2.1 15/02/06 Changed GEL file contents. GP 2.2 09/05/06 Minor changes SM 2.3

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Revision History....................................................................................................... 2

Table of Contents ..................................................................................................... 3

Contacting Sundance............................................................................................... 4

Notational Conventions ........................................................................................... 5

DSP ........................................................................................................................ 5

SDB ........................................................................................................................ 5

SHB ........................................................................................................................ 5

Outline Description .................................................................................................. 6

Intended Audience ................................................................................................... 6

Block Diagram .......................................................................................................... 7

Architecture Description.......................................................................................... 8

DSP............................................................................................................................ 8

Boot Mode............................................................................................................... 8

EMIF Control Registers........................................................................................... 9

ZBTRAM .................................................................................................................. 11

FLASH ..................................................................................................................... 12

Virtex FPGA............................................................................................................. 13

Version control...................................................................................................... 13

Firmware versions.................................................................................................. 13

Reprogramming the firmware and boot code ...................................................... 13

Comports................................................................................................................. 14

SHB.......................................................................................................................... 14

Architecture........................................................................................................... 14

Global bus............................................................................................................... 14

LED Setting............................................................................................................. 14

LED Register......................................................................................................... 15

CONFIG & NMI ........................................................................................................ 16

Config Register..................................................................................................... 16

Timer........................................................................................................................ 17

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IIOF interrupt........................................................................................................... 18

FPGA space availability......................................................................................... 18

Code Composer...................................................................................................... 19

Application Development....................................................................................... 19

SMT6400 .............................................................................................................. 19

3L Diamond........................................................................................................... 19

SMT6500 .............................................................................................................. 19

Operating Conditions............................................................................................. 20

Safety.................................................................................................................... 20

EMC...................................................................................................................... 20

General Requirements.......................................................................................... 20

Power Consumption.............................................................................................. 20

Weight................................................................................................................... 20

Connector Positions .............................................................................................. 21

Serial Ports & Other DSP I/O ................................................................................. 22

FPGA and CPLD JTAG........................................................................................... 22

FPGA configuration................................................................................................ 22

Virtex Memory Map................................................................................................. 23

SHB pinout.............................................................................................................. 25

SHB generic pin-out.............................................................................................. 25

32-bits SDB interface:........................................................................................... 26

Bibliography............................................................................................................ 27

Index........................................................................................................................ 28

Contacting Sundance

You can contact Sundance for additional information by login onto the Sundance

support forum.

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Notational Conventions

DSP

The terms DSP, C64xx and TMS320C64xx will be used interchangeably throughout this document.

SDB

The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface.

SHB

The term SHB will be used throughout this document to refer to the Sundance Highspeed Bus interface.

Register Descriptions

The format of registers is described using diagrams of the following form:

31–24 23–16 15–8 7–0

OFLAGLEVEL

R,00000000 RW,10000000 R,00000000 R,10000000

The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields. The bottom row describes what may be done to the field and its value after reset. Shaded fields are reserved and should only ever be written with zeroes.

R Readable by the CPU W Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset

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Outline Description

The SMT365 is a DSP module, size 1 TIM offering the following features:

 TMS320C6416 processor running at 600MHz  Six 20MB/s comports  8MB of ZBTRAM (133MHz)  8MBytes Flash ROM  Global Bus connector  2 SHB connectors for high-speed data transfer

Intended Audience

There are two existing versions of the firmware for the SMT365. These two versions differ by the number and the type of communication resources (comport and SDB interfaces) provided.

For each of the versions of the different firmware is loaded in the FPGA:

- Firmware version 1.0 or

- Firmware version 2.0

This user manual covers the version 2.0 of the firmware for the SMT365 implemented with the model described in the

The changes between the firmware version 1.0 and version 2.0 are described in the section Firmware versions.

SMT6500 help file.

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Block Diagram

The following drawing shows the block diagram of the SMT365 module. The main components of the SMT365 are:

- a Texas Instruments DSPs

- One Xilinx FPGA Virtex-II device

- 8MB of ZBTRAM

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Architecture Description

DSP

The Texas Instruments DSP can run at up to 600MHz. The DSP is doted of 8MBytes of Zero Bus Turnaround RAM (ZBTRAM).

The DSP is a TMS320C6416 type. This is a fixed-point digital signal processor provided by Texas Instruments. The

processor will run with zero wait states from internal SRAM. The internal memory is 1MB in size and can be partitioned between normal SRAM and L2 cache.

An on-board crystal oscillator provides the clock used for the DSP which them multiplies this by twelve internally.

Boot Mode

The DSP is connected to the on-board flash ROM that contains the Sundance bootloader and the FPGA bitstream.

Following reset, the DSP will automatically load the data from the flash ROM into its internal program memory at address 0 and then start executing from there. All this code is the Sundance bootloader, and it is made up of two parts: FPGA configuration and processor configuration. FPGA configuration uses data in the ROM to configure the FPGA. A processor configuration sets the processor into a standard state by writing into the DSP internal registers of the EMIF. Then it configures the FPGA from the data held in the flash ROM.

Note that two control register bits are needed for this purpose, one to put the FPGA into a ‘waiting for configuration’ state, and another to actually transfer the configuration data. The PROG pin (causes the FPGA to enter the non-configured state) is accessed at address 0x6C02000X. Writing to address 0x6C020000 will assert this pin, and address 0x6C0200001 will de-assert this pin.

The configuration data clock is accessed at address 0x6C080001. Each bit of the FPGA’s configuration bit-stream must be serially clocked through this address.

The bootloader is executed. It will continually check the six comports until data appears on one of them. This will next load a program in boot format from this comport. Note that the bootloader will not read data arriving on other comports. Finally the control is passed to the loaded DSP application.

The DSP will take approximately about 1000ms to configure the FPGA following reset, assuming a 600MHz clock. The external devices implemented in the FPGA (such as comports) must not be used during this configuration.

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It is safest to wait for the configuration to complete. Note that comports will appear to be "not ready" until the FPGA has been configured.

The FPGA programming algorithm is not described here. It can be found in the boot code.

EMIF Control Registers

The DSP has two external memory interfaces (EMIF) that are 64 bits wide and 16 bits wide.

The DSP contains several registers that control the external memory interface (EMIF). A full description of these registers can be found in the

DSP C6000

Peripherals Reference Guide.

The standard bootstrap will initialise these registers to use the following resources:

Memory space

(EMIFA)

Internal program memory (1MB) 0x00000000 - 0x000FFFFF CE0 ZBTRAM (2x 8MB sections) 0x80000000 - 0x807FFFFF CE1 Virtex 0x90000000 - 0x900FFFFF

Memory space

(EMIFB)

CE1 1st/3rd section of flash

CE2 2nd/4th section of flash

Resource Address range

0x64000000 – 0x641FFFFF

(2MB each)

0x68000000 – 0x681FFFFF