Sundance SMT363XC2 User Manual
SMT363XC2
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Version 2.2 Page 2 of 27 SMT363XC2 User Manual
Revision History
Date Comments Engineer Version
14/11/03 First release JPA 1.0.0
02/12/03 Added addressing mode section (LED Setting)
JPA 1.0.1
Updated ComPort section
20/10/04 Updated block diagram.
JPA 1.0.2
Removed endianess section
Updated LED section
Replaced Timer and interrupt section by
Interrupt section
07/06/05 Added: power consumption SM 1.0.3
09/08/05 Update: Support the firmware V1.1 SM 2.0
05/12/05 Updated LED descriptions. GP 2.1
29/11/07 Removed HPI connection from block diagram. GP 2.2
Version 2.2 Page 3 of 27 SMT363XC2 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Contacting Sundance ................................................................................................. 5
Notational Conventions .............................................................................................. 6
DSP ........................................................................................................................ 6
SDB ........................................................................................................................ 6
SHB ........................................................................................................................ 6
Register Descriptions.............................................................................................. 6
Outline Description ..................................................................................................... 7
Intended Audience...................................................................................................... 7
Block Diagram ............................................................................................................ 8
Architecture Description ............................................................................................. 9
NET+50 ...................................................................................................................... 9
DSP ............................................................................................................................ 9
Boot Mode............................................................................................................... 9
DPRAM ................................................................................................................. 10
EMIF Control Registers......................................................................................... 10
CE1 - IO Control ................................................................................................... 11
SDRAM..................................................................................................................... 11
FLASH...................................................................................................................... 11
RS232 ...................................................................................................................... 12
Serial ports ............................................................................................................... 12
FPGA........................................................................................................................ 12
Version control ...................................................................................................... 12
Firmware versions .................................................................................................... 12
Reprogramming the firmware and boot code............................................................ 12
Comports.................................................................................................................. 13
SHB .......................................................................................................................... 13
Architecture........................................................................................................... 13
Global bus ................................................................................................................ 13
Version 2.2 Page 4 of 27 SMT363XC2 User Manual
LED Setting .............................................................................................................. 14
LED Register......................................................................................................... 14
CONFIG & NMI......................................................................................................... 15
Config Register ..................................................................................................... 15
Timer ........................................................................................................................ 16
Timer Control Register .......................................................................................... 16
IIOF interrupt ............................................................................................................ 17
Code Composer ....................................................................................................... 18
Application Development .......................................................................................... 18
SMT6400 .............................................................................................................. 18
SMT6060 .............................................................................................................. 18
3L Diamond........................................................................................................... 18
SMT6500 .............................................................................................................. 18
FPGA Memory Map.................................................................................................. 19
SHB pinout ............................................................................................................... 20
SHB generic pin-out.............................................................................................. 20
Jumper Pin-Outs....................................................................................................... 21
JP1 - NET+50 connections ............................................................................ 21
JP2 - Serial port header ................................................................................. 21
JP3 - Xilinx CPLD programming port. ............................................................ 22
JP4 - NetICE port........................................................................................... 22
LED Descriptions...................................................................................................... 23
Mechanical Configuration ......................................................................................... 24
Operating Conditions................................................................................................ 25
Safety.................................................................................................................... 25
EMC...................................................................................................................... 25
General Requirements.......................................................................................... 25
Power Consumption.............................................................................................. 25
Bibliography.............................................................................................................. 26
INDEX ...................................................................................................................... 27
Version 2.2 Page 5 of 27 SMT363XC2 User Manual
Contacting Sundance
You can contact Sundance for additional information by login onto the Sundance
support forum. Please note that first users have to register first.
Version 2.2 Page 6 of 27 SMT363XC2 User Manual
Notational Conventions
DSP
The terms DSP, C6713 and TMS320C6713 will be used interchangeably throughout
this document.
SDB
The term SDB will be used throughout this document to refer to the Sundance Digital
Bus interface.
SHB
The term SHB will be used throughout this document to refer to the Sundance Highspeed Bus interface.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
OFLAGLEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset
Version 2.2 Page 7 of 27 SMT363XC2 User Manual
Outline Description
The SMT363XC2 is an Ethernet module, size 1 TIM offering the following features:
NetSilicon ARM-chip Net+50
TMS320C6713 processor running at 225MHz
Six Comports
64MB of SDRAM
8MB Flash ROM
Global Bus connector
High bandwidth data I/O via 2 Sundance Digital Buses (SDB)
Intended Audience
There are two existing versions of the firmware for the SMT363XC2. These two
versions differ by the number and the type of communication resources (comport and
SDB interfaces) provided.
For each of the versions of the different firmware is loaded in the FPGA:
- Firmware version 1.0 or
- Firmware version 1.1
This user manual covers the version 1.1 of the firmware for the SMT363XC2
implemented with the model described in the SMT6500 help file.
The changes between the firmware version 1.0 and version 1.1 are described in the
section Firmware versions.
Version 2.2 Page 8 of 27 SMT363XC2 User Manual
Block Diagram
The following drawing shows the block diagram of the SMT363XC2 module.
The main components of the SMT363XC2 are:
- A Texas Instruments DSP
- One Xilinx Virtex-II FPGA
- One NetSilicon ARM Net+50 device with integrated MAC controller for
connection to an Ethernet network.
- 16/64MB of SDRAM
DSP and
FPGA PSU
4 LEDs &
4 I/O pins
JTAG Header
Sundance High-speed
Bus
60-way Samtec
J1 Top Primary TIM
Global Bus
J3 Global Expansion
Connector
Connector
Comm-Port 3
24 I/O pins
2x Comm-Ports/SDL
Xilinx FPGA
Virtex-II
1.5V
74 I/O pins
J2 Bottom Primary TIM
15 I/O pins
Timer,& C ontrol
48 I/O pins
4x Comm-Port/SDL
Connector
Comm-Port 1, 2, 4
32-bit EMIF
Dual Port
RAM
8M bytes Flash
16/64M bytes
SDRAM
2 x (4/16M x 16)
'C6211/6711/6713
DSP
NET+50
16M bytes SDRAM
2 x (4M x 16)
McBSP,
GPIO, LEDs
RJ45, RS232,
LEDs
Figure 1: SMT363XC2 block diagram
Version 2.2 Page 9 of 27 SMT363XC2 User Manual
Architecture Description
NET+50
The NET+50 is a cost-effective, high-performance 32-bit network attached
microprocessor developed especially for high-bandwidth applications in Intelligent
Networked Devices. Based on ARM's architecture, it integrates 10/100Base-T
Ethernet MAC with an MII interface, a distributed 10-channel linking DMA controller
and a memory controller supporting all of the popular memory devices in use today.
This device is connected directly to an Intel LXT971 PHY device, which provides an
IEEE 802.3 compatible 10Base-T and 100Base-T physical layer interface.
Also, directly connected to the NET+50 are 16Mbytes of SDRAM, an RS232 level
converter and a 128KB Dual Port RAM (DPRAM).
LEDs 4 and 4 are controlled via PORTA bits 0 and 1.
DSP
The Texas Instruments DSP can run at up to 225MHz. The DSP is doted of 16MB
(optional 64MB) of SDRAM.
The DSP is a TMS320C6713 type.
An on-board 37.5MHz crystal oscillator provides the clock used for the DSP which
then multiplies this by for input to the DSP. DSP internally multiplies this up to the
required frequency, using a PLL.
Boot Mode
The DSP is connected to the on-board flash ROM that contains the Sundance
bootloader and the FPGA bitstream.
Following reset, the DSP will automatically load the data from the flash ROM into its
internal program memory at address 0 and then start executing from there. All this
code is the Sundance bootloader, and it is made up of three parts: FPGA
configuration, processor configuration and the Comport boot procedure. FPGA
configuration uses data in the ROM to configure the FPGA. A processor configuration
sets the processor into a standard state, copies its comport boot procedure into a
dual-port RAM (DPRAM) implemented in the FPGA, and releases the NET+50 chip
from reset. The Net+50 chip is configured to boot from this DPRAM.
The bootloader is executed. It will continually check the six comports until data
appears on one of them. This will next load a program in boot format from this
comport. Note that the bootloader will not read data arriving on other comports.
Finally the control is passed to the loaded DSP application.
It is safest to wait for the configuration to complete. Note that comports will appear to
be "not ready" until the FPGA has been configured.
The FPGA programming algorithm is not described here. It can be found in the boot
code.
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