Sundance SMT362 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Form : QCF42
Date : 6 July 2006
Unit / Module Description:
Unit / Module Number:
Document Issue Number:
Issue Date:
Original Author:
User Manual
What is this all about?
SMT362
2.2
th
29
April 2009
Graeme Parker
for
SMT362
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2006
User Manual SMT362 Last Edited: 29/04/2009 08:56
Revision History
Issue Changes Made Date Initials
1.0 First release. 5/2/07 GKP
1.1 Update 20/6/07 GKP
1.1.1 Added CCS basic info. 2/8/07 GKP
1.2 Added default firmware links configuration 2/6/08 E.P
1.3 Added McBSP connectivity detail. 21/7/08 GKP
1.4 Added FPGA pin-out 22/7/08 GKP
2.0 Major update to include missing detail from the
technical specification.
2.1 Corrected PHY references. 17/12/08 GKP
2.2 Default for McBSP1 or GPIO is GPIO. 29/4/09 GKP
3/10/08 GKP
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Table of Contents
1 Introduction.....................................................................................................................4
2 Related Documents ........................................................................................................5
3 Acronyms, Abbreviations and Definitions ...................................................................5
4 Functional Description...................................................................................................6
4.1 Block Diagram ............................................................................................................6
4.2 Module Description.....................................................................................................7
4.2.1 Mechanical Interface..............................................................................................7
4.2.2 Processor...............................................................................................................7
4.2.3 Flash ......................................................................................................................7
4.2.4 DSP Reset .............................................................................................................7
4.2.5 DSP Boot ...............................................................................................................9
4.2.6 Host Port Interface (HPI) .......................................................................................9
4.2.7 Virtex 4 FX FPGA ................................................................................................10
4.2.8 GPIO (General Purpose I/O) ...............................................................................13
4.2.9 LEDs ....................................................................................................................14
4.2.10 Ethernet ...............................................................................................................15
4.2.11 RapidIO and RSLs...............................................................................................17
4.2.12 McBSP & Timers .................................................................................................18
4.2.13 Power Supplies....................................................................................................18
5 Footprint........................................................................................................................19
5.1 Top View ..................................................................................................................19
5.2 Bottom View .............................................................................................................20
6 Support Packages ........................................................................................................ 21
6.1 Code Composer Studio ............................................................................................21
6.2 3L Diamond ..............................................................................................................21
7 Physical Properties ......................................................................................................22
8 FPGA Pin-out (ucf) .......................................................................................................23
9 Safety.............................................................................................................................30
10 EMC ..............................................................................................................................30
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1 Introduction
The SMT362 is a dual processor module. Each TMS320C6455 processor runs at up to
1GHz. This provides a module performance of up to 16GIPS.
Each processor has independent access to 256Mbytes of DDR2 memory.
A single 4Mbyte flash memory device is directly connected to the primary DSP (DSP A). This
device contains the DSP boot code and FPGA (Virtex-4) configuration.
The secondary DSP (DSP B) boots from its Host Port Interface, which is directly connected
to DSP A.
The FPGA provides 6 TIM compatible comm. ports, 2 Sundance SHBs, up to 16 RSLs, and
other minor functions. The FPGA can be easily customised.
The SMT362 could be used in applications where the FPGA does the pre-processing, the
first DSP the ‘Input Signal Processing’, the second DSP does ‘Output Signal Processing’,
and the FPGA does the final post-processing.
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2 Related Documents
TI TMS320C6455 material (http://focus.ti.com/docs/prod/folders/print/tms320c6455.html).
Sundance SHB specification. (ftp://ftp2.sundance.com/Pub/documentation/pdf-
files/SHB_Technical_Specification_v1_0.pdf)
Sundance RSL specification. (http://www.sundance.com/docs/RSL - Technical Specification
Rev01 Iss03.pdf)
TI TIM specification & user’s guide. (ftp://ftp2.sundance.com/Pub/documentation/pdf-
files/tim_spec_v1.01.pdf)
3 Acronyms, Abbreviations and Definitions
A list of acronyms etc (http://www.sundance.com/web/files/static.asp?pagename=acc).
User Manual SMT362 Last Edited: 29/04/2009 08:56
4 Functional Description
4.1 Block Diagram
2xLED
256M bytes DDR2
4M bytes
Top TIM Connector
2x (64Mx16)
flash
ComPorts 0 & 3
32-bit
8-bit data
C6455 1GHz
EMIF
64-bit
DSP A
Host Port - 16-bit
McBSP
FPGA
Virtex4 XC4VFX60
2xLED
32-bit
DSP B
C6455 1GHz
EMIF
McBSP
1.2V core
FF1152 package
64-bit
256M bytes DDR2
Bottom TIM Connector
2x (64Mx16)
ComPorts 1, 2, 4 & 5
4xLED
3x RSL
Connectors
2x SHB
12 lanes
Connectors
JTAG Header
4x LVTTL I/O Pins
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4.2 Module Description
4.2.1 Mechanical Interface
This module conforms to the TIM standard for single width modules. It requires an additional
3.3V power supply (as present on all Sundance TIM carrier boards) that must be provided by
the two diagonally opposite mounting holes.
4.2.2 Processor
The module incorporates two TMS320C6455 DSPs.
A JTAG interface is provided to enable application debugging via a suitable JTAG controller
and software. The DSPs’ JTAG interfaces are chained and available only on the Top TIM
connector. Typically, the JTAG controller this will be an SMT107 or 310/Q and TI Code
Composer Studio. This is an invaluable interface that enables the application programmer to
quickly debug a ‘chain’ of processors in single or multi-processor situations.
The DSPs have two external memory interfaces. One connects directly to the DDR2 (2
devices of 128M bytes clocked at 250MHz:DDR2-500) and the other (EMIFA, clocked at
133MHz) is used to interface to the remaining peripherals.
Each DSP provides 4 chip selects (numbered 2-5) on its EMIFA interface. The function of
each is shown below;
Chip
select
CE2 A0000000 FPGA FPGA
CE3 B0000000 Flash Unused
CE4 C0000000 HPI of DSPB Unused
CE5 D0000000 FPGA configuration Unused
Separate to the EMIFA, the DSP provides an interface solely for the connection of DDR2
memory. This is addressed as shown here;
DDR2 E0000000 DDR2 SDRAM DDR2 SDRAM
4.2.3 Flash
A 4Mbyte flash memory is provided with direct access by DSP A. This device contains boot
code for the DSP and the configuration data for the FPGA.
This device is directly connected to DSP A. This is an 8-bit wide device.
The flash is mapped with address bits 0 & 1 (byte addressing) connected to the top address
of the flash so a sector erase will need to erase 4 sectors at once. This is equivalent to
having a flash of 32 128Kwords sectors (instead of 128 32Kwords sectors). The flash is only
accessible byte-wise so it gives a total capacity of the flash of 4MB.
Base Address
(hex)
DSPA DSPB
4.2.4 DSP Reset
The DSPs’ configuration is determined during the reset process. The state of the EMIF
address lines is examined, and this determines the on-chip peripheral status.
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The following table details this;
EMIF
A
0 Latched at reset. Not used on
the 362.
1 Latched at reset. Not used on
Comment EMIF A Comment
10 Pull-up with 1k0. Used to select
MAC with an RGMII interface.
11 Pull-up via 1k0.
the 362.
2 Latched at reset. Not used on
the 362.
12 UTOPIA or EMAC select.
Internal pull-down selects
EMAC.
3 Pull-up via 1k0. 13 Internal pull-up selects little
endian operation.
4 GP01 function. Connected to
CPLD via 1k0. A ‘0’ (default)
14 Internal pull-down selects 16 bit
HPI operation.
makes this an I/O pin. A ‘1’
enables the SYSCLK3 signal to
be output.
5 McBSP1 or GPIO selection.
Connected to the CPLD via 1k0.
A ‘1’ enables the McBSP
(default if GPIO).
15 Connected to CPLD via 1k0. A
‘0’ selects external clock for
EMIF. A ‘1’ selects SYSCLK3/8
as EMIF clock.
6 NC – PCI speed. 16 Internal pull-down. Set to ‘0’ for
DSPA. Set to ‘1’ for DSPB.
Together with EMIFA17-19, this
sets the boot mode.
7 NC – internal pull-down. 17 Internal pull-down.
8 NC – PCI auto-init. 18 Internal pull-down. Set to ‘1’ for
DSPA. Set to ‘0’ for DSPB.
9 Pull-up with 1k0. Used to select
19 Internal pull-down.
MAC with an RGMII interface.
Boot mode is the 4-bit value from EMIFA[19:16]. This is 0100 for DSPA (ROM boot) and
0001 for DSPB (HPI boot).
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4.2.5 DSP Boot
When the module is reset, both DSPs come out of their reset state. DSPA will begin
execution of code stored in the flash memory. DSPB is set to boot from host port, and will
thus wait until is has had its boot code loaded by DSPA. The DSPA boot code (factory
programmed by default) will load the FPGA configuration (again from flash), boot DSPB over
the EMIF to host port interface, perform any necessary initialisation and then enter a
ComPort boot sequence. The ComPort boot involves polling the ComPort status register(s)
and downloading code from the first active port.
DSPB, when booted, will simply enter the ComPort boot sequence after initialising any of its
internal devices.
4.2.6 Host Port Interface (HPI)
The HPI of DSPA is not connected, and DSPB’s is connected to the EMIF of DSPA.
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