Sundance SMT361Q User Manual
SMT361Q
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 1.0.2 Page 2 of 24 SMT361Q User Manual
Revision History
Date Comments Engineer Version
22/04/04 First rev, based on 365 J.V. 1.0.0
01/06/04 FPGA clock rate compared with DSP clock rate
J.V. 1.0.1
added
03/03/06 Minor changes, and ComPorts architecture SM 1.0.2
Version 1.0.2 Page 3 of 24 SMT361Q User Manual
Table of Contents
Revision History....................................................................................................... 2
Contacting Sundance............................................................................................... 4
Notational Conventions ........................................................................................... 5
C60 ......................................................................................................................... 5
Register Descriptions.............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 7
TMS320C6416 ........................................................................................................... 8
DSP resources and control..................................................................................... 8
Clock settings.......................................................................................................... 9
Boot Mode............................................................................................................... 9
EMIF Control Registers......................................................................................... 10
FLASH ..................................................................................................................... 11
FLASH Paging...................................................................................................... 11
Virtex-II FPGA ......................................................................................................... 11
External Clock......................................................................................................... 12
Version control....................................................................................................... 12
Reprogramming the firmware and boot code ...................................................... 12
FPGA resources ..................................................................................................... 13
ComPorts.............................................................................................................. 13
Interrupts............................................................................................................... 14
SDB ...................................................................................................................... 14
SDB Clock selection.......................................................................................... 14
Global bus............................................................................................................. 14
CONFIG & NMI..................................................................................................... 14
Timer..................................................................................................................... 14
IIOF interrupt......................................................................................................... 14
LED....................................................................................................................... 15
TTL pins................................................................................................................ 15
Code Composer Studio .......................................................................................... 16
Version 1.0.2 Page 4 of 24 SMT361Q User Manual
Operating Conditions............................................................................................. 16
Safety.................................................................................................................... 16
EMC...................................................................................................................... 16
General Requirements.......................................................................................... 16
Power Consumption.............................................................................................. 17
PCB description...................................................................................................... 17
Component Side................................................................................................... 17
Connector Pinouts ................................................................................................. 19
FPGA PROG Pin Control (JP1) ............................................................................ 19
FPGA JTAG (JP2) ................................................................................................ 19
TTL (JP3).............................................................................................................. 19
SHB pinout............................................................................................................ 20
FPGA Pinout ........................................................................................................... 23
Bibliography............................................................................................................ 23
Index........................................................................................................................ 24
Contacting Sundance
You can contact Sundance for additional information by login onto the Sundance
support forum.
Version 1.0.2 Page 5 of 24 SMT361Q User Manual
Notational Conventions
C60
The terms C60, C64xx and TMS320C64xx will be used interchangeably throughout
this document.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
LEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
Version 1.0.2 Page 6 of 24 SMT361Q User Manual
Outline Description
The SMT361Q is Sundance’s 3rd generation of Texas Instruments ‘C6x DSP TIM
(
Texas Instruments Module). This module uses 4 TMS320C6416 DSPs which have
clock speeds of up to 720MHz.
The module also includes a
Xilinx Virtex-II (XC2V2000FF896) FPGA which is
configured to provide ‘C4x style ComPorts, a TIM compatible enhanced global bus,
two
Sundance High-Speed Busses (SHBs) and other control functions.
The SMT361Q is, from the user’s perspective, a multi-DSP version of the
SMT361A
Module and a system can be designed with a mixture of SMT361s and SMT361Qs
on the same Module Carrier.
The SMT361Q is supported by the TI
Code Composer Studio and 3L Diamond
RTOS to enable full MultiDSP systems with minimum efforts by the programmers.
Version 1.0.2 Page 7 of 24 SMT361Q User Manual
Block Diagram
HPI
'C64xx
DSP
D
voltage
convertors
1.5V & 1.2V
4 LEDs &
4 I/O pins
JTAG Header
Sundance High-
Speed Bus
60-way x2
120 I/O Pin s; 16 -bit D a ta
J3 Global Expansion
Connector
EMIFB
'C64xx
DSP
HPI
EMIFB
'C64xx
DSP
HPI
EMIFB
'C64xx
DSP
EMIFA EMIFA EMIFA EMIFA
HPI
32 bit
32 bit
32 bit
32 bit
16 bit
C
B
A
Serial port
Oscillators
Flash (CE1)
FPGA
(XC2V2000)
Virtex-II, FF896
618 I/O Pins
1.5V
Control
Timer &
Global Bus
24 I/O pins
74 I/O pins
24 I/O pins
2x Comm-Ports
J2 Bottom Primary TIM
Connector
Comm-Port 1 & 4
2x Comm-Ports
J1 Top Primary TIM
Connector
Comm-Port 0 & 3
Architecture Description
The SMT361Q TIM consists of a Texas Instruments TMS320C6416 running at
600MHz.
A Field Programmable Gate Array (FPGA) is used to manage Global bus accesses
and implement four ComPorts and two Sundance High Speed Busses. This is a
Xilinx Virtex-II device.
Version 1.0.2 Page 8 of 24 SMT361Q User Manual
TMS320C6416
The processor will run with zero wait states from internal SRAM.
The following table shows the main DSP characteristics.
Feature C6416
DMA / McBSP / Timer 64/3/3
On-chip memory 1056k bytes
Speed 1GHz
Others UTOPIA
Viterbi and Turbo decoders
The SMT361Q implementation using this DSP provides interfaces using the EMIFs
(External Memory Interfaces A & B), timers and JTAG.
The JTAG interface is provided to enable application debugging via a suitable JTAG
controller and software. Typically, this will be a
SMT310 and TI Code Composer
Studio. This is an invaluable interface that enables the application programmer to
quickly debug a ‘chain’ of processors in single or multi-processor situations.
Each DSP’s EMIFA is used to connect to the Virtex-II FPGA.
The Flash ROM is connected via DSP_A, EMIFB as a 16-bit device.
DSP resources and control
The DSP resources available to each DSP are the following:
Ressource DSP_A DSP_B DSP_C DSP_D
External
1 1 1 1
ComPort
Internal ComPort 5 5 5 5
External SHB 2 0 0 0
Global bus 1 0 0 0
Flash 1 0 0 0
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