Sundance SMT361 User Manual
SMT361
SMT361A
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 2.7 Page 2 of 23 SMT361 SMT361A User Manual
Revision History
Date Comments Engineer Version
16/1/02 First rev, based on 335 GP 1.0.0
9/5/02 Drawing corrections and jumper function
GP 1.1.0
updates
7/5/02 Memory mapping corrections, New firmware
E.P 2.0
memory mapping, CCS problems
11/05/02 Additional warning concerning DMA support E.P 2.1
03/01/03 Addition of IIOF paragraph. Update of mapping
E.P 2.2
table
30/01/03 New firmware 1.8 J.V. 2.3
13/08/03 Firmware version display and update via the
J.V. 2.5
SMT6001 utility.
Comport notation updated and reference to
support system added.
26/08/03 Version updated at the top of each file J.V. 2.6
26/09/03 SMT361A description added J.V. 2.7
It is important that you use the correct version of the firmware; you should use the
firmware provided with the latest SMT6001.
Sundance’s support forum http://support.sundance.com/
Version 2.7 Page 3 of 23 SMT361 SMT361A User Manual
Table of Contents
Revision History ....................................................................................................... 2
Contacting Sundance............................................................................................... 4
Notational Conventions ........................................................................................... 5
SMT361 .................................................................................................................. 5
C64xx...................................................................................................................... 5
Register Descriptions.............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 8
TMS320C64xx ........................................................................................................... 9
Boot Mode............................................................................................................... 9
EMIF Control Registers.......................................................................................... 10
SDRAM ................................................................................................................. 10
FLASH .................................................................................................................. 10
Version control ....................................................................................................... 11
Reprogramming the firmware and boot code ...................................................... 11
Interrupts................................................................................................................. 11
Communication ports ............................................................................................ 11
SDB.......................................................................................................................... 12
SDB Clock selection ............................................................................................. 12
Global bus............................................................................................................... 12
LED Setting ............................................................................................................. 13
LED Register......................................................................................................... 13
CONFIG & NMI ........................................................................................................ 13
Timer........................................................................................................................ 13
IIOF interrupt........................................................................................................... 13
Code Composer...................................................................................................... 14
Application Development....................................................................................... 15
Operating Conditions............................................................................................. 16
Safety.................................................................................................................... 16
EMC...................................................................................................................... 16
Version 2.7 Page 4 of 23 SMT361 SMT361A User Manual
General Requirements.......................................................................................... 16
Power Consumption.............................................................................................. 17
Connector Positions .............................................................................................. 17
Serial Ports & Other DSP I/O ................................................................................. 18
FPGA and CPLD JTAG........................................................................................... 18
Virtex Memory Map................................................................................................. 19
SDB Pin-Out ............................................................................................................ 21
Bibliography............................................................................................................ 22
Index ........................................................................................................................ 23
Contacting Sundance
You can contact Sundance for additional information log onto Sundance’s support
forum
http://support.sundance.com/
Version 2.7 Page 5 of 23 SMT361 SMT361A User Manual
Notational Conventions
SMT361
Throughout this document the term SMT361 will usually be used to refer to all
processor variant including the SMT361A. It should be clear from the context when a
distinction is being drawn between the types of module.
C64xx
The terms C64xx and TMS320C64xx will be used interchangeably throughout this
document.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
OFLAGLEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
Version 2.7 Page 6 of 23 SMT361 SMT361A User Manual
Outline Description
The SMT361 is a C64xx-based size 1 TIM offering the following features:
SMT361: TMS320C64xx processor running at 600MHz
Four 20MB/s communication ports (ComPorts)
32MB of SDRAM (150MHz)
2MByte Flash ROM for boot code and FPGA programming
Global expansion connector
High bandwidth data I/O via 2 Sundance Digital Buses (SDB).
The SMT361A includes the same features with a TMS320C64xx processor
running at 720MHz. All the external interface are running at 120MHz instead of
100MHz.
Version 2.7 Page 7 of 23 SMT361 SMT361A User Manual
Block Diagram
J1 Top Pri mary TIM
JTAG Header
Connector
Comm-Port 0 & 3
26 I/O pins
2x Comm-Ports/SDL
Linear regulat ors
1.5V & 1.2V
15 I/O pins
Timer,& Control
4 LEDs &
4 I/ O pins
McBSP0
McBSP/Ut opia/
GPI O
4 LEDs
Sundance Digi tal Bus
40- way ODU x2
46 I/ O Pins; 16-bit Data
J3 Global Expansi on
FPGA Controller
Connector
Vir tex-II, FG456
324 I/ O Pins
1.5V
74 I/O pins
Global Bus
52 I/O pins
2x Comm-Port/SDL
J2 Bott om Primary TIM
Connector
Comm-Port 1 & 4
92 pins
'C64xx
DSP
525 pins
32 M by tes SDRAM ( EMI FA)
4 x K4S641632 (4M x 16)
Flash ( EMIFB CE1)
Start-up mode sel ecti on.
Oscil lator s
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