Sundance SMT358 User Manual
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Version 2.5 Page 2 of 25 SMT358 User Manual
Revision History
Date Comments Engineer Version
10 Feb
1999
20 Sept
Overall update to SMT358 User Manual E.Puillet Version1.1
1999
12 Oct
1999
08 Nov
1999
22 Nov
1999
08 Dec
1999
07 Jan
2000
28 Jan
2000
15 Feb
2000
SDB connector Pins renamed.
Addition of Global Clock Buffer signal assignments
Modification of the FSM for the FPGA
Reconfiguration.
Addition of TIM Connectors and mounting
holes’ position
Clarification of the FSM and explanations for
the FPGA Configuration and Reconfiguration.
SDB bi-directional clock drawing in Figure 4
corrected
SDB Connector Pins correspondence between
SMT373 and SDB standard.
Description of the Installation and configuration
of the SMT358
Initial Release
E.Puillet Version1.0
E.Puillet Version1.2
E.Puillet Version
1.3
E.Puillet Version
1.4
E.Puillet Version
1.5
E.Puillet Version
1.6
E.Puillet Version
1.7
E.Puillet Version
1.8
07 March
2000
22 March
2000
20 July
2000
26
October
2000
06
January
2001
23
January
2001
Addition of a WARNING for customers with
SMT358 boards delivered before 07.03.00.
Addition of the memory addressing scheme
for a memory Bank.
Figure 3 modification of SDB bi-directional
signal number for SDB C and D
Table 3 is modified and becomes Table
1.General modifications to adapt the User
Manual to VirtexE
Table 1 is modified to remove parts, which
won’t be fitted on SMT358. Addition of new
conversion software.
Addition of power consumption considerations
for the SMT358
E.Puillet Version
2.0
E.Puillet Version
2.1
E.Puillet Version
2.2
E.Puillet Version
2.3
E.Puillet Version
2.4
E.Puillet Version
2.5
Version 2.5 Page 3 of 25 SMT358 User Manual
The FPGARESET signal must be tied to ground in any FPGA design
for SMT358s received before 07.03.00.
SMT358s received after 07.03.00 see the FPGA constraint file
modified for Comm-Port 3 and any FPGA design must use the
FPGARESET signal as a global reset active low.
Version 2.5 Page 4 of 25 SMT358 User Manual
Table of Contents
Revision History..........................................................................................................2
Table of Contents........................................................................................................4
Scope..........................................................................................................................6
SMT358 Versions....................................................................................................... 6
SMT358 Power consumption Considerations............................................................. 7
Technical description..................................................................................................8
On-board SRAM......................................................................................................9
Sundance Digital Bus (SDB).................................................................................11
SMT358-DSP Communication channels............................................................... 12
Sundance Datapipe Links..................................................................................... 13
FPGA ....................................................................................................................14
Global Clock Buffers..............................................................................................15
Installation.................................................................................................................16
Configuration ............................................................................................................16
Hardware Sequence of events..............................................................................16
At power-up....................................................................................................... 16
FPGA Reconfiguration..........................................................................................18
Once configured................................................................................................18
FPGA Reconfiguration in real time........................................................................ 18
Software tools ....................................................................................................... 19
The Bit to Dat Conversion..................................................................................20
The Dat to Obj conversion................................................................................. 20
Interface.................................................................................................................... 21
TIM Connectors’ Position..........................................................................................22
Version 2.5 Page 5 of 25 SMT358 User Manual
LIST OF FIGURES
FIGURE 1: SMT358 BLOCK DIAGRAM.............................................................................................................8
FIGURE 2: ZBT SRAM CLOCK SIGNAL............................................................................................................9
FIGURE 3: FPGA, MEMORY AND SDB COMMUNICATION CHANNELS .................................................10
FIGURE 4: MEMORY ADDRESSING ............................................................................................................... 11
FIGURE 5: FPGA-DSP COMMUNICATION CHANNELS...............................................................................13
FIGURE 6: GLOBAL CLOCK BUFFERS ASSIGNMENTS IN THE VIRTEX/E.............................................15
FIGURE 7: GLOBAL RESET ROUTING. USE OF FPGARESET AS A GLOBAL RESET FOR DESIGNS.. 17
FIGURE 8: FPGA RECONFIGURATION...........................................................................................................18
FIGURE 9: SMT358 LAYOUT............................................................................................................................21
FIGURE 10: TIM CONNECTORS’ POSITION..................................................................................................22
FIGURE 11: TIM DIMENSIONS AND MOUNTING HOLES POSITIONS .....................................................23
LIST OF TABLES
TABLE 1: VIRTEX/E-ZBT SRAM COMBINATIONS........................................................................................6
TABLE 2: SMT358 CONNECTOR REFERENCE TABLE................................................................................22
TABLE 3: 40 WAY SDB CONNECTOR PINS...................................................................................................24
TABLE 4: JTAG CONNECTOR..........................................................................................................................25
Version 2.5 Page 6 of 25 SMT358 User Manual
Scope
This document describes the architecture, the function, the use and the interface
considerations for the SMT358. This document is intended for both the users of the SMT358
and the designer who is interested in designing the FPGA provided on the Board.
SMT358 Versions
The SMT358 comes under 4 standard versions, highlighted in red in Table 1. A Virtex
or Virtex E is fitted and the ZBTSRAM is in the pipelined version.
The total amount of memory on the board is either 4 MBytes or 8 Mbytes or 16
Mbyte.
Depending on the amount of on-board memory required, the Virtex/E fitted on-board,
the SMT358 can be implemented in 18 subversions, which can be adapted to a wide
range of application needs and costs.
Other configurations are possible depending on the speed of the application, as
shown in Table 2 and Table 3.
Table 1 summarises the various board configurations offered.
SMT358
Virtex/E XCV400 XCV600 XCV800 XCV1000E
ZBT
SRAM
4MBytes SMT358-
400-4
8 MBytes SMT358-
400-8
16
MBytes
SMT358-
400-16
SMT358-
600-4
SMT358-
600-8
SMT358-
600-16
SMT358-
800-4
SMT358-
800-8
SMT358-
800-16
SMT358-
1000E-4
SMT358-
1000E-8
SMT358-
1000E-16
Table 1: Virtex/E-ZBT SRAM Combinations
Version 2.5 Page 7 of 25 SMT358 User Manual
SMT358 Power consumption Considerations
The SMT358 power consumption is mostly dependant on the Virtex fitted and its
usage.
When using a S MT3581000E, suff icient cooling is provid ed on-board for t he voltage
regulator and for the Virtex 1000E, nevertheless a correct airflow MUST prevail in
your PC.
The larger and the faster the Virtex FPGA design is, the higher the Virtex power
consumption is.
For example, considering a shift register using 50% of the LUTs of a Virtex 1000E at
100 Mhz with data toggling at every clock cycle will have the effect of drawing more
current than the voltage regulator can provide and will make the voltage regulator fail
(safely) and the FPGA will loose its configuration.
Therefore, we advice customers to use Xilin x power estimator to determine the worstcase power consumption of their design AND to consult.
The Excel program can be found at:
http://support.xilinx.com/support/techsup/powerest/virtex_power_estimator_v15.xls
The user guide on how to use this program can be found at:
http://support.xilinx.com/xapp/xapp152.pdf
Version 2.5 Page 8 of 25 SMT358 User Manual
Technical description
ZBT SRAM
ZBT SRAM
ZBT SRAM
ZBT SRAM
BANK1
40 way IDC
SDB_ConA
40 way IDC
SDB_ConB
40 way IDC
SDB_ConC
SDB A
SDB B
SDB C
BANK2
Memory Signals
XCVxxxxxBG560
FPGA
BANK3
Memory Signals
Com-Port 1,4
Control
D[31:0]
A[30:0]
BANK4
Bottom Primary
Connector
Global Bus
Connector
40 way IDC
SDB_ConD
SDB D
50MHz Oscillator
Config Control
Com-Port 3 Ctrl Com-Port 3 Data
Figure 1: SMT358 Block diagram
Config D[7:0]
Configuration Logic CPLD
IIOF2
H1
Com-Port 0
Top Primary
Connector
Com-Port 3
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