Sundance SMT356 User Manual
SMT356
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Version 2.1 Page 2 of 26 SMT356356 User Manual
Revision History
Date Comments Engineer Issue
19/9/2000 First draft GKP 1.0
21/9/2000 Second draft GKP 1.1
30/4/2001 Converted to new form and added spectrum GKP 2.0
22/2/2005 Clarified JP1 function GKP 2.1
The SMT356 is a size 1 TIM offering the following features;-
Four communications ports for control
8 channel, 14-bit simultaneous sample ADC
High bandwidth data output via a single 16-bit SDB (Sundance Digital Bus)
Notes:
Within the drawings, DIP Switch refers to Jumper Bank 1.
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Table of Contents
Revision History.......................................................................................................... 2
Notes:......................................................................................................................... 2
Table of Contents....................................................................................................... 3
Architecture Description ............................................................................................. 4
EMC ........................................................................................................................... 5
Power ......................................................................................................................... 5
ADC Sub-System ....................................................................................................... 6
Input Level.................................................................................................................. 6
Output Codes ............................................................................................................. 6
ADC Control ............................................................................................................... 7
Programmable Clock Divider...................................................................................... 8
Sample Clock Routing.............................................................................................. 10
Connector Position................................................................................................... 11
Jumper Bank JP1.................................................................................................. 11
Input Circuitry ........................................................................................................... 12
Virtex ........................................................................................................................ 13
SDB.......................................................................................................................... 13
SDB Pin-Out............................................................................................................. 14
Clock Enable ............................................................................................................ 16
Clock Source............................................................................................................ 16
Example Code.......................................................................................................... 18
Configure Virtex.................................................................................................... 18
General Operation Description.............................................................................. 21
Spectrum (typical)..................................................................................................... 26
Version 2.1 Page 4 of 26 SMT356356 User Manual
Architecture Description
The SMT356 (356) module is a single width TIM device.
It incorporates a Xilinx XCV300 Virtex FPGA.
Eight 14-bit ADCs interface to the Virtex device, together with six ‘C40 style comm
ports.
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EMC
This module is designed to operate from within an enclosed host system, which is
built to provide EMC shielding. Operation within the EU EMC guidelines is not
guaranteed unless it is installed within an adequate host system.
This module is protected from damage by fast voltage transients originating from
outside the host system which may be introduced through the output cables.
Short circuiting any output to ground does not cause the host PC system to lock up
or reboot.
Power
This module must be fixed to a TIM40 compliant carrier board. Additionally, a 3v3
power source must be provided to the fixings. This is normally achieved by means of
a power source provided directly through conducting pillars on the carrier board.
Power for the analog components on this module is provided by on-board dc-dc
converters. All of the analog circuitry is shielded on the top and bottom of the module
using custom RFI shielding cans.
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ADC Sub-System
This consists of 8 Analog Devices AD9240 converters. These provide an overall
system performance with an ENOB of 12 (minimum) for each of the eight channels.
All ADCs simultaneously sample using the same clock.
Input Level
The input to the ADC module is DC coupled with a pk-pk level of 2v. This is centred
about 0v.
Vmin=-1v
Vmax=+1v.
Output Codes
The converted samples are presented on the SDB connector as 16 bit offset binary.
Code 0x0000 is equivalent to –Vmax
Code 0x8000 is equivalent to 0V
Code 0xFFFC is equivalent to +Vmax
The two least significant bits of the output word are undefined and should be masked
by the user.
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ADC Control
All of the ADCs are controlled via one of the six available ‘C40 style comm ports. The
desired comm port must be selected using the jumper bank JP1.
JP1 – positions 5-7 Comm Port
7 6 5
ON ON ON 0
ON ON OFF 1
ON OFF ON 2
ON OFF OFF 3
OFF ON ON 4
OFF ON OFF 5
This interface contains a single control register. This controls the clock divider, clock
enable, ADC enable and the state of the four LEDs. This register is described here,
Control Register
Function
Data Bits
D7-0 Clock Divider
D15-8 ADC Enable
D19-16 LED4-1 control
D20 Clock enable
D21 Clock enable mode
D22 SDB mode
D23 Reset FIFO
D31-24 Sample count
Bit D20 of this register controls the ADC clock enable via software. A ‘1’ enables the
ADC, or generates a rising edge trigger (depending on clock enable mode). The
power-on state of this bit is ‘0’.
Bit D21 controls the clock enable mode. A ‘0’ selects latched counter mode, a ‘1’
selects direct control. The power-on state of this bit is ‘0’.
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D31-24 determines the number of samples in clock enable mode ‘0’. The range is
from 1-256. The value loaded into bits 31-24 is the required sample count –1. A value
of 0 gives 1 sample, a value of 0xFF gives 256 samples.
Note that the sample count should be changed before the acquisition is triggered.
Bits D15-8 control the enabled state of the 8 ADCs. The power-on state is a ‘1’ for
each bit, indicating that all channels are enabled. Setting a bit to a ‘0’ will remove that
ADC’s output from appearing in the SDB data stream.
Programmable Clock Divider
An 8-bit divider is provided which allows the ADC clock to be provided from a divided
clock. The following table shows the possible values,
Divider Value ADC Sample
Frequency (MHz)
Division
[External clock]
[Internal clock]
00
01
02
03
50
25
16.6
12.5
2
4
6
8
04 10 10
05 8.3 12
06 7.1 14
07 6.3 16
08 5.5 18
09 5 20
…
Sampling rates of 50, 25, 16.6 and 12.5 are not allowed.
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