Sundance SMT351T User Manual
Sundance Multiprocessor Technology Limited
SMT351T
Unit / Module Description: FPGA module
Unit / Module Number: SMT351T
Document Issue Number:
Issue Date:
Original Author: E.P
SMT351T User Guide
Form : QCF42
Date : 6 July 2006
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
SMT351T User Guide Last Edited: 04/09/2009 11:26:00
Revision History
Issue Changes Made Date Initials
1.0.0 First release 28/01/08 E.P
1.0.1 Typo corrections, fixed broken Hyperlinks, added
chapter
32H32H4.2.7 33H33HFPGA Bitstream formatting.
30/01/08 E.P
Added references to MIG tools.
1.0.2 Updated Figure 3, updated RSL, SLB descriptions 30/01/08 E.P
1.0.3 updated number of RSL links available per FPGA,
22/02/08 E.P
Top and Bottom View, SLB warning considering its
voltage level
1.0.4 updated DDR2SDRAm hyperlinks and added Xilinx
20/04/08 E.P
Answer record bug fixes for MIG2.0 generated
cores.
1.0.5 updated CPLD code to support multiboot option.
06/08/08 E.P
Switch settings updated as a consequence.
1.0.6 Addition of JTAG connector pinout. 03/12/08 E.P
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Table of Contents
1 Introduction ................................................................................................................ 6
2 Related Documents..................................................................................................... 7
2.1 Referenced Documents .............................................................................................7
2.2 Applicable Documents ..............................................................................................7
3 Acronyms, Abbreviations and Definitions ................................................................. 7
3.1 Acronyms and Abbreviations ...................................................................................7
3.2 Definitions .................................................................................................................7
4 Functional Description ............................................................................................... 9
4.1 Block Diagram...........................................................................................................9
4.2 Module Description.................................................................................................10
4.2.1 FPGA...................................................................................................................10
4.2.2 CPLD...................................................................................................................10
4.2.3 FLASH MEMORY..............................................................................................10
4.2.4 JTAG Header......................................................................................................11
4.2.5 FPGA Configuration schemes............................................................................11
4.2.6 FPGA Reset Scheme...........................................................................................12
4.2.7 FPGA Bitstream formatting ..............................................................................14
4.2.8 DDR2SDRAM .....................................................................................................14
4.2.9 Sundance Rocket io Serial Link ........................................................................16
4.2.10 Sundance Low voltage Bus ................................................................................16
4.2.11 TIM Connectors..................................................................................................17
4.2.12 DIP Switches ......................................................................................................17
4.2.13 Available clocks ..................................................................................................18
4.2.14 LEDs ...................................................................................................................20
4.2.15 Performance........................................................................................................20
4.3 Interface Description ..............................................................................................20
4.3.1 Power Budget .....................................................................................................20
5 Footprint ....................................................................................................................22
5.1 Top View..................................................................................................................22
5.2 Bottom View............................................................................................................23
6 Pinout.........................................................................................................................24
6.1 FPGA Pin allocation by bank .................................................................................24
6.2 SHB..........................................................................................................................33
6.3 SLB ..........................................................................................................................33
6.4 JTAG........................................................................................................................34
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7 Qualification Requirements ......................................................................................34
7.1 Qualification Tests..................................................................................................34
7.1.1 Meet Sundance standard specifications............................................................34
7.1.2 Speed qualification tests ....................................................................................34
7.1.3 Integration qualification tests ...........................................................................34
8 Support Packages ......................................................................................................34
9 Physical Properties ....................................................................................................35
10 Safety .........................................................................................................................36
11 EMC ...........................................................................................................................37
12 Ordering Information ................................................................................................37
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Table of Figures
Figure 1: Block Diagram ........................................................................................................9
Figure 2: CPLD state machine.............................................................................................13
Figure 3: FPGA connections to DDR2SDRAM....................................................................15
Figure 4: FPGA clock buffers usage.....................................................................................19
Figure 5: Top View................................................................................................................22
Figure 6: Bottom view ..........................................................................................................23
Figure 7: JTAG connector Pinout ........................................................................................34
Table of Tables
TTable 1: DIP switch SW1 position for special reset featureT ...............................................17
TTable 2: DIP switch SW1 position for the selection of the configuration bitstream sourceT
.......................................................................................................................................18
TTable 3: DIP switch SW1 position for the selection of the Flash erase & program
operations.
TTable 4: Coolrunner II resources summary.T........................................................................21
TTable 5:Coolrunner II pin resources.T ...................................................................................21
T .....................................................................................................................18
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1 Introduction
The SMT351T is an FPGA TIM module designed to be integrated in modular
systems.
It is designed to connect to the huge range of other TIM modules and carriers
developed by Sundance.
Sundance modular solutions provide flexible and upgradeable systems.
The SMT351T is a TIM module aimed at completing the range of Sundance
Virtex4 and Virtex5 modules like 5H5HHTSMT362TH6H6HHTSMT339TH, 7H7HHTSMT339TH.
It provides a communications platform between an XC5VSXT/LXT device and
• 2 banks of DDR2 SDRAM at a frequency of up to 250Mhz.
• 4 8H8HHTRSLTH, connectors (up to 4 times .4 MGTs)
• LVDS connections for high speed parallel connections
• LVTTL connections and connectors.
This variety of connectors and interfaces provides a wide range of development
options for designers to explore the capabilities of the comprehensive Sundance
TIM modules family.
This module conforms to the TIM standard (Texas Instrument Module, See 9H9HHTTI TIM
specification & User’s guideTH) for single width modules.
It sits on a carrier board.
The carrier board provides power (5V, 3.3V, +/-12V), ground, communication links
(Comport links or for some RSL links as well) between all the modules fitted and a
pathway to the host.
The SMT351T requires a 3.3V power supply (as present on all Sundance TIM
carrier boards), which must be provided by the two diagonally opposite mounting
holes.
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2 Related Documents
2.1 Referenced Documents
10H10HHTSundance SDB specificationTH
11H11HHT
SUNDANCE SHB specificationTH
Sundance SLB specificationTH
12H12HHT
Micron 13H13HHTDDR2SDRAM 1GbitTH (MT47H64M16BT-37E) or
Micron
15H15HHTSpansion S29GLXXXN flashTH
14H14HHTDDR2SDRAM 2GbitTH (MT47H128M16BT-37E) device
2.2 Applicable Documents
16H16HHTTI TIM specification & User’s guideTH
17H17HHT
Samtec QSH Catalogue pageTH
Virtex 5 User GuideH
18H18HH
3 Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
TIM Texas Instruments Module
TI© DSP Texas Instrument Digital Signal Processor
Xilinx© FPGA Xilinx© Field Programmable Gate Array.
DDR2SDRAM Dual Data Rate 2 SDRAM
CP ComPort. Communication interface
RSL Rocket Serial Link
SHB Sundance High-Speed Bus. Communication interface
3.2 Definitions
DSP Module
FPGA-only Module A TIM with no on-board DSP, where the FPGA provides all
Firmware A proprietary FPGA design providing some sort of functionality.
SMT351T User Guide Last Edited: 04/09/2009 11:26:00
Typically a TIM module hosting a TI DSP and, a Xilinx FPGA.
functionality.
Sundance Firmware is the firmware running in an FPGA of a DSP
module.
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4 Functional Description
The SMT351T provides a Virtex 5 FPGA, memory and IO connectors to allow the
development of applications ranging from Software defined Radio to MIMO, video,
Signal processing.
Typically, an ADC/DAC mezzanine can be fitted on the SLB connector and memory is
used to store burst data between the outside world/host/other TIMs, while the FPGA
implements functions on that data.
4.1 Block Diagram
Switch
JTAG Header
Xilinx Coolrunner II CPLD
XC2C256CP132 on
Comport3 and
Config&control
2 banks of
DDR2SDRAM
2x (64Mx16 or 128Mx16)
4 LEDs
Flash memory
11 I/O pins
204 I/O pins
J2 Bottom Secondary TIM
JTAG
Connector
ComPort/SDL 1 & 4
J1 Top Primary TIM
Connector
ComPort/SDL 0 & 3
FPGA
Virtex-5 FF1136
XC5V
SX50T/LX50T/
SX95T/LX110T
1.0V Core
1.8V/2.5V/3.3V I/O
RSL clock
Local clock
16 RocketIO links
20 differential pairs
40 TTL IOs
Sundance Rocket io
Serial Link (4 Conn.)
Sundance Low-voltage Bus
(1 Conn.)
ONLY with
LX160
Figure 1: Block Diagram
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4.2 Module Description
Figure 1 presents colour coded blocks regrouping components according to their functionality or
their nature.
The following paragraphs will detail each one of them, but first, here is a global description of each
block.
• Block1 and Block6 Xilinx Virtex 5 XC5VSXT/LXT and configuration scheme for the FPGA.
• Block2: DDR2SDRAM memory banks.
• Block3: IO connectors for general purpose or dedicated interfaces.
• Block4: 50MHz or 125MHz clocks.
• Block5: LEDs for development and in-use monitoring and general purpose use.
4.2.1 FPGA
Xilinx Virtex 5 XC5VSX50T, XC5VLX50T, XC4VSX95T or XC5VLX110T FPGA.
This device is packaged in a FF1136-pin BGA package.
4.2.2 CPLD
Xilinx Coolrunner II device H19H19HHTUXC2C256-7CP132CUTHH.
This device is packaged in a 132-ball BGA type package with a -7 speed grade.
It can be used to configure the FGPA via Comport 3, or from a configuration stored in flash
memory.
The flash memory is programmed using the CPLD and via the ComPort3.
4.2.3 FLASH MEMORY
20H20HHS29GL256N11TFI01H is a 256Mbit flash from Spansion.
It can be used to configure the FPGA at power up.
Flash accessed using Comport3 via the CPLD.
Flash programming selection via switch SW1 (See X87H87HTable 3X)
Software Library Support available from Sundance.
The code can run on Sundance DSP TIM or a Host.
All the flash functionalities are available.
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4.2.4 JTAG Header
The JTAG header is compatible with Xilinx H21H21HHTUParallel-IVUTHH cable signals.
The header is a custom header that plugs onto a custom cable that must be ordered at time from
Sundance.
This cable then plugs into the Xilinx parallel cable pod.
It supportsT code download (for the FPGA), FPGA configuration, Hardware and Software
Debugging tools for the Virtex-5.
This cable connects the parallel port/USB port of an engineer's Workstation/PC to the JTAG
chain of the SMT351T Module.
All the Xilinx devices from block1 are chained and accessible via this JTAG header.
4.2.5 FPGA Configuration schemes
Different schemes are available to provide maximum flexibility in systems where the
SMT351T is involved:
The FPGA configuration bitstream source is
• On Comport 3:
The CPLD is connected to the Comport 3 link of the SMT351T TIM connector. (See block1).
A switch is used to select Comport 3 as the link that will be used to receive the bitstream.
The CPLD allows for FPGA configuration in slave SelectMAP mode.
• Using the on-board Flash memory.
The CPLD monitors the configuration data between the Flash and the FPGA.
The FPGA configuration is operated in Slave SelectMap mode.
A switch is used to select the Flash as the source for the configuration bitstream.
• Using the on-board JTAG header and Xilinx JTAG programming tools.
The JTAG header is a H22H22HHTUParallel-IVUTHH Header.
Note: Using JTAG to configure the FPGA bypasses the CPLD which controls configuration.
The following section describes the CPLD role and the reset scheme used.
As the CPLD is bypassed when JTAG is used to configure the FPGA, it is necessary to adopt
one of the three following ways:
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• If your FPGA design does not implement comport3,
o do not use the Reset signal generated by the CPLD but use the TIM reset signal
as your design’s reset. You can use JTAG to configure your FPGA with your
application and the design will reset and run everytime you issue a new TIM
reset.
• If your design implements comport3
o Set the switch to configure the FPGA from flash after reset. In this way a default
bitstream being stored in flash will be loaded in the FPGA by the CPLD.
In this manner the CPLD has gone trhough the cycle of configuring the
FPGA and releases the reset (FPGAresetn)
Then you can reconfigure the FPGA via JTAG with your application.
o Set the switch to configure from comport 3. After reset, configure the FPGA via
JTAG and provide an end key word on comport 3 to the CPLD so that it releases
the Reset. (FPGAresetn).
4.2.6 FPGA Reset Scheme
The CPLD is connected to a TIM global Reset signal provided to the SMT351T via its primary
TIM connector pin 30. (See 23H23HHTI TIM specification & User’s guideH).
This signal goes to the CPLD and the FPGA.
Nevertheless as a general rule for good practice, the FPGA should not use this reset but should
use the reset signal generated by the CPLD.
The CPLD provides another signal called FPGAResetn that offers a better Reset control over
the FPGA.
At power up or on reception of a low TIM global Reset pulse, the CPLD drives the
FPGAResetn signal low and keeps it low.
This is used to keep the FPGA design in reset.
A new FPGA configuration bitstream can then be downloaded.
When the ENDKEY has been received, the CPLD drives FPGAResetn high.
Use FPGAResetn for the Global Reset signal of your FPGA
designs.
In this manner, you can control your FPGA design Reset activity and you will also avoid
possible conflicts on ComPort 3 if your FPGA design implements it.
(Comport3 is a communication resource shared by the CPLD and the FPGA. But only 1 entity
is allowed to use it at a time).
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