Sundance SMT351 User Manual

SMT351

User Manual

Version 1.6 Page 2 of 25 SMT351 User Manual

Revision History

Date Comments Engineer Version

28/07/04 First revision JPA 1.1 16/09/04 Added pin number for “JP1 pinout” section.

JPA 1.2

Updated connectors’ location section. 30/09/04 Updated software library section JPA 1.3 01/06/05 Added annexe 1.

JPA 1.4

Removed Sundance logo. 18/07/06 General update for release 2 of the firmware JPA 1.5 08/09/06 Minor changes added for the release of the

JPA 1.6

firmware for the SMT351-G.

Version 1.6 Page 3 of 25 SMT351 User Manual

Revision History.......................................................................................................... 2

Table of Contents....................................................................................................... 3

Introduction................................................................................................................. 7

Description.............................................................................................................. 7

Features.................................................................................................................. 7

Additional resources ............................................................................................... 7

Architecture description.............................................................................................. 8

SMT351 block diagram........................................................................................... 8

Block description..................................................................................................... 9

FPGA...................................................................................................................... 9

Memory................................................................................................................... 9

CPLD ...................................................................................................................... 9

Sundance High Speed Bus..................................................................................... 9

Comports ................................................................................................................ 9

TTL I/Os................................................................................................................ 10

LEDs..................................................................................................................... 10

JTAG..................................................................................................................... 10

Switch ................................................................................................................... 10

Using the SMT351.................................................................................................... 11

FPGA Configuration ................................................................................................. 12

Reset........................................................................................................................ 13

Functional description............................................................................................... 14

FPGA design overview.......................................................................................... 14

Memory compartments ......................................................................................... 15

Sundance High Speed Bus (SHB)........................................................................ 16

Registers............................................................................................................... 16

Clock structure...................................................................................................... 17

FPGA implementation .............................................................................................. 18

Language.............................................................................................................. 18

3L Diamond........................................................................................................... 18

Synthesis and Implementation tool ....................................................................... 18

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FPGA resource usage .......................................................................................... 18

Registers definition................................................................................................... 19

Control register (0x4) ............................................................................................ 19

Address register Low order 16-bits (0x5).............................................................. 19

Address register High order 16-bits (0x6) ............................................................. 19

Count register Low order 16-bits (0x7).................................................................. 19

Count register High order 16-bits (0x8)................................................................. 20

Repeat register (0x9)............................................................................................ 20

Application example ................................................................................................. 21

Connector Locations................................................................................................. 22

JP2 pinout................................................................................................................. 23

JP1 pinout................................................................................................................. 24

Physical Properties................................................................................................... 25

Version 1.6 Page 5 of 25 SMT351 User Manual

Table of Figures

Figure 1: SMT351 board block diagram ..................................................................... 8

Figure 2: SMT351 FPGA data flow........................................................................... 14

Figure 3: SMT351 state machine.............................................................................. 15

Figure 4: DDR SDRAM components compartments organization............................ 16

Figure 5: FPGA’s clock domains .............................................................................. 17

Figure 6: SMT351 connector locations..................................................................... 22

Figure 7: TTL I/Os (JP2) pinout................................................................................ 23

Figure 8: JTAG header (JP1) pinout......................................................................... 24

Tables of Tables

Table 1: LED description .......................................................................................... 10

Table 2: configuration comport selection.................................................................. 12

Table 3: TIM CONFIG feature: SW1 settings ........................................................... 13

Table 4: FPGA’s clock domains description ............................................................. 17

Introduction

Description

The SMT351 card is a TIM format memory module that is able to store up to 1GB of data at 400MB/s.

The module works in a similar way than a FIFO memory. The first data stored into module will be available in output.

SMT351 modules can be cascaded to extend storage capability. The module is based on DDR SDRAM memory components running at up to 133

MHz. DDR (Double Data Rate) SDRAM activates the data outputs on both the rising and falling edges of the system clock rather than on just the rising edge, potentially doubling the output.

A Xilinx Virtex-II Pro FPGA (or XC2VP20, or XC2VP30) controls input and output data flows on two Sundance High-speed Bus (SHB) connectors. This bus is compatible with a wide range of Sundance processor, converter and I/O modules

Features 2 x Sundance High-speed Bus (SHB) connectors 6 x comport connectors Xilinx VirtexII Pro FPGA XC2VP7 (or XC2VP20, or XC2VP30) 1GB Double Data Rate (DDR) SDRAM 133 MHz

Additional resources

SUNDANCE SHB specification TI TIM specification & user’s guide. Samtec QSH Catalogue page Micron DDR SDRAM webpage

Version 1.6 Page 8 of 25 SMT351 User Manual

Architecture description

SMT351 block diagram

Figure 1 shows a block diagram of the SMT351 board. Refer to the following section for additional information on the major blocks.

‘FPGA configured’

On-board Oscillator

4 LEDs + 4 TTL IOs

2 x Sundance High-speed

Bus Connectors

2 x RSL Connectors

(8 RSL Interfaces)

3 Power

Supply

LEDs

LED

50 MHz

FPGA

configuration via

one of six comports

6-pin JTAG

header

J1 Top Primary TIM

Connector

2x ComPorts/SDLs

Xilinx FPGA

VirtexII-Pro, FF896

XC2VP7,20,30

1.5V Core

2.5/3.3V I/O

40 I/O pins (D+@) Clock + Feedback

External 5-Volt

Power Supply

converted to

2.5 Volts by a

DC-DC converter

128 (256) Mbytes DDR RAM - MT46V16M16

J2 Bottom Secondary TIM

Connector

4x ComPorts/SDLs

Figure 1: SMT351 board block diagram

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