Sundance SMT350 User Manual

SMT350

User Manual

Version 1.9 Page 2 of 45 SMT350 User Manual

Revision History

Changes Made Issue Initials

11/10/05
18/01/06

25/01/06
31/10/06

11/12/06
25/01/2007
05/02/2007
21/02/2007

23/03/2007

18/12/2007

Original Document. 1.0 PSR
Updates on ADC inputs and DAC outputs

1.1 PSR

(impedances)
Added details on PHSTR synch. 1.2 PSR
Dac Trigger was missing. Corrected 0x0 and 0x1C

1.3 PSR

register descriptions.
LED description added as well as J1 description. 1.4 PSR
Connector list added; Control structure corrected. 1.5 PSR
Figure 6 corrected. 1.6 PSR
Scratch Test register description corrected. ADC

1.7 PSR

PLL register (0x2) corrected.
Details added to the clock circuitry. 1.8 PSR

Ordering Information added 1.9 PSR

Version 1.9 Page 3 of 45 SMT350 User Manual

Table of Contents

Physical Properties ....................................................................................................... 6

Ordering Information..................................................................................................... 6

Precautions................................................................................................................... 7

Introduction ................................................................................................................... 8

Overview ................................................................................................................... 8

Module features ........................................................................................................ 8

Possible applications ................................................................................................ 9

Related Documents .................................................................................................. 9

Functional Description ................................................................................................ 10

Block Diagram......................................................................................................... 10

Module Description ................................................................................................. 10

ADC Channels. ....................................................................................................... 12

ADC Main Characteristics. .................................................................................. 12

ADC Input Stage. ................................................................................................ 12

Dual-Channel DAC. ................................................................................................ 13

DAC Main characteristics. ................................................................................... 13

DAC output stage. ............................................................................................... 13

Clock Structure........................................................................................................ 14

Power Supply and Reset Structure......................................................................... 17

JumperJ1 ................................................................................................................ 17

Green LEDs. ........................................................................................................... 17

Mezzanine module Interface................................................................................... 17

Control Register Settings............................................................................................ 25

Control Packet Structure......................................................................................... 25

Reading and Writing Registers ............................................................................... 25

Memory Map ........................................................................................................... 26

Register Descriptions.............................................................................................. 27

Reset Register – 0x0........................................................................................... 27

Test Register – 0x1. ............................................................................................ 28

ADCA Register 0 – 0x2. ...................................................................................... 28

ADCA Register 1 – 0x3. ...................................................................................... 28

ADCA Register 2 – 0x4. ...................................................................................... 29

Version 1.9 Page 4 of 45 SMT350 User Manual

ADCB Register 0 – 0x5. ...................................................................................... 29

ADCB Register 1 – 0x6. ...................................................................................... 29

ADCB Register 2 – 0x7. ...................................................................................... 30

DAC Register 0 – 0x8.......................................................................................... 30

DAC Register 1 – 0x9.......................................................................................... 30

DAC Register 2 – 0xA. ........................................................................................ 31

DAC Register 3 – 0xB. ........................................................................................ 31

DAC Register 4 – 0xC. ........................................................................................ 31

DAC Register 5 – 0xD. ........................................................................................ 31

DAC Register 6 – 0xE. ........................................................................................ 32

DAC Register 7 – 0xF. ........................................................................................ 32

CDCM7005 Register 0 – 0x10. ........................................................................... 32

CDCM7005 Register 1 – 0x11. ........................................................................... 32

CDCM7005 Register 2 – 0x12. ........................................................................... 33

CDCM7005 Register 3 – 0x13. ........................................................................... 33

CDCM7005 Register 4 – 0x14. ........................................................................... 33

CDCM7005 Register 5 – 0x15. ........................................................................... 33

CDCM7005 Register 6 – 0x16. ........................................................................... 34

CDCM7005 Register 7 – 0x17. ........................................................................... 34

Main Module Temperature (not implemented) – 0x18........................................ 34

Main Module FPGA Temperature (not implemented) – 0x19 ............................. 34

Mezzanine Module Temperature (not implemented) – 0x1A.............................. 34

Mezzanine Module Converters Temperature (not implemented) – 0x1B ........... 35

Miscellaneous Register – 0x1C........................................................................... 35

Updates, Read-back and Firmware Version Registers – 0x1D .......................... 36

DDS Register 0 – Start Phase Increment LSB - 0x20 ........................................ 37

DDS Register 1 – Start Phase Increment MSB - 0x21 ....................................... 37

DDS Register 2 – Stop Phase Increment LSB - 0x22 ........................................ 38

DDS Register 3 – Stop Increment MSB - 0x23................................................... 38

DDS Register 0 – Step Phase Increment LSB - 0x24 ........................................ 38

DDS Register 5 – Step Increment MSB - 0x25................................................... 39

FPGA Design.............................................................................................................. 40

Serial Interfaces ...................................................................................................... 40

Version 1.9 Page 5 of 45 SMT350 User Manual

Block of registers .................................................................................................... 41

Space available in FPGA ........................................................................................ 41

PCB Layout................................................................................................................. 42

Connectors ................................................................................................................. 44

Description .............................................................................................................. 44

Location on the board ............................................................................................. 45

Table of Figures

Figure 1 – Fan across PCI. ......................................................................................................7

Figure 2 - Block Diagram........................................................................................................10

Figure 3 - Main features. ........................................................................................................12

Figure 4 - ADC Input Stage. ...................................................................................................12

Figure 5 - DAC Output Stage. ................................................................................................14

Figure 6 - Clock Structure. .....................................................................................................14

Figure 7 - External Clock........................................................................................................16

Figure 8 - Clock Architecture Main Characteristics. ...............................................................17

Figure 9 – Mezzanine module Connector Interface (SLB data and power connectors).........18

Figure 10 – Mezzanine Module Interface Power Connector and Pinout. ...............................20

Figure 11 – Daughter Module Interface: Data Signals Connector and Pinout (Bank A). ......21

Figure 12 – Daughter Module Interface: Data Signals Connector and Pinout (Bank B). .......23

Figure 13 – Daughter Module Interface: Data Signals Connector and Pinout (Bank C). .......24

Figure 14 – Setup Packet Structure. ......................................................................................25

Figure 15 – Control Register Read Sequence. ......................................................................25

Figure 16 – Register Memory Map.........................................................................................27

Figure 17 - Firmware Block Diagram......................................................................................40

Figure 18 - Space available in FPGA .....................................................................................41

Figure 19 – Main Module Component Side............................................................................42

Figure 20 - Main Module (SMT368) Solder Side....................................................................42

Figure 21 - Daughter Module Component Side......................................................................43

Figure 22 - Daughter Module Solder Side..............................................................................43

Figure 23 - Connectors Location. ...........................................................................................45

Version 1.9 Page 6 of 45 SMT350 User Manual

Physical Properties

Dimensions 63.5mm x 106.7mm x 18mm

Weight 35 grams

Supply Voltages

Supply Current +12V N/A

+5V 1.2 Amps (reset

/ converters
active)

1.4 Amps max

+3.3V 0.14 Amp (reset

/ converters
active)

0.4 Amps max

-5V N/A

-12V N/A

MTBF

Ordering Information

SMT350 (Standard Product): ADC inputs and DAC outputs are AC-coupled.

SMT350-DC: ADCs inputs are DC-coupled and DAC outputs are AC-coupled.

Version 1.9 Page 7 of 45 SMT350 User Manual

Precautions

In order to guarantee that Sundance’s boards function correctly and to protect the
module from damage, the following precautions should be taken:

- They are static sensitive products and should be handled accordingly.

Always place the modules in a static protective bag during storage and transition.

- When operated in a closed environment make sure that the heat generated
by the system is extracted e.g. a fan extracting heat or blowing cool air. Sundance
recommends and uses PAPST 12-Volt fans (Series 8300) producing an air flow of 54
cubic meters per hour (equivalent to 31.8 CFM). Fans are placed so they blow across
the PCI bus as show on the following picture:

Figure 1 – Fan across PCI.

Version 1.9 Page 8 of 45 SMT350 User Manual

Introduction

Overview

The SMT350 is a single width expansion TIM that plugs onto the SLB

SMT368

Converters (ADS5500
Converter (DAC5686
based on a CDCM7005

(Virtex-4 FPGA) and incorporates 2 Texas Instrument Analog-to-Digital

) and a Texas Instrument dual-channel Digital-to-Analog

). The SMT350 implements a comprehensive clock circuitry

chip that allows synchronisation among the converters and

base module

cascading modules for multiple receiver or transmitter systems as well as the use of
an external reference clock. It provides a complete conversion solution and stands as
a platform that can be part of a transmit/receive base station.

ADCs are 14-bit and can sample at up to 125 MHz. The DAC has a resolution of 16
bits and is able to update outputs at up to 500MHz. All converters are 3.3-Volt.

The Xilinx FPGA

(Virtex-4) on the base module is responsible for handling data

going/coming to/from one of the following destination/source: TI converters, Comport

(TIM-40 standard

), Sundance High-speed Bus (SHB). These interfaces are

compatible with a wide range of Sundance’s modules.

The memory on base module can be divided into two 16-bit wide independent blocks
for storing incoming and/or outgoing samples.

Converter configuration, sampling and transferring modes are set via internal control
registers stored inside the FPGA and accessible via Comport.

Module features

The main features of the SMT350 are listed below:

● Dual 14-bit 125MSPS ADC (ADS5500

),

● Dual channel 16-bit 500MSPS DAC (DAC5686

● On-board low-jitter clock generation (CDCM7005

● One external clocks, two external triggers and one reference clock via

MMCX

connector,

● One SLB

connector to link SMT350 and SMT368,

● Synchronisation signals,

● All Analogue inputs to be connected to 50-Ohm sources.

● All Analogue outputs to be connected to 50-Ohm loads.

● Temperature sensors.

),

),

Version 1.9 Page 9 of 45 SMT350 User Manual

Possible applications

The SMT350 can be used for the following application (this non-exhaustive list

should be taken as an example):

● High Intermediate-Frequency (IF) sampling architecture,

● Cellular base station such as CDMA and TDMA,

● Baseband I&Q systems,

● Wireless communication systems,

● Communication instrumentation,

● ...

Related Documents

ADS5500 Datasheet – Texas Instrument:

http://focus.ti.com/docs/prod/folders/print/ads5500.html

DAC5686 Datasheet – Texas Instrument:

http://focus.ti.com/docs/prod/folders/print/dac5686.html

CDCM7005 Datasheet – Texas Instrument:

http://focus.ti.com/docs/prod/folders/print/cdcm7005.html

Sundance High-speed Bus (SHB) specifications – Sundance.

ftp://ftp2.sundance.com/Pub/documentation/pdf­files/SHB_Technical_Specification.pdf

Sundance LVDS Bus (SLB) specifications – Sundance.

http://www.sundance.com/docs/SLB%20-%20Technical%20Specifications.pdf

TIM specifications.

ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf

Xilinx Virtex-4 FPGA.

http://direct.xilinx.com/bvdocs/publications/ds031.pdf

MMCX Connectors – Hubert Suhner.

MMCX Connectors

Surface Mount MMCX connector

Sundance Multiprocessor Technology Ltd.

SMT368

Version 1.9 Page 10 of 45 SMT350 User Manual

Functional Description

In this part, we will see the general block diagram and some comments on some the

SMT350 entities.

Block Diag ram

The following diagram describes the architecture of the SMT350, coupled – as an
example – with an SMT368 to show how mezzanine and base modules are

connected together:

Power
Supplies: 1.8
and 3.3 Volts

ADC Input

Ch A MMCX

50-Ohm

ADC Input

Ch B MMCX

50-Ohm

ADCs and DAC External

Clock In - MMCX

ADCs and DAC External

Clock Out - MMCX

External Reference
Clock Out - MMCX

External Reference

Clock In - MMCX

DAC Output
Ch A MMCX

50-Ohm

DAC Output
Ch B MMCX

50-Ohm

Temperature

Sensors

Channel A

Signal

Conditioning

Channel B

Signal

Conditioning

Channel A

Signal

Conditioning

Channel B

Signal

Conditioning

ADS5500

ADC ChA

14-bit 125MSPS

ADS5500

ADC ChB

14-bit 125MSPS

PECL Clock

Generation and

Distribution

based on

CDCM7005 and

SN65LVPC23

DAC5686

Dual Channel DAC

16-bit 500MSPS

Interpolation

External ADC

Trigger

ChA Data(14),
Clock and Control

ChB Data(14),
Clock and Control

ChA Data (16)
and Control

ChB Data (16)
and Control

External ADC

Trigger

DAC Clock

Daughter Card

Daughter Card

SMT350

interface

connector

SLB

Power

connector

SLB

Bank A

Bank B

Bank C

Virtex-4

XCV4SX35

FF668 Package

448 IOs

ChA&ChB Data, Clock
and Control (60)

2xComports and
Control (24)

ChA&ChB Data, Clock
and Control (60)

Power

Supplies: 1.25,

1.5, 2.5 and 3.3
Volts

SHBB

ADC Channel A and

Channel B

Spare SHB connector

(SHBA)

Top and Bottom TIM

Connectors

Spare SHB connector

(SHBC)

SHBD

DAC Channel A and

Channel B

SMT368

Figure 2 - Block Diagram.

Module Description

The module is built around two TI ADS5500
converters and one TI DAC5686

ADCs

: Analog data enters the module via two MMCX connectors, one for each

dual 16-bit digital-to-analog converter.

14-bit sampling analog-to-digital

channel. Both signals are then conditioned (AC coupling; DC optional) before being
digitized. Both ADCs gets their own sampling clock, which can be either on-board
generated or from an external reference or an external clock, common to ADCs and
DAC (MMCX connector). Digital samples travel to the FPGA on the base module via

Version 1.9 Page 11 of 45 SMT350 User Manual

the inter-module connector (SLB – Sundance LVDS Bus, used in this case as

‘single-ended’).

DAC

: Digital samples are routed from the FPGA to the DAC via the inter-module
connector. Internal interpolation scheme allows reaching 500 Mega Samples per
Second. The DAC shows other modes such as Dual DAC, Single side-band,
Quadrature or up conversion. Both outputs are AC-coupled. By default they are
single-ended but can optionally be differential. The DAC mode is selected via Jumper
J1, that enables or disables the DAC Internal PLL (see DAC5686 datasheet for more
details).

Clock generator and distribution

: All samplings clocks are generated by the same

chip. It allows having them all synchronized to a single reference clock.

Multi-module Synchronization

: There are two types of synchronization available on

the SMT350. The first one is frequency synchronization, by passing the external

reference clock to an other module. It first goes through a 0-delay buffer and is then
output. Note that the synchronization is in frequency and not in phase. The second
type is register synchronization between DACs. It is achieved by the way of an extra
link between several modules to synchronize DAC internal registers (DAC signal
PHSTR passed from one module to the other and driven by the master FPGA – it
resets the internal VCO).

Inter-module Connector

pins). It is called Sundance LVDS Bus. Please refer to the SLB specifications

: it is made of a power (33 pins) and data connectors (120

for

more details. In the case of the SMT350, the SLB is used as ‘single-ended’.

A global reset signal is mapped to the FPGA from the bottom TIM connector.

External Clock signals

, used to generate Sampling clocks. There is one external
clock, common to ADCs and DAC When used, the CDCM7005 is used as a clock
multiplexer. Also available, an external reference clock that can be passed to an
other SMT350 module with ‘0-delay’.

External Trigger

: passed directly to base module. There are two, one for the ADCs

and one for the DAC.

Temperature Sensor
provided.

: available for constant monitoring. Not part of default firmware

Version 1.9 Page 12 of 45 SMT350 User Manual

ADC Channels.

ADC Main Characteristics.

The main characteristics of the SMT350 ADCs are gathered into the following table.

Analogue Inputs

Input voltage range

Impedance

Bandwidth

Output Data Width

Data Format

SFDR

SNR

Minimum Sampling Clock

Maximum Sampling Frequency

2.4 Vp-p (11.5 dbm – 50 Ohm) Full scale ­AC coupled

ADC single-ended inputs are to be
connected to a 50Ω source. Source
impedance matching implemented between
RF transformers and ADC.

ADC bandwidth: 750 MHz.

ADCs Output

14-Bits
2’s Compliment or offset binary
(Changeable via control register)
82dBs maximum (manufacturer)
70dBs maximum (manufacturer)
10 MHz (ADC DLL off)
125 MHz (ADC DLL on)

Figure 3 - Main features.

ADC Input Stage.

Each ADC Analogue input is AC-coupled via and RF transformer. The 50-Ohm
resistor between the connector and the first RF transformer is not fitted because the
source impedance match is implemented between the second RF transformer and
the ADC by the way of two 25-Ohm resistors.

Figure 4 - ADC Input Stage.

Version 1.9 Page 13 of 45 SMT350 User Manual

Dual-Channel DAC.

DAC Main characteristics.

The main characteristics of the SMT350 DAC are gathered into the following table.

Analogue Outputs

Input voltage range

Impedance

Bandwidth

Output Data Width per channel

Data Format

SFDR

SNR

Maximum input data rate

Maximum Sampling rate

1 Vp-p – Full scale - AC coupled
DAC single-ended outputs are to be

connected to a 50Ω load, which impedance
matching implemented between DAC and
RF transformers.

TBD

DAC Input

16-Bits
2’s Compliment or offset binary
(Changeable via control register)
89dBs maximum (manufacturer)
80dBs maximum (manufacturer)
160 MSPS (Clk1 – DAC5686)
500 MSPS (Clk2 – DAC5686)

Jumper J1 disables (position 1-2; also called External Clock Mode) or enables
(position2-3; also called Internal Clock Mode) the DAC internal PLL.

DAC output stage.

The following piece of schematics shows how the DAC outputs are coupled. The
DAC5686 generates differential output signals that are fed into an RF transformer
(Ohm ratio 4), that makes both DAC channels AC coupled. 100-Ohm resistors to Vcc
on the primary stage of the transformer allow balancing the secondary stage to 50
Ohm single-ended. (Note that R153 is not mounted).

Version 1.9 Page 14 of 45 SMT350 User Manual

Figure 5 - DAC Output Stage.

Clock Structure

There is one integrated clock generator on the module (CDCM7005 – Texas
instrument). The user can either use this clock (on-board) or provide the module with
an external clock (input via MMCX connector).

Figure 6 - Clock Structure.