Sundance SMT 348 User Manual
Sundance Multiprocessor Technology Limited
User Manual
Unit / Module Description: User Manual
Unit / Module Number: SMT348
Document Issue Number:
Issue Date:
Original Author: E.P
User Manual
Form : QCF42
Date : 6 July 2006
Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,
Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied nor
communicated to a third party without prior written permission.
© Sundance Multiprocessor Technology Limited 2006
User Manual SMT348 Last Edited: 29/02/2008 17:52:00
Revision History
Issue Changes Made Date Initials
1.0.0 First release 06/11/06 E.P
1.0.1 Minor inconsistency about comports removed from
block Diagram
1.0.2 Clarification about the elements in the JTAG chain 15/11/07 E.P
1.0.3 Updated JTAG header information. Wrong marking
of position.
Added chapters about bitstream formatting, FPGA
configuration
26/02/07 E.P
29/02/08 E.P
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Table of Contents
1 Introduction ................................................................................................................ 6
2 Related Documents..................................................................................................... 7
2.1 Referenced Documents .............................................................................................7
2.2 Applicable Documents ..............................................................................................7
3 Acronyms, Abbreviations and Definitions ................................................................. 8
3.1 Acronyms and Abbreviations ...................................................................................8
3.2 Definitions .................................................................................................................8
4 Functional Description ............................................................................................... 9
4.1 Block Diagram...........................................................................................................9
4.2 Module Description.................................................................................................10
4.2.1 FPGA...................................................................................................................10
4.2.2 CPLD...................................................................................................................10
4.2.3 FLASH MEMORY..............................................................................................10
4.2.4 JTAG Header......................................................................................................10
4.2.5 FPGA Configuration schemes............................................................................11
4.2.6 FPGA Reset Scheme...........................................................................................12
4.2.7 FPGA Bitstream formatting ..............................................................................13
4.2.8 QDR2 SRAM.......................................................................................................14
4.2.9 Sundance High speed Bus .................................................................................15
4.2.10 Sundance Low voltage Bus ................................................................................15
4.2.11 TIM Connectors..................................................................................................16
4.2.12 DIP Switches ......................................................................................................16
4.2.13 Clocking scheme .................................................................................................17
4.2.14 LEDs ...................................................................................................................17
4.2.15 Performance........................................................................................................17
4.3 Interface Description ..............................................................................................17
4.3.1 Power Budget .....................................................................................................17
5 Footprint ....................................................................................................................22
5.1 Top View..................................................................................................................22
5.2 Bottom View............................................................................................................23
6 Pinout.........................................................................................................................24
6.1 FPGA Pin allocation by bank .................................................................................24
6.2 SHB..........................................................................................................................24
6.3 SLB ..........................................................................................................................24
6.4 JTAG........................................................................................................................25
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7 Qualification Requirements ......................................................................................25
7.1 Qualification Tests..................................................................................................25
7.1.1 Meet Sundance standard specifications............................................................25
7.1.2 Speed qualification tests ....................................................................................26
7.1.3 Integration qualification tests ...........................................................................26
8 Support Packages ......................................................................................................26
9 Physical Properties....................................................................................................27
10 Safety .........................................................................................................................28
11 EMC ...........................................................................................................................29
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Table of Figures
Figure 1: Block Diagram ........................................................................................................9
Figure 2: CPLD state machine.............................................................................................13
Figure 3: FPGA connections to Bank1 of QDRII.................................................................14
Figure 4: Top View................................................................................................................22
Figure 5: Bottom view ..........................................................................................................23
Figure 6: JTAG Connector, top view....................................................................................25
Table of Tables
Table 1: DIP switch SW1 position for special reset feature ...............................................16
Table 2: DIP switch SW1 position for the selection of the configuration bitstream source
.......................................................................................................................................16
Table 3: DIP switch SW1 position for the selection of the Flash erase & program
operations. .....................................................................................................................16
Table 4: Total available power. ............................................................................................18
Table 5: Power budget on 1.2v .............................................................................................18
Table 6: Power budget on 2.5v .............................................................................................18
Table 7: Power budget on 1.8v. ............................................................................................19
Table 8: Power budget on QDRII 0.9v Termination voltage. .............................................19
Table 9: Power budget on QDRII and FPGA 0.9v reference voltage. ................................20
Table 10: Power budget on 3.3v. ..........................................................................................20
Table 11: Coolrunner II resources summary.......................................................................21
Table 12:Coolrunner II pin resources. .................................................................................21
Table 13: Pin allocation by Bank .........................................................................................24
User Manual SMT348 Page 5 of 29 Last Edited: 29/02/2008 17:52:00
1 Introduction
The SMT348 is an FPGA TIM module designed to be integrated in modular
systems.
It is designed to connect to the huge range of other TIM modules and carriers
developed by Sundance.
Sundance modular solutions provide flexible and upgradeable systems.
The SMT348 is a TIM module aimed at completing the range of Sundance Virtex4
modules like SMT368, SMT362, SMT339.
It provides a communications platform between an XC4VSX55 or XC4VLX160
FPGA and
• 4 banks of QDR2 SRAM at a frequency of up to 250Mhz.
• 2 32-bit SHBs.
• TIM Global Bus.
• LVDS connections for high speed parallel connections
• LVTTL connections and connectors.
This variety of connectors and interfaces provides a wide range of development
options for designers to explore the capabilities of the comprehensive Sundance
TIM modules family.
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2 Related Documents
2.1 Referenced Documents
SUNDANCE SDB specification.
SUNDANCE SHB specification
SUNDANCE SLB specification
Samsung QDRII Datasheet
Spansion S29GLXXXN flash
2.2 Applicable Documents
TI TIM specification & user’s guide.
Samtec QSH Catalogue page
Virtex 4 Datasheet
User Manual SMT348 Last Edited: 29/02/2008 17:52:00
3 Acronyms, Abbreviations and Definitions
3.1 Acronyms and Abbreviations
TIM Texas Instruments Module
TI© DSP Texas Instrument Digital Signal Processor
Xilinx©
FPGA
QDR Quad Data Rate
CP ComPort. Communication interface
SDB Sundance Digital Bus. Communication interface
SHB Sundance High-Speed Bus. Communication interface
Xilinx© Field Programmable Gate Array.
3.2 Definitions
DSP Module
FPGA-only Module A TIM with no on-board DSP, where the FPGA provides all
Firmware A proprietary FPGA design providing some sort of functionality.
Typically a TIM module hosting a TI DSP and, a Xilinx FPGA.
functionality.
Sundance Firmware is the firmware running in an FPGA of a DSP
module.
User Manual SMT348 Last Edited: 29/02/2008 17:52:00
4 Functional Description
This module conforms to the TIM standard (Texas Instrument Module, See TI TIM
specification & user’s guide) for single width modules.
It sits on a carrier board.
The carrier board provides power (5V, 3.3V, +/-12V), ground, communication links
(Comport links) between all the modules fitted and a pathway to the host, for a non
stand-alone system.
The SMT348 requires a 3.3V power supply (as present on all Sundance TIM carrier
boards), which must be provided by the two diagonally opposite mounting holes.
4.1 Block Diagram
J1 Top Primary TIM
Connector
ComPort/SDL 0 & 3
JTAG Header
J
T
A
G
Xilinx Coolrunner II CPLD
XC2C256VQ100 on
Comport3 and
Config&control
4 banks of QDR2 SRAM
4x (2Mx18)
4 LEDs and
Figure 1: Block Diagram
Flash memory
11 I/O pins
260 I/O pins
2x ComPorts/SDL
JTAG
Virtex-4 FF1148
XC4VSX55/LX160
1.8V/2.5V/3.3V I/O
24 I/O pins
2x ComPort/SDL
J2 Bottom Secondary TIM
Connector
ComPort/SDL 1 & 4
24 I/O pins
FPGA
1.5V Core
5I/Opins
Interrupts & Reset
80 I/O pins
20 differential pa irs
40 TTL IOs
72 I/O pins
Add, Data, Control
J3 Global Bus TIM Connector
Sundance High-speed Bus
(2 Conn.)
Sundance Low-voltage Bus
(1 Conn.)
ONLY with
LX160
External clock
Local clock
User Manual SMT348 Last Edited: 29/02/2008 17:52:00
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