Sundance SMT338 User Manual

SMT338

User Manual

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Version 1.5 Page 2 of 19 SMT338 User Manual

Revision History

Date Comments Engineer Version

1 Oct

Initial Release E Puillet.

1999

2 Dec

1999

06 Jan
2000

Modification of the FSM for the FPGA
Reconfiguration

Clarification of the FSM and explanations for
the FPGA Configuration and Reconfiguration.

05.12.00 Description of the Installation and configuration
of the SMT338

20.12.00 Addition of drawing for 50-way connector
pinout and of reference for mating 50-way
SCSI connector

02.05.01 Modification of table 3 Pin out to match the
change of connector on the SMT338 (Female
to Male). Modification of explanations about
the reconfiguration in real time.

31.03.04 Modification of paraghaph 3.1 section 3.1.1
DONE is on LED 6

Version1.0

E.Puillet Version1.1

E.Puillet Version

1.2

E.Puillet Version

1.3

E.Puillet Version

1.4

E.Puillet Version

1.5

E.Puillet Version

1.6

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Version 1.5 Page 3 of 19 SMT338 User Manual

Table of Contents

Revision History.......................................................................................................... 2

Table of Contents ....................................................................................................... 3

List of Figures ............................................................................................................. 4

List of Tables .............................................................................................................. 4

Scope ......................................................................................................................... 4

1. Technical description........................................................................................... 5

1.1. Differential lines............................................................................................ 6

1.2. Sundance Digital Bus (SDB) ........................................................................ 8

1.3. SMT338-DSP Communication channels ...................................................... 8

1.4. Sundance Datapipe Link .............................................................................. 9

1.5. FPGA ......................................................................................................... 10

2. Installation ......................................................................................................... 10

3. Configuration ..................................................................................................... 11

3.1. Hardware Sequence of events ................................................................... 11

3.1.1. At power-up......................................................................................... 11

3.2. FPGA Reconfiguration ............................................................................... 13

3.2.1. Once configured.................................................................................. 13

3.3. FPGA Reconfiguration in real time............................................................. 13

3.4. Software tools ............................................................................................ 14

4. SMT338 Versions.............................................................................................. 15

5. Interface ............................................................................................................ 16

Version 1.5 Page 4 of 19 SMT338 User Manual

List of Figures

Figure 1: SMT338 Block diagram ............................................................................................. 5

Figure 2: LVD Familly sets standard ........................................................................................ 6

Figure 3: Global Clock Buffers assignments in the Virtex ........................................................ 7

Figure 4: FPGA-DSP Communication Channels ...................................................................... 9

Figure 5: Global Reset routing. Use of FPGARESET as a global reset for designs............... 12

Figure 6: FPGA reconfiguration ............................................................................................. 13

Figure 7: SMT338 Layout ........................................................................................................ 16

Figure 8: SCSI Connector Front View (Male)......................................................................... 17

List of Tables

Table 1: Virtex-Differential I/Os Combinations ......................................................................15

Table 2: SMT338 connector reference table............................................................................ 16

Table 3: Differential Signals –50 WAY High-density cable Pins............................................. 17

Table 4: 40 Way SDB Connector Pins ..................................................................................... 18

Table 5: JTAG Connector ........................................................................................................ 19

Scope

This document describes the architecture, the function, the use and the interface
considerations for the SMT338. This document is intended for both the users of the SMT338
and the designer who is interested in designing the FPGA provided on the Board.

Version 1.5 Page 5 of 19 SMT338 User Manual

1. Technical description

50 way High
Density
Diff_Con1

50 way High
Density
Diff_Con2

40 way IDC
SDB_Con1

40 way IDC
SDB_Con2

50MHz Oscillator

SDB 1

SDB 2

Differential
Line converters

DIFF1 DIFF2

FPGA

XCVxxxxBG352-4

Differential
Line converters

Comm-Port

1,4,2,5

Control

D[31:0]

A[30:0]

IIOF2

H1

Comm-Port

Bottom Primary

Connector

Global Bus

Connector

Top Primary

Connector

Config Control

Comm-Port 3 Ctrl Comm-Port 3

Configuration Logic CPLD

Figure 1: SMT338 Block diagram

Config D[7:0]

Comm-Port

Version 1.5 Page 6 of 19 SMT338 User Manual

Figure 1 shows the block diagram of the SMT338 I/O module. The following section
describes the SMT338 from a user’s point of view. Reference is made to the different blocks
of Figure 1 in the next Figures.

1.1. Differential lines

Differential signalling is the mechanism of choice when long-distance connections
from a PC to the outside world or/and high bandwidth requirements need to be
satisfied.

The SMT338 provides the user with differential pairs connected to two on-board 50­way headers on one end and to a Virtex FPGA on the other end to offer an extremely
flexible differential signalling solution.

With the ability to interface directly to RS422, RS485, Low Voltage Differential
Signalling (LVDS), and Bus LVDS (BLVDS) known as well under Multipoint LVDM
differential I/O standards, the SMT338 supports input, output and I/O signalling.

Point-to-point and multidrop transfers are achievable with up to 40 pairs for RS422,
RS485 at 32 Mbps or LVDS at 400Mbps.

Figure 2 describes the different types of transfer.

LVDM for multipoint buses.

More than one driver and one

receiver on the line

LVDS for point-to-point(1) and

multidrop(2) connections.

(1)One driver and one receiver on the
line

(2)One driver and more than one
receiver on the line.

Figure 2: LVD Familly sets standard