Sundance SMT335E User Manual
SMT335E
SMT375E
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 1.5 Page 2 of 53 SMT335E SMT375E User Manual
Revision History
Date Comments Engineer Version
04/04/01 Copy from SMT335E V1.1 J.V. 1.0
12/06/02 JTAG Header for FPGA reprogramming added
J.V. 1.1
Interrupt control register 6 address corrected
FPGA firmware version 1.1
24/06/02 SDBC and SDBD Added
Y.C 1.2
FPGA firmware version 1.2
15/07/04 Note about firmware versions added to
S.M. 1.3
clarify the difference between the 2 versions of
firmware
21/10/04 Correction in the SDB section S.M. 1.4
15/04/05 Replace the block diagram S.M. 1.5
Check your firmware revision number with the program read_version_335E.out and
ask for a more recent version if necessary.
E-mail: support@sundance.com
.
Version 1.5 Page 3 of 53 SMT335E SMT375E User Manual
Table of Contents
Revision History....................................................................................................... 2
Contacting Sundance............................................................................................... 5
Notational Conventions ........................................................................................... 6
SMT335E ................................................................................................................ 6
Register Descriptions.............................................................................................. 6
Outline Description .................................................................................................. 7
Block Diagram .......................................................................................................... 8
Architecture Description.......................................................................................... 8
TMS320C6201/6701 .................................................................................................. 9
Boot Mode............................................................................................................... 9
EMIF Control Registers.......................................................................................... 10
SBSRAM............................................................................................................... 10
SDRAM ................................................................................................................. 10
FLASH .................................................................................................................. 10
Reprogramming the firmware and boot code ...................................................... 11
Note about firmware versions ............................................................................... 11
Interrupts................................................................................................................. 12
Interrupt Control Register...................................................................................... 12
Communication ports ............................................................................................ 14
Overview ............................................................................................................... 14
Comm-ports on the SMT335E .............................................................................. 15
Comm-port Status and Control Register ............................................................... 16
Global Status Register .......................................................................................... 19
Data rates ............................................................................................................. 20
SDB.......................................................................................................................... 21
SDB Status Register ............................................................................................. 22
Output Flag Register............................................................................................. 23
Input Flag Register................................................................................................ 23
SDB update........................................................................................................... 23
SDB Interrupts ...................................................................................................... 24
DMA...................................................................................................................... 25
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SDB Initialisation................................................................................................... 26
Suspending SDB transmission.............................................................................. 26
Bus exchange ....................................................................................................... 26
SDB Clock selection ............................................................................................. 27
Data formatting ..................................................................................................... 27
Global bus............................................................................................................... 28
Writing to the Global Bus ...................................................................................... 28
Reading from the Global Bus ................................................................................ 29
Global Bus Operation Register ............................................................................. 30
Global Bus Control Register.................................................................................. 30
PCI access............................................................................................................ 31
Programmable Wait States ................................................................................... 34
Clock Speed............................................................................................................ 35
LED Setting............................................................................................................. 35
LED Register......................................................................................................... 35
CONFIG & NMI ........................................................................................................ 36
Config Register ..................................................................................................... 36
Timer........................................................................................................................ 37
Timer Control Register .......................................................................................... 37
Code Composer...................................................................................................... 38
Application Development....................................................................................... 38
Operating Conditions............................................................................................. 39
Safety.................................................................................................................... 39
EMC...................................................................................................................... 39
General Requirements.......................................................................................... 39
Power Consumption.............................................................................................. 40
Serial Ports.............................................................................................................. 41
Host Port Interface ................................................................................................. 41
Silicon Serial Number ............................................................................................ 41
C6201 Memory Map................................................................................................ 42
Flash Access........................................................................................................... 42
Virtex Memory Map................................................................................................. 43
Jumpers................................................................................................................... 45
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JP1: Clock speed select........................................................................................ 45
JP2: Serial port header ......................................................................................... 45
JP3 - Fan power connector ............................................................................... 46
JP4 - External 5V supply ................................................................................... 46
JTAG header........................................................................................................... 46
SDB Pin-Out............................................................................................................ 47
Virtex Pin-Out.......................................................................................................... 48
Bibliography............................................................................................................ 51
Index........................................................................................................................ 52
Contacting Sundance
You can contact Sundance for additional information by sending email to
support@sundance.com
Version 1.5 Page 6 of 53 SMT335E SMT375E User Manual
Notational Conventions
SMT335E
Throughout this document the term SMT335E will usually be used to refer to both the
SMT335E and the SMT375E. It should be clear from the context when a distinction is
being drawn between the two types of module.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
OFLAGLEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
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Outline Description
The SMT335E is a C6000-based size 2 TIM offering the following features:
SMT335E: TMS320C6201 processor running at 200MHz
SMT375E: TMS320C6701 processor running at 166MHz
Six 20MB/s communication ports
512KB of fast SBSRAM, 16MB of SDRAM
2MB Flash ROM for boot code and FPGA programming
Global expansion connector
High bandwidth data I/O via 4 Sundance Digital Buses (SDB).
Version 1.5 Page 8 of 53 SMT335E SMT375E User Manual
Block Diagram
Architecture Description
The SMT335E TIM consists of a Texas Instruments TMS320C6201 running at
200MHz while the SMT375E has a TMS320C6701 running at 166MHz. Modules are
populated with 512KB of synchronous burst SRAM (SBSRAM) and 16MB of
synchronous DRAM (SDRAM), giving a total memory capacity of 16.5MB.
A Field Programmable Gate Array (FPGA) is used to manage global bus accesses
and implement six communication ports and four Sundance Digital Buses.
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TMS320C6201/6701
Bother processors will run with zero wait states from internal SRAM, the
TMS320C6201 at 200MHz and the TMS320C6701 at 166MHz.
An on-board synthesiser from MicroClock provides the clock used for the C6000;
jumpers on the TIM allow you to select clock speeds from 118MHz to 200MHz.
Unlike similar TIMs based on the TMS320C4x, there is no option to provide an
external clock source.
The TIM configuration feature is fully implemented. This provides a single opencollector line that can be held low until software configuration has been completed.
Boot Mode
The SMT335E is configured to use the following boot sequence each time it is taken
out of reset:
1. The processor copies a bootstrap program from the first 32KB of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT335E then performs the following
operations:
1. All relevant C6000 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance Digital Buses. This
step must have been completed before data can be sent to the comm-ports
from external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the six
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” on page 38 for details
of the boot loader format;
4. Finally, control is passed to the loaded program.
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EMIF Control Registers
The C6000 contains several registers that control the external memory interface
(EMIF). There is one global control register and a separate register for each of the
memory spaces CE0 to CE3. A full description of these registers can be found in the
C600001 Peripherals Reference Guide[1].
The standard bootstrap will initialise these registers to the following values:
GC (global control)
0x00003779
0x0000377D
For half speed SBSRAM
For full speed SBSRAM (default)
CE0 0x00000040 Indicates SBSRAM
CE1 0x30FF3F23 Defines asynchronous memory timings
CE2 0x00000030 Indicates SDRAM
CE3 0x00000030 VIRTEX FPGA
SBSRAM
Memory space CE0 is used to access 512KB of zero wait-state SBSRAM over the
C6000 external memory interface (EMI).
SBSRAM is normally set to run at the speed of the C6000 core clock, but the GC
register can be used to reduce this to one half of the core clock speed. The
appropriate setting has to be determined in conjunction with the C6000 core speed
and the external memory speed; refer to Clock Speed on page 35 for further details.
SDRAM
Memory space CE2 is used to access 16MB of SDRAM over the EMI. The SDRAM
operates at one half of the core clock speed.
FLASH
A 2MB Flash ROM device is connected to the C6000 EMI. This device is accessed,
16-bit word at a time, with word addresses from 0x0140 0000 to 0x015F FFFF using
strobe CE1 in 32-bit asynchronous mode. Each 32-bit load will give 16 bits of data in
bits 15–0 of the result; the state of bits 31–16 is undefined.
The ROM holds boot code for the C6000, configuration data for the FPGA, and
optional user-defined code.
A software protection algorithm is in place to prevent programs accidentally altering
the ROM’s contents. Please contact Sundance for further information about reprogramming this device [6].
Version 1.5 Page 11 of 53 SMT335E SMT375E User Manual
Reprogramming the firmware and boot code
The Reprogramming\flash directory of the distribution disk contains a utility that
will run under code composer and program the flash ROM. The utility is called
pflashx_y_z.out, where x_y_z is the FPGA version number.
You load the utility with the code composer “Load Program” option from the “File”
menu. Once the program has loaded, you should select “Run” from the “Debug”
menu. The reprogramming process takes a minute or so and should display “Flash
programming complete” when it has finished. After the program has run you should
“Halt” the processor from the “Debug” menu and select “Run Free”. To confirm that
the programming has been successful you should use the Sundance Server to reset
the board and execute one of the supplied test programs.
A detailed description of the reprogramming process is available as an Application
Note [2], which will also help you to develop your own core in the FPGA.
Note about firmware versions
There are two versions of Sundance firmware for SMT335E.
One version is for the FPGA Virtex-2000. This firmware implements only 2 SDBs,
and it is named: top335ev2000_v1_1.dat
The other version is for the FPGA Virtex-1000. This firmware implements 4 SDBs,
and it is named: top335ev1000_v1_2.dat
Version 1.5 Page 12 of 53 SMT335E SMT375E User Manual
p
Interrupts
The generation of a CPU interrupt by a comm-port, an SDB, or the Global Bus starts
when the FPGA asserts an interrupt condition. For example, this may be the result of
an input FIFO becoming not empty or an output FIFO not full.
The interrupt condition is then further controlled by interrupt condition enables in the
FPGA. If enabled, an asserted interrupt condition will cause one of the CPU’s
external interrupt lines to be asserted and an interrupt event to be latched in the
processor’s Interrupt Flag Register (IFR).
Finally, the processor will be interrupted, providing the interrupt event is enabled in
the processor’s Interrupt Enable Register (IER) and the Global Interrupt Enable (GIE)
is set in the processor’s Control and Status Register (CSR).
The C6000 provides four external interrupt input lines, EXT_INT4, EXT_INT5,
EXT_INT6, and EXT_INT7, which can be driven by a variety of interrupt conditions.
Each external interrupt has a separate interrupt control register (INTCTRLn) where
you set bits to enable the interrupt condition.
Interru
t Control Register
INTCTRL4 0x03E00000
INTCTRL5 0x03E80000
INTCTRL6 0x03F00000
INTCTRL7 0x03F80000
31–30 29–28 27–26 25–24 23–22 21–20 19–18 17–16
CP0 IE CP1 IE CP2 IE CP3 IE CP4 IE CP5 IE SDBA IE SDBB IE
RW,00 RW,00 RW,00 RW,00 RW,00 RW,00 RW,00 RW,00
15 14 13 12 11 10
GB IE TCLK1 IE TCLK0 IE IIOF2 IE IIOF1 IE IIOF0 IE
RW,0 RW,0 RW,0 RW,0 RW,0 RW,0
9–0
RW,0000000000
Field Description Interrupt condition selected
Version 1.5 Page 13 of 53 SMT335E SMT375E User Manual
CPx IE(bit 0)
CPx IE (bit 1)
Comm-port Input FIFO
Interrupt Enable
Comm-port Output FIFO
Interrupt Enable
IFBM=0
IFBM=1 8 words available
OFBM=0 not full
OFBM=1 8 spaces available
not empty
SDBx IE (bit 0) SDB IFLAG Interrupt Enable ≥ IFLAGLEVEL words available
SDBx IE (bit 1) SDB OFLAG Interrupt Enable ≥ OFLAGLEVEL spaces available
GB IE Global Bus Interrupt Enable STAT = 1
TCLKn IE TIM clock interrupt enable See TIM specification [3]
IIOFn IE External line interrupt enable See TIM specification [3]
It is possible to map more than one condition to an interrupt line. For example, you
might map all of the comm-port conditions to a single interrupt line and then use the
Global Status Register to find which condition or conditions had caused the interrupt.
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Communication ports
Overview
The SMT335E provides six 8-bit, data-parallel, inter-processor links that follow Texas
Instruments’ TMS320C4x Communication Port standard. Additional information on
the standard is available in the TMS320C4x User’s Guide chapter 12:
Communication ports and the Texas Instrument Module Specification.
The standard gives a TIM six links numbered from 0 to 5. Each link can be a
transmitter or a receiver, and will switch automatically between these states
depending on the way you use it. Writing to a receiver or reading from a transmitter
will cause a hardware negotiation (token exchange) that will reverse the state of both
ends of the link.
Following a processor reset, the first three links (0, 1, and 2) initialise as transmitters
and the remainder (3, 4, and 5) initialise as receivers. When you wire TIMs together
you must make sure that you only ever connect links initialising as transmitters to
links initialising as receivers; never connect two transmitters or two receivers. For
example, connecting link 0 of one TIM to link 4 of another is safe; connecting link 0 of
one TIM to link 2 of another could damage the hardware.
Always connect comm-ports 0, 1, or 2 to comm-ports 3, 4, or 5.
On the SMT320 carrier board the physical connection between comm-ports is made
with FMS cables (Ref. SMT3xx-FMS). You must be careful when connecting the
cables the make sure that one end is inserted in the opposite sense to the other. One
end must have the blue backing facing out and the other must have the silver
backing facing out.
The SMT320 motherboard communicates with the host PC using comm-port 3 of the
site 1 TIM. You should not make any other connections to this comm-port.
Version 1.5 Page 15 of 53 SMT335E SMT375E User Manual
1
5
Comm-ports on the SMT335E
An SMT335E TIM has access to six FIFO-buffered comm-ports, fully compliant with
the Texas Instruments’ standard [3].
Each comm-port is associated with two 15x32-bit unidirectional FIFOs; one for input
and one for output. An additional one-word buffer makes them appear as 16x32-bit
FIFOs. These allow the guaranteed maximum transfer rate of 20MB/s to be achieved.
FIFO
FIFO
15x32x2
15x32x2
D[0..7]
STRB
RD Y
REQ
ACK
PO RT 0PO RT
Da ta
FIFO
15x32x2
Ad d ress
Ad d ress
decode
… …
D[0..7]
STRB
RD Y
REQ
ACK
Control
FIFO
15x32x2
D[0..7]
STRB
RD Y
REQ
ACK
PO RT
Version 1.5 Page 16 of 53 SMT335E SMT375E User Manual
Comm-port Status and Control Register
CP0_STAT 0x03040000 CP3_STAT 0x031C0000
CP1_STAT 0x030C0000 CP4_STAT 0x03240000
CP2_STAT 0x03140000 CP5_STAT 0x032C0000
31–28 27 26 25 24 23–20 19–16 15–12 11-8
IFF IFE OFF OFE IFL OFL
R,0 R,1 R,0 R,1 R,0000 R,1111
7 6 5 4 3 2 1 0
ICPRDY OCPRDY CLRCP IFBM OFBM CLRIF CLROF DIR
R,0 R,1 W,0 RW,0 RW,0 W,0 W,0 R,0
Field Description (flags are active when 1)
0 Reading
DIR
1 Writing
CLROF Write 1 to clear outgoing FIFO
CLRIF Write 1 to clear incoming FIFO
0 Single-word operation
OFBM Output FIFO Burst Mode
1 8-word burst mode operation
0 Single-word operation
IFBM Input FIFO Burst Mode
1 8-word burst mode operation
CLRCP
Reset comm-port: Both FIFOs are cleared and the comm-port interface
is set back to its default direction. Use with caution (see below).
OFL Output FIFO Level: Number of words (0–15) which can be written
OCPRDY Comm-port interface buffer OCPRDY=’1’ if empty
IFL Incoming FIFO level: Number of words (0–15) available to be read
ICPRDY Comm-port interface buffer; ICPRDY=’0’ if empty
OFE Outgoing FIFO Empty Flag (space is available for writing 16 words)
OFF Outgoing FIFO Full Flag
IFE Incoming FIFO Empty Flag
IFF Incoming FIFO Full Flag (16 words are available to be read)
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