Sundance SMT329 User Manual

Sundance Multiprocessor Technology Limited

User Manual

Unit / Module Description: VME64 carrier with 4 TIM sites
Unit / Module Number: SMT329
Document Issue Number:
Issue Date:
Original Author: S. E. Carpenter

User Manual

for

Form : QCF42
Date : 6 July 2006

SMT329

Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside,

Chesham, Bucks. HP5 1PS.

This document is the property of Sundance and may not be copied nor

communicated to a third party without prior written permission.

© Sundance Multiprocessor Technology Limited 2006

User Manual SMT329 Last Edited: 09/02/2007 10:58:00

Revision History

Issue Changes Made Date Initial

1.0 First draft 24th Jan 07 SEC

s

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Table of Contents

1 Introduction............................................................................................... 6

2 Related Documents .................................................................................... 7

2.1 Referenced Documents ..................................................................................................7

2.2 Applicable Documents....................................................................................................7

3 Acronyms, Abbreviations and Definitions..................................................8

3.1 Acronyms and Abbreviations.........................................................................................8

3.2 Definitions ......................................................................................................................8

4 Functional Description............................................................................. 10

4.1 Block Diagram ..............................................................................................................10

4.2 Module Description......................................................................................................10

4.2.1 Virtex 4......................................................................................................................11

4.2.2 Spartan 3..................................................................................................................13

4.2.3 CPLD .......................................................................................................................20

4.3 TIM Global Bus Resources...........................................................................................21

4.4 VME Interface...............................................................................................................22

4.4.1 VME slave interface to VME config and reset registers .........................................22

4.4.2 VME slave interface to the I/O registers.................................................................26

4.4.3 VME slave interface to the SRAM ...........................................................................27

4.4.4 TIM Global bus interface to the I/O registers ........................................................29

4.4.5 TIM Global bus interface to the VME bus master..................................................29

4.4.6 TIM Global bus interface to the SRAM.................................................................. 30

4.5 I/O Registers.................................................................................................................31

4.5.1 Comm Port Interface ...............................................................................................31

4.5.2 Reset (RST) register.................................................................................................34

4.5.3 Flash control interface.............................................................................................34

4.5.4 IO Control and Status registers...............................................................................36

4.6 Static RAM (sram).......................................................................................................40

4.7 JTAG Debugging Logic................................................................................................40

4.8 TIM Sites.......................................................................................................................41

4.8.1 TIM Connectors.......................................................................................................42

4.9 ROCKETIO....................................................................................................................42

4.10 Gigabit Ethernet ...........................................................................................................42

4.11 DMA controllers ...........................................................................................................43

4.12 Power Supplies .............................................................................................................43

4.13 Interface Description....................................................................................................44

4.13.1 Mechanical Interfac e ...............................................................................................44

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4.13.2 Electrical Interface...................................................................................................44

5 Footprint.................................................................................................. 45

5.1 Top View .......................................................................................................................45

5.2 Bottom View..................................................................................................................46

6 Pinout ...................................................................................................... 47

7 Support Packages..................................................................................... 52

8 Physical Properties .................................................................................. 52

9 Safety ....................................................................................................... 52

10 EMC ......................................................................................................... 52

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Table of Figures

Figure 1: SMT329 Architecture ..................................................................................................10

Figure 2: SMT329 Virtex4 internal bus architecture..................................................................11

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1 Introduction

The Smt329 is a VME four-site module carrier developed to provide ac cess to TIM Modules
over the VME64 (parallel) and VXS (serial) busses. It is backward compatible with the
SMT328, and can replace the SMT328 with no software mo difications. By implementing the
VME64 2eSST standard it offers up to 320M bytes/sec (2.56G bits/sec) across the VME bus,
while 8 VXS ports offer up to 2.5G bits/sec each, making a VXS total of up to 20G bits/sec.

The SMT329 has 8M bytes of high sp eed static ra m arranged as 1M by 64 bits, with a read or
write speed of at least 1G bytes/sec throughput for 64 bit transfers.

Buffered front panel JTAG ports allow control and debug of all 4 TIM modules
simultaneously, and multiple SMT329s.

All communications apart from JTAG and comms ports are controlled by a single Virtex 4
FPGA.

The 6 comms ports on each TIM (3 reset to out and 3 reset to in), and 2 comms ports on the
Virtex 4 (2 reset to out), are connected to a crossbar switch which allows a static
configuration to specify which of the 14 reset to out ports is connected to each of the 12 reset
to in ports. The switch is implemented in a Xilinx Spartan 3 FPGA. The switch topology is
stored in NVRAM and copied to the switch at board reset by the Virtex4.

The 2 RSL ports on each TIM are connected to Virtex4 Rocketio ports.

Four 1 Gigabit Ethernet ports are available on the VME P2 connector.

Two TIM sites have global bus interfaces to the Virtex4 for access to the static ram and VME
bus.

For use in legacy VME racks, SMT329 can be assembled with no P0 connector, and an on
board 3.3V PSU. It does not guarantee to support 2eVME or 2eSST and does not support
VXS, but it does retain the four Gigabit Ethernet ports on the P2 connector.

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2 Related Documents

2.1 Referenced Documents

SMT 328 User Guide 7p1
SMT329 Product Specification 20Dec05

2.2 Applicable Documents

TIM-40 Module Specification (1993)

ANSI/VITA 1.1-1997 American National Standard for VME64 Extensions
ANSI/VITA 1-1994 (R2002) American National Standard for VME64

2eSST ANSI/VITA 1.5-2003
VITA 41.0-200x VXS standard
SN74VMEH22501A data sheet Texas Instruments SCES620 – DECEMBER 2004

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3 Acronyms, Abbreviations and Definitions

3.1 Acronyms and Abbreviations

C60

The terms C60, C64xx and TMS320C64xx are used interchangeably throughout this
document.

3.2 Definitions

Register Descriptions
The format of registers is described using diagrams of the following form:

31–24 23–16 15–8 7–0

LEVEL

R,00000000 RW,10000000 R,00000000 R,10000000

The digits at the top of the diagram indicate bit positions within the register and the central
section names bits or bit fields. The bottom row describes what may be done to the field and
its value after reset. Shaded fields are reserved and should only ever be written with zeroes.

R = Readable by the CPU
W = Writeable by the CPU
RW = Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.

Byte Addressing

All byte addresses are “Big Endian”. This is defined as follows:
Decreasing numeric significance with increasing memory addresses.
So for the register definition shown above:
Bits 31-24 = Byte Address 0
Bits 23-16 = Byte Address 1
Bits 15-8 = Byte Address 2
Bits 7-0 = Byte Address 3

Care must be taken when using an Intel (PC) little endian based VME host controller, to
ensure the use of either hardware or software byte swapping when accessing the SMT329
over the VME bus.

VME64 and legacy VME systems

A VME64 system meets the ANSI/VITA specification for VME64, with 160 pin backplane
connectors and a 3.3 Volt backplane supply.

User Manual SMT329 Last Edited: 09/02/2007 10:58:00

A “legacy” VME system meets the ANSI/VITA specification for VME, with 96 pin
backplane connectors and NO 3.3 Volt backplane supply.

The SMT329 is always fitted with 160 pin connectors, which are designed to successfully
mate with either a VME64 system or a legacy VME system.

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4 Functional Description

4.1 Block Diagram

Figure 1: SMT329 Architecture

4.2 Module Description

Figure 1 shows the SMT329 block diagram. There are 4 single width or 2 double width TIM
sites. All communications apart from the comms port switching are routed through the Xilinx
Virtex4 fpga, including all VME and SRAM i/o. Comms port cross bar switching is
performed by a Xilinx Spartan3. Loading the configuration data into the 2 fpgas and
managing the JTAG interface are performed by a Xilinx CPLD.

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4.2.1 Virtex 4

Figure 2: SMT329 Virtex4 internal bus architecture

Figure 2 shows the SMT329 bus architecture within the Virtex4. This is backwards
compatible with SMT328, with the addition of a 4 channel Ethernet DMA engine, a 4 channel
Rocketio DMA engine, and a Rocketio cross bar switch matrix.

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Table 1 below shows the actual implementation of the parall el bus connectivity for the VME
slave, TIM global 1, TIM global 2, DMAA, DMAB. These 5 separate bus masters each have
fully dedicated connections to an arbitrating bus switch, which can con nect all 5 masters to
any 5 slaves out of the 8 available, AT THE SAME TIME. This architecture avoids the
traditional bottle neck problems associated with a single bus, which is used by on e master at
a time.

Slave S1 S2 S3 S4 S5 S6 S7 S8
Master VME&

Reset

Control
& DMA

Flash Sram VME

Master

Comms RSLA RSLB

M1 VME

Y Y Y Y N Y Y Y

Slave

M2 TIM

N Y Y Y Y N Y Y

Global1

M3 TIM

N Y Y Y Y N Y Y

Global2

M4 DMAA

N N N Y Y N Y Y

M5 DMAB

N N N Y Y N Y Y

Table 1: SMT329 Virtex4 internal bus architecture

There are exceptions to the permitted connectivity indic ated by “Y” for connection p ermitted
and “N” for no connection.

Revision 1 of the Virtex 4 configuration, provides functional equivalence with the SMT328,
which it replaces. Subsequent releases of the Virtex 4 configuration will provide support for
the following additional functions:

VME64 burst transfer modes.
VME 2eSST transfer modes.
RSL TIM interfaces.
1G bit Ethernet connectivity.
DMA to and from the SRAM.
VXS connectivity.
Subsequent revisions of the Virtex 4 configuration will be mad e available on the Sundance

WEB site along with a utility for updating their flash images on the SMT329. Updates to this
manual will accompany new firmware releases.

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4.2.2 Spartan 3

The SMT329 comms port mapping is performed by a cross bar switch implemented in a
Xilinx Spartan3 fpga. The cross bar switch has 12 Reset To In (RTI) ports and 14 Reset To
Out (RTO) ports.

Table 2 below illustrates the architecture:

RTI 0 1 2 3 4 5 6 7 8 9 10 11
RTO T1C3 T1C4 T1C5 T2C3 T2C4 T2C5 T3C3 T3C4 T3C5 T4C3 T4C4 T4C5
0 T1C0 Y Y Y Y Y Y Y Y Y Y Y Y
1 T1C1 Y Y Y Y Y Y Y Y Y Y Y Y
2 T1C2 Y Y Y Y Y Y Y Y Y Y Y Y
3 T2C0 Y Y Y Y Y Y Y Y Y Y Y Y
4 T2C1 Y Y Y Y Y Y Y Y Y Y Y Y
5 T2C2 Y Y Y Y Y Y Y Y Y Y Y Y
6 T3C0 Y Y Y Y Y Y Y Y Y Y Y Y
7 T3C1 Y Y Y Y Y Y Y Y Y Y Y Y
8 T3C2 Y Y Y Y Y Y Y Y Y Y Y Y
9 T4C0 Y Y Y Y Y Y Y Y Y Y Y Y
10 T4C1 Y Y Y Y Y Y Y Y Y Y Y Y
11 T4C2 Y Y Y Y Y Y Y Y Y Y Y Y
12 VXC1 Y Y Y Y Y Y Y Y Y Y Y Y
13 VXC2 Y Y Y Y Y Y Y Y Y Y Y Y

Table 2: SMT329 Spartan 3 comms port switch internal architecture

This switch has no connectivity restrictions.

The connectivity map is loaded by the CPLD directly from flash memory following power on,
after the Spartan 3 configuration is loaded, but before the Virtex 4 configuration is loaded.
This connectivity map can be changed by the user, who uses a flash program ming utility to
write a new map into the flash. This map is then loaded into the Spartan 3 the next time the
SMT329 is powered on.

4.2.2.1 Comms Switch Map

The map has 12 entries, each of which defines which RTI is connected to which RTO. So entry
1 defines which RTO is connected to RTI 1, and entry 12 defines which RTO is connected to
RTI 12. Each entry has a value in the range 0 to 13 as there are 14 RTO ports. Each entry must
be different.

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The map itself is embedded in a normal text file, and the whole text file is stored in the flash,
so that the map can be accompanied by any descriptive text, up to a maximum file size of 64K
bytes. The map is identified in the text by the keyword “SMT329MAP

The SMT329 flash can be programmed from ei ther the VME bus or by a TIM in either slot 1
or 4. The map is loaded from the flash into th e Sp artan3 fpga by the CPLD, immediately after
the SMT329 power is stable following switch on. The map can not be loaded at any other
time. The map must load without error for the cross bar switch to work correctly. The
Spartan3 performs the following data validation checks before enabling the switch:

1. All entries are in the range 0 to 13.

2. No entry is the same.
If either of these criteria are not met, the switch will not be enabled.

”.

4.2.2.2 Comms Switch Map port connectivity

The 12 RTI ports and 14 RTO ports are connected as follows:

Switch port RTI port RTO port

0 T1C3 T1C0
1 T1C4 T1C1
2 T1C5 T1C2
3 T2C3 T2C0
4 T2C4 T2C1
5 T2C5 T2C2
6 T3C3 T3C0
7 T3C4 T3C1
8 T3C5 T3C2
9 T4C3 T4C0
10 (0xA) T4C4 T4C1
11 (0xB) T4C5 T4C2
12 (0xC) not connected VXC1 (VME port 1)
13 (0xD) not connected VXC2 (VME port 2)

4.2.2.3 Comms Switch Map Example 1

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This example duplicates the default connectivity of th e SMT328, and is loaded in the flash
during SMT329 production, filename “s329map.txt” :

SMT329MAPCAB012345D78
SUNDANCE SMT329 STANDARD COMMS PORT MAP MIMICS SMT328
DATE: 17-DEC-06
COMPANY: SUNDANCE
AUTHOR: SEC
Connect SMT329 to mimic a standard SMT328
Entry Value Description
1 12 = 0xC T1C3 (RTI) to VXC1 (RTO)
2 10 = 0xA T1C4 (RTI) to T4C1 (RTO)
3 11 = 0xB T1C5 (RTI) to T4C2 (RTO)
4 0 = 0x0 T2C3 (RTI) to T1C0 (RTO)
5 1 = 0x1 T2C4 (RTI) to T1C1 (RTO)
6 2 = 0x2 T2C5 (RTI) to T1C2 (RTO)
7 3 = 0x3 T3C3 (RTI) to T2C0 (RTO)
8 4 = 0x4 T3C4 (RTI) to T2C1 (RTO)
9 5 = 0x5 T3C5 (RTI) to T2C2 (RTO)
10 13 = 0xD T4C3 (RTI) to VXC2 (RTO)
11 7 = 0x7 T4C4 (RTI) to T3C1 (RTO)
12 8 = 0x8 T4C5 (RTI) to T3C2 (RTO)
The map file is stored in the flash in ascii
and has a keyword identifier immediately before the map data of

"SMT329MAP"
This is the map which is duplicated at the top of the file:
SMT329MAPCAB012345D78

-END-

The very first line begins with the map keyword “SMT329MAP“, although it can appear
anywhere in the text. This is immediately followed by “CAB012345D78” which is the actual
map. The descriptive text which follows explains each map entry.

4.2.2.4 Comms Switch Map Example 2

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This example is used for testing, and with the correct TIM software implements a spiral
which allows loop back testing of all ports on all tims at once. Filename
“S329MAPSPIRAL1.txt” :

SMT329MAPCAB012345678
SUNDANCE SMT329 SPIRAL1 TEST COMMS PORT MAP
This map implements a spiral connection of comms ports to
allow testing all comms ports from VME port 1.
It can not test VME port 2.
DATE: 17-DEC-06
COMPANY: SUNDANCE
AUTHOR: SEC
This is the 328 equivalent map:
Entry Value Description
1 12 = 0xC T1C3 (RTI) to VXC1 (RTO)
2 10 = 0xA T1C4 (RTI) to T4C1 (RTO)
3 11 = 0xB T1C5 (RTI) to T4C2 (RTO)
4 0 = 0x0 T2C3 (RTI) to T1C0 (RTO)
5 1 = 0x1 T2C4 (RTI) to T1C1 (RTO)
6 2 = 0x2 T2C5 (RTI) to T1C2 (RTO)
7 3 = 0x3 T3C3 (RTI) to T2C0 (RTO)
8 4 = 0x4 T3C4 (RTI) to T2C1 (RTO)
9 5 = 0x5 T3C5 (RTI) to T2C2 (RTO)
10 13 = 0xD T4C3 (RTI) to VXC2 (RTO)
11 7 = 0x7 T4C4 (RTI) to T3C1 (RTO)
12 8 = 0x8 T4C5 (RTI) to T3C2 (RTO)
This is the sprial test map:
Entry Value Description
1 12 = 0xC T1C3 (RTI) to VXC1 (RTO)
2 10 = 0xA T1C4 (RTI) to T4C1 (RTO)
3 11 = 0xB T1C5 (RTI) to T4C2 (RTO)
4 0 = 0x0 T2C3 (RTI) to T1C0 (RTO)
5 1 = 0x1 T2C4 (RTI) to T1C1 (RTO)
6 2 = 0x2 T2C5 (RTI) to T1C2 (RTO)
7 3 = 0x3 T3C3 (RTI) to T2C0 (RTO)
8 4 = 0x4 T3C4 (RTI) to T2C1 (RTO)
9 5 = 0x5 T3C5 (RTI) to T2C2 (RTO)
10 6 = 0x6 T4C3 (RTI) to T3C0 (RTO)
11 7 = 0x7 T4C4 (RTI) to T3C1 (RTO)
12 8 = 0x8 T4C5 (RTI) to T3C2 (RTO)
It assumes the following software routing in the TIMs:

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