Sundance SMT326 User Manual
Release Page 1 of 24 SMT326 DSP PC/ISA System User Guide
SMT326v2
Sundance SMT326V2
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 2 of 24 SMT326 DSP PC/ISA System User Guide
Contents
Description ................................................................................................................................... 3
Architecture.................................................................................................................................. 3
Processor ..................................................................................................................................... 3
Interrupts.......................................................................................................................... 4
Reset ............................................................................................................................... 4
Communications Ports ..................................................................................................... 4
Local Bus Resource ...................................................................................................................... 5
Local SRAM..................................................................................................................... 5
ID ROM ............................................................................................................................ 5
Local Memory Interface Control Register (LMICR) ........................................................... 5
Global Bus Resource.................................................................................................................... 6
Global SRAM................................................................................................................... 6
CODEC............................................................................................................................ 6
DAC..................................................................................................................... 6
ADC..................................................................................................................... 6
CODEC Clocking................................................................................................. 7
CODEC Control ................................................................................................... 7
CODEC Start....................................................................................................... 7
CODEC Stop ....................................................................................................... 7
CODEC Interrupt & Status ................................................................................... 7
LED Control ..................................................................................................................... 8
Global Memory Interface Control Register (GMICR) ......................................................... 8
Codec Interface FPGA..................................................................................................... 8
C44 Memory Map Summary......................................................................................................... 8
Interface Logic .............................................................................................................................. 9
Communication Port Interface.......................................................................................... 9
Link Reset / NMI .................................................................................................. 9
Link Status........................................................................................................... 9
Link Data ............................................................................................................. 9
PC I/O Map Summary .................................................................................................................. 10
Jumpers ....................................................................................................................................... 10
CV10 series Micro-miniature Coaxial Connector........................................................................... 10
Connector Numbering................................................................................................................... 12
Example Code .............................................................................................................................. 13
Test Code ..................................................................................................................................... 14
Test both a ADC channel and a DAC channel .................................................................. 14
Functions 17
Test a DAC channel ......................................................................................................... 19
How To DMA................................................................................................................................ 24
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 3 of 24 SMT326 DSP PC/ISA System User Guide
LED
LED
CP1
Description
The SMT326 is a PC-ISA full-length card supporting a TMS320C44 ('C44) DSP together with
multiple A/D and D/A channels.
Incorporated on the card is an interface between the PC and a 'C44 communications port.
For increased processing performance, another 'C44 (or 'C40) can be added as a TIM.
Architecture
CP2 CP3
FMS 0
FMS 1
5
2
1
'C44
local global
FMS 2
SRAMSRAM
ID ROM FLASH
4
ADC
I2C
Interface
DAC
Logic
TTL I/O
CTRL
PC-ISA Bus
Processor
The SMT326 includes a 50MHz TMS320C44 DSP. This device is connected to a TIM (Texas
Instruments Module) site via 3 communication ports (4 ports are available with a 'C44). These three
ports are also brought out to individual connectors for connection to a larger processing system. The
connectors used are compatible with a range of Sundance 'C4x products including a 4 slot PC-ISA
TIM carrier card, frame grabbers, VXI carrier card and a 'C40 TRAM.
Debugging of application software may be carried out by the connection of an XDS-510 (or
compatible) JTAG debugger. A standard JTAG header (compliant with the requirements in the 'C4x
User's Guide) is provided on the rear edge of the board.
The 'C44 processor has two separate memory busses. They are named local and global, and the
resources on the SMT326 are shared between these busses.
An upgrade to a 60MHz 'C44 is possible
This 'C44 implementation is capable of being booted from a communication port or from on board
ROM.
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 4 of 24 SMT326 DSP PC/ISA System User Guide
Interrupts
The processor may be interrupted from the ADCs on IIOF0. The ‘C44 should be set up as
edge triggered, as this signal lasts only 4 CODEC master clocks (80ns).
'C44 interrupt IIOF1 is routed to the PC Interface Logic but is currently uncommitted.
Reset
Reset to the board is performed by the PC-ISA signal RSTDRV.
A software reset to the 'C44 and communications port interface can be performed by the PC
writing a '1' to bit 0 of the link reset register (PC I/O address 0x30C).
Communications Ports
The 'C44 has four bi-directional communications ports (CPn - where n is 1,2,4 or 5) able to
sustain data rates of up to 20Mbytes/s.
On this board, one of the ports, P4, is connected to the PC-ISA communications port
interface. The other three are taken to ribbon cable connectors on the reverse of the board.
They are labelled CP1, CP2 and CP3. CP1 is connected to P1, CP2 to P2 and CP3 to P5.
(CP1=P1=FMS0; CP2=P2=FMS1 and CP3=P5=FMS2).
Additionally, ports P1, P2 and P5 are routed to the TIM site provided for expansion. P1 is
connected to TIM port 4, P2 to TIM port 5 and P5 to TIM port 1.
It must be noted that if a TIM is mounted in the TIM site then care must be taken to
ensure that only one device is driving the communications ports.
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 5 of 24 SMT326 DSP PC/ISA System User Guide
Local Bus Resource
The local bus has access to a bank of SRAM and the ID ROM.
Local SRAM
The SRAM is composed using a 72 pin ZIP SRAM module. Up to 4Mbytes are available with
the largest module. Faster SRAM (15ns) would be needed for 60MHz operation.
The local SRAM is accessed at address 0x00300000 on processor strobe LSTRB0.
ID ROM
On the local bus of the 'C44 is an ID ROM which contains module specific data to enable
operating systems such as 3L to determine the processor network architecture.
This device is a 32k byte erasable ROM, and can be re-written by the 'C44. It must be
accessed with 7 wait states at address 0x70000000 on processor strobe LSTRB0.
For write protection purposes, in addition to a software mechanism, a jumper, JP4, must be
inserted to enable writes to the ID ROM.
For storage of TIM compliant ID information, this ROM appears as a 4 bit ID ROM.
This device also contains the configuration code for the Xilinx Codec Interface.
Local Memory Interface Control Register (LMICR)
Within the 'C44 is a register which determines how the bus is partitioned and how many wait
states to use for accesses. There are two values which must be programmed here. One is for
ID ROM access, and the other for SRAM access.
For ID ROM access the value 0x3E39FF50 must be programmed into the LMICR.
For SRAM access (normal operation) the value 0x3EF78050 must be programmed into the
LMICR. When using an operating system like 3L, the loading of this register is performed
using the value within the ID ROM.
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 6 of 24 SMT326 DSP PC/ISA System User Guide
Global Bus Resource
The global bus has access to SRAM, DACs, ADCs, LED control register and ADC control registers.
Global SRAM
The SRAM is composed using a 72 pin ZIP SRAM module. Up to 4Mbytes are available with
the largest module. Faster SRAM (15ns) would be needed for 60MHz operation.
The global SRAM is accessed at address 0x80000000 on processor strobe STRB0.
CODEC
Sixteen stereo audio CODEC devices are employed on the SMT326 to provide 32 channels
of analog input and 32 channels of analog output.
The CODECs have a serial output and are interfaced to the ‘C44 global bus via an XC4006
FPGA. Configuration of the CODECs is performed through an I2C serial interface. The
CODEC can respond to two I2C addresses, primary and alternate. Eight of the CODECs
respond to their primary address, and the other eight to their secondary address. Pairs of
CODECs are then selected within the LED Control register.
DAC
The DAC output signals range from -2.83V to +2.83V (2Vrms) and are available on
the miniature co-ax connectors along the top and bottom edges.
The DAC outputs are subject to a digital filter which limits the bandwidth (0.1dB) to
10 - 20kHz, and is DC coupled.
The differential output of the CODEC is buffered with an op-amp which provides a
single-ended output.
ADC
The ADC input signal range is AC coupled (1Vrms). These signals are presented to
the ADC circuitry through connectors mounted on the top and bottom edges of the
board.
A single-ended analog input is buffered to produce the differential input required by
the codec.
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 7 of 24 SMT326 DSP PC/ISA System User Guide
CODEC Clocking
The CODEC clock is generated by an on-board oscillator. There is no way to change
via software the sampling rate.
The on-board oscillator can be exchanged for any oscillator which is packaged in an
8-pin DIP. The oscillator frequency is chosen such that;-
fosc=m x fsamp < 30MHz
where fosc is the oscillator frequency,
m = oversample rate / 2 = (1024), and
fsamp is the sample rate.
i.e.:
if fosc=50MHz then fsamp=50 Ksamples/sec
CODEC Control
CODEC Start
After power-on or reset, the CODECs will be held in a reset state (not
sampling). To start the CODECs sampling a processor write to address
0x80200020 with D7 set, using processor strobe STRB1, must be performed.
This is a global signal and all CODECs will start at the same time (within one
CODEC input clock period).
CODEC Stop
To stop acquisition a processor write to address 0x80200020 with D7 clear,
using processor strobe STRB1, must be performed. This is a global signal
and all CODECs will stop at the same time. Note that the only advantage of
stopping the CODECs is to reduce power consumption. An alternative to
stopping sampling is to disable the interrupt enable within the ‘C44.
CODEC Interrupt & Status
The CODECs operate in a left/right mode. Although all channels are
sampled at the same point, the serial data from the CODECs are transmitted
in two phases as 16 channels of left followed by 16 channels of right. At the
end of each of these phases an interrupt is signalled on IIOF0. The first
interrupt received after removing reset is from the left channel.
The interrupt must be set to edge triggered as it only remains active for
approximately 120ns (hence it cannot be polled reliably by the ‘C44 within
the IIF register).
When the address 0x80200020 is read, the codec interface status is
returned. Bit 0 reflects the IIOF0 state, and bit 1 indicates which phase (left
or right) is able to be accessed by the ‘C44. When bit 1 is 0, then the ‘C44
can access the first 16 channels (left).
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
Release Page 8 of 24 SMT326 DSP PC/ISA System User Guide
LED Control
An 8 bit latch is provided within the Codec FPGA to enable the state of an on board hex LED
to be changed. The LED is controlled by the 4 lsbs of this register. This register is accessed
at address 0x80200020.
The next 3 msbs of this register select which of the CODECs are selected for configuration
via the I2C interface device.
The msb of this register is used to reset the CODECs. A logic 1 will remove the reset signal.
Global Memory Interface Control Register (GMICR)
Within the 'C44 is a register which determines how the bus is partitioned and how many wait
states to use for accesses.
The value 0x34F4F840 must be programmed into the GMICR. When using an operating
system like 3L, the loading of this register is performed using the value within the ID ROM.
This value will provide 0 wait state access to SRAM (external ready), externally defined wait
states for access to the I2C interface, and n wait states for access to the CODECs.
Codec Interface FPGA
The XC4006 FPGA is configured by the ‘C44. Normally this is done by ‘C44 boot code
resident within the boot ROM. This code would read the spare section of the ID ROM and
use this as configuration data for the FPGA.
The FPGA is configured in a byte wide asynchronous peripheral mode. The PROGRAM pin
is asserted by the ‘C44 writing to address 0x80300000. This pin is de-asserted when address
0x803000000 is read.
C44 Memory Map Summary
Address A20 A4 Function Strobe
(00)30 0000
(70)00 0000
(80)00 0000
(80)10 0000
(80)20 0000+nn
(80)20 0020
(80)30 0000
Local SRAM LSTRB0
ID ROM LSTRB0
0 x Global SRAM STRB0
1 x I2C STRB1
0 0 ADC/DAC nn STRB1
0 1 W:LED & I2C control
STRB1
R:Status,
bit 0 - interrupt status
bit 1 - left/right status
1 x W: Set FPGA PROG
STRB1
R: Clr FPGA PROG
Document Name: SMT326 Ugv2.doc Original Date: 08/11/97
Product Name: SMT326 Revision Date: 08/26/99
Author: Graeme Parker – Fabio Ancona
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