Sundance SMT321 User Manual

Unit / Module Name:

Frequency Generator Module

Unit / Module Number:
Used On:
Document Issue:
Date:

SMT321
All ADC and DAC modules

1.0
10/05/2004

CONFIDENTIAL

Approvals Date

Managing Director
Software Manager
Design Engineer

Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside, Chesham, Bucks. HP5 1PS.
This documents is the property of Sundance and may not be copied nor communicated to a third party
without the written permission of Sundance. © Sundance Multiprocessor Technology Limited 1999

Revision History

10/05/04

Changes Made Issue Initials

First release 1.0 LPS

List of Abbreviations

Abbreviation Explanation

ADC Analog to Digital Converter
BER Bit Error Rate
BOM Bill Of Materials
CDR Clock and Data Recovery
DLL Delay Lock Loop
DSP Digital Signal Processor
FPGA Field Programmable Gate Array
LSB Least Significant Bit
LVDS Low Voltage Differential Signalling
LVPECL Low Voltage Positive ECL
MSB Most Significant Bit
NA Not Applicable
PC Personal Computer
PCB Printed Circuit Board
PCI Peripheral Component Interconnect
POR Power On Reset
SMT Sundance Multiprocessor Technology
SPI Serial Peripheral Interface
TBD To Be Determined
TI Texas Instruments
VCO Voltage Controlled Oscillator

Table of Contents

1 Introduction..................................................................................................................7

1.1 Overview ...............................................................................................................7

1.2 Module Features....................................................................................................7

1.3 Related Documents...............................................................................................7

2 Functional Description..................................................................................................8

2.1 Module Overview...................................................................................................8

2.2 Main Analog Characteristics..................................................................................9

2.3 Data Stream Description......................................................................................10

2.3.1 Description of Internal FPGA Blocks .............................................................10

2.4 Clock Structure....................................................................................................11

2.5 Power Supply and Reset Structure......................................................................12

2.6 MSP Functionality................................................................................................14

2.7 Trigger Output.....................................................................................................14

2.8 Analog Signal Output...........................................................................................15

2.9 Clock Output........................................................................................................16

2.10 Connectors Pin outs ..........................................................................................16

2.10.1 FPGA & MSP JTAG connector....................................................................17

2.10.2 Digital IOS ...................................................................................................18

2.10.3 Trigger Connectors .....................................................................................18

2.10.4 Analog Signal Connectors...........................................................................18

2.10.5 Clock Connectors........................................................................................18

2.11 FPGA IOS .........................................................................................................18

3 Description of interfaces.............................................................................................21

3.1 MSP430 Interface................................................................................................21

3.2 Digital Pod Interface............................................................................................21

3.3 Clock Synthesizers Interface ...............................................................................21

3.4 TIM Interface.......................................................................................................21

4 Control Register Settings ...........................................................................................21

4.1 Control Packet Structure......................................................................................21

4.2 Reading and Writing Registers ............................................................................22

4.3 Memory Map .......................................................................................................23

4.4 Register Descriptions...........................................................................................24

4.4.1 Com In Scratch Registers .............................................................................24

4.4.2 Clock Control Registers .................................................................................24

4.4.3 Trigger Control Registers .............................................................................. 25

4.4.4 Digital Pod Registers.....................................................................................26

4.4.5 Digital IOS output register.............................................................................26

4.4.6 Firm Ware Version........................................................................................27

4.4.7 Com Out Scratch Registers...........................................................................27

4.4.8 Smt321 Serial Number Registers..................................................................27

4.4.9 Smt321 Air Temp and Smt321 Diode Temp..................................................27

4.4.10 Voltage registers of the module...................................................................27

4.4.11 FPGA Dip Register......................................................................................27

5 PCB Layout................................................................................................................28

6 Waveform Outputs .....................................................................................................29

7 User Manual...............................................................................................................39

7.1 Read SMT321 Firmware Version.........................................................................40

7.2 Write to the SMT321 Scratch Register.................................................................40

7.3 Read the SMT321 Scratch Register....................................................................40

7.4 Read SMT321 Temperatures ..............................................................................40

7.5 Read the SMT321 Serial Number........................................................................41

7.6 Read all the SMT321 Voltages............................................................................41

7.7 Write any command to SMT321 ..........................................................................41

7.8 Read the SMT321 dip switches ...........................................................................41

7.9 Setup Trigger A ...................................................................................................41

7.10 Setup Trigger B .................................................................................................41

7.11 Setup VCO 1.....................................................................................................41

7.12 Setup VCO 2.....................................................................................................42

7.13 Setup Clock A....................................................................................................42

7.14 Setup Clock B....................................................................................................42

7.15 Multiplex Trigger A CONT or PULSE.................................................................42

7.16 Multiplex Trigger B CONT or PULSE.................................................................42

7.17 Setup Pulse on Trigger A...................................................................................42

7.18 Setup Pulse on Trigger B...................................................................................42

Table of Tables

Table 1. VCO models frequency ranges..........................................................................9

Table 2. Analog characteristics of SMT321 low frequency configuration.........................9

Table 3. Analog characteristics of SMT321 high frequency configuration........................9

Table 4. User IOS of FPGA in SMT321. ........................................................................21

Table 5. Register Memory Map.....................................................................................24

Table 6. Clock Control setup registers...........................................................................24

Table 7. Test bit configurations. ....................................................................................24

Table 8. Output division configurations..........................................................................25

Table 9. Digital pod register setup.................................................................................26

Table 10. Digital IO register setup.................................................................................26

Table of Figures

Figure 1.Functional Block Diagram of the SMT321. ........................................................8

Figure 2. Data path of the FPGA and module................................................................ 10

Figure 3. SMT321 Power Structure...............................................................................13

Figure 4. Reset Generation and Distribution. ................................................................14

Figure 5. Trigger path from FPGA to output..................................................................15

Figure 6. Analog signal path from FPGA to output. .......................................................16

Figure 7. Clock path from FPGA to output.....................................................................16

Figure 8. Connectors present on the SMT321...............................................................17

Figure 9. Split JTAG Cable for SMT321........................................................................17

Figure 10. Digital IOS connector present on the SMT321.............................................. 18

Figure 11. Setup Packet Structure................................................................................22

Figure 12. Control Register Read Sequence.................................................................23

Figure 13. Clock output equation...................................................................................25

Figure 14. Trigger with 1 clock high and 1 clock low......................................................25

Figure 15. One pulse generated on trigger A output (ChannelATrigPulse)....................26

Figure 16. Module Top View.........................................................................................28

Figure 17. Module Bottom View....................................................................................28

Figure 18. Trigger A: 0 high time 0 low time. Positive side of signal..............................29

Figure 19. Trigger B: 10 high time 2 low time. Positive side of signal............................30

Figure 20. Clock B: Freq 62MHz in time. Positive side of signal....................................31

Figure 21. Clock B: Freq 62MHz in frequency................................. ..............................32

Figure 22. Clock B: 233MHz in time. Positive side of signal. .........................................33

Figure 23. Clock B: 233MHz in frequency.....................................................................34

Figure 24. VCO2: 247MHz in time................................................................................. 35

Figure 25. VCO2: 247MHz in frequency................................. .......................................36

Figure 26. VCO1: 91MHz in time...................................................................................37

Figure 27. VCO1: 91MHz in frequency..........................................................................38

1 Introduction

1.1 Overview

The SMT321 is a single width TIM module. It is capable of generating:

• two separate LVPECL triggers continuous or single pulse,

• two separate analog test signals with the frequency depending on the VCO’s on

the board,

• two separate LVPECL clock signals.

The triggers are generated by a Xilinx Spartan 3 FPGA (XC3S400 – TQ144) this FPGA
also controls all the control register settings via the Comports. The analog test signals
are generated by two separate VCO’s (Microwave Corporations UMS series of VCO’s)
for different frequency ranges. Finally the two clock signals are generated by Micrel high
frequency clock synthesizers.

1.2 Module Features

The main features of the SMT321 are shown in the following list.

• Six seprate channels consisting of two triggers, two analog signals and two clock
signals.

• Triggers range from 75Hz to 5MHz and the high and low time of each trigger is
programmable.

• Each analog signal varies in frequency depending on the VCO mounted in the
channel. The VCO ranges available can be seen in Table 1.

• Clock signals range from 50MHz to 950MHz.

• Standard Sundance Comports for easy interconnection to other Sundance

products.

1.3 Related Documents

[1] TIM specifications.

ftp://ftp2.sundance.com/Pub/documentation/pdf-files/tim_spec_v1.01.pdf

[2] MICREL SY89430VZC and SY89429AZC specifications

http://www.micrel.com

[3] ANALOG DEVICES AD5235 specifications

http://www.analog.com

2 Functional Description

2.1 Module Overview

The following shows a block diagram of the SMT321.

Temprature

Sensor

T

Comport 3

I

M

C

o

Control

n

Signals

n
e
c

t

Comport 0

o

r

Texas Inst

MSP430F149

Voltages from

board

Config

Serial number

Xilinx Spartan 3 FPGA

(XC3S400 - TQ144)

TTL to

LVPECL

LVPECL

Clock

Generation

Trigger

Connector

TTL to

LVPECL

VCO

VCO

LVPECL

Clock

Generation

Clock

Connector

Trigger

Connector

Analog

Connector

Analog

Connector

Clock

Connector

Figure 1.Functional Block Diagram of the SMT321.

The user sets up the triggers, analog and clock signals in the FPGA via the comports
using a software interface on the Personal Computer. This sets up the internal registers
of the firmware design.

The triggers are generated by the FPGA itself. It scales a 10MHz clock by using two
counters, one for the high time of the trigger and one for the low time of the trigger. Thus
the maximum frequency attainable by the triggers is 5MHz.

The analog signals are generated by generating a variable voltage on the VCO using a
1024 position digital potentiometer. Using the FPGA to program the potentiometer to a
certain voltage the VCO’s swings to new frequencies depending on the voltage applied
to them.

Finally the clocks are generated by clock synthesizers. The synthesizers are
programmed to a certain frequency using the FPGA.

2.2 Main Analog Characteristics

The SMT321 comes in two different configurations. The main differences on the two
modules are clock generation and analog signal generation. Table 2 shows the
configuration of the lower frequencies module. Table 1 shows the frequencies attainable
by the various VCO’s implemented on the SMT321. The high frequency configuration
board is shown in Table 3.

VCO Model Number Minimum Frequency Maximum Frequency

UMS-150-A16
UMS-300-A16
UMS-535-A16

UMS-1000-A16

75MHz 150MHz
150MHz 300MHz
300MHz 535MHz
500MHz 1000MHz

Table 1. VCO models frequency ranges.

SMT321 (Lower Frequencies Configuration) Output
Triggers (LVPECL)

Channel A 75Hz – 5MHz
Channel B 75Hz – 5MHz
Analog Signals (Analog)
Channel A 75MHz – 150MHz
Channel B 150MHz – 300MHz
Clock Signals (LVPECL)
Channel A 25MHz – 400MHz
Channel B 25MHz – 400MHz

Table 2. Analog characteristics of SMT321 low frequency configuration.

SMT321 (Higher Frequencies Configuration) Output
Triggers (LVPECL)

Channel A 75Hz – 5MHz
Channel B 75Hz – 5MHz
Analog Signals (Analog)

Channel A 300MHz – 535MHz
Channel B 500MHz – 1000MHz
Clock Signals (LVPECL)

Channel A 50MHz – 950MHz
Channel B 50MHz – 950MHz

Table 3. Analog characteristics of SMT321 high frequency configuration.

2.3 Data Stream Description

The module and the FPGA have three different data paths depending on the output.
Each architecture has two separate channels for a total of six outputs on the SMT321.

The following figure illustrates the data path of the FPGA and module.

FPGA

Comport

Comport

Decoding

Trigger

Registers

Digital Pod

Registers

Clock

Registers

Trigger

Setup x 2

Trigger

Pulse

Setup x 2

Digital Pod

Setup

Clock

Setup x2

Mux x2

Synehsizer x2

VCO x2

Clock

Output

Output

Output

Output

Output

Output

Figure 2. Data path of the FPGA and module.

The user configures the SMT321 via the comport decoding block in firmware. All the
registers needed for the generation of the test signals is configured by the decoding
block and then all the setup blocks are enabled. Once the setup blocks are enabled the
registers values are clocked into the different blocks which activates the different signals.

If a change in any channel is desired the user sends the change to the specific register
and enables the activate pulse on the specific channel. The new regis ter value will be
clocked into the specific setup block and the chosen signal will change accordingly.

2.3.1 Description of Internal FPGA Blocks

Comport Decoding

This block receives the module setting made by the user via the DSP interface using the
PC. It then decodes the data and configures the specific registers.

Trigger Registers, Trigger Setup, Trigger Pulse Setup and Multiplexer

The trigger setup consist of six 16-bits registers, three enable signals and two
multiplexer signals. The last two signals are needed to select between a continuous
trigger and a single pulse on each channel.

The enable signals are split up into one for both continuous triggers and one each for the
pulse triggers. Separate enables are needed on the pulse generators because when
asserted a single pulse goes out on the channel and then the channel stays inactive till
the next enable on the pulse generator.

There are six 16-bit registers for the trigger operation block in firmware. They are split up
between the two channels thus three per channel. Each channel has a trigger high
register, trigger low register and a pulse high register. The first two registers are used in
the generation of the continuous trigger. The first register sets up the high time for the
trigger and the second the low time for the trigger. The last register sets up the high time
for the single pulse. The channel is switched between the two signals using a multiplexer
and the multiplexer signal for the certain channel.

Digital Pod Registers and Digital Pod Setup

As the comport is implemented on the SMT321 to be able to only send data in 16 bits
the digital pod’s registers are split up into two as it requires a 24bit data stream for setup.
The comport sends the first data, which consists of the upper (MSB) 16 bits of the data
word, to the digital pod and then a second transmit which contains the lower (LSB) 8 bits
of the digital pod’s data word. Thus 16 bits + 8 bits = 24 bits.

These two registers are then combined in a single register which is sent to the digital
pod setup by sending the update signal to the digital pod firmware module. Here the
firmware generates a sequence of handshaking protocols and clocks the 24bit word into
the digital pod. The pod has a resolution of 1024 positions which is dealt into a 0 Volt to
18 Volt swing on the VCO’s. This results into a 0.0175V step size. But most of the VCO’s
only operate from 1 Volt to 16 Volts thus some resolution is lost to these operating
regions.

Clock Registers and Clock Setup

There are two 16 bit registers in the clock setup. The data word needed for the setup of
the clock is only 14 bits long thus the 16 bit registers are sufficient to receive data from
the comport in one cycle. Each clock synthesizer (two present on the board) has its own
register. When the comport receives the data for the clock registers it configures the
registers accordingly and asserts the enable pin on the clock setup firmware.

The clock setup firmware generates the handshaking protocols and then clocks the data
into the synthesizers. The synthesizers then generate a clock depending on the setup
given by the user.

2.4 Clock Structure

An external 100MHz oscillator provides the FPGA with a clock. All the internal firmware
operates on this frequency.

The Microcontroller is driven by an external 8MHz resonator.

Finally the two clock synthesizers are driven by external 16MHz crystal oscillators.

These are the only blocks needing clocks to operate.

2.5 Power Supply and Reset Structure

The SMT321 conforms to the TIM standard for single width modules. The TIM
connectors supply the module with 5.0V. The module also requires an additional 3.3V
power supply, which must be provided by the two diagonally opposite mounting holes.
This 3.3V is present on all Sundance TIM carrier boards. From the 5.0V the FPGA Core
Voltage (V
The FPGA IO Voltage (V

A TI MSP430 low power microprocessor is located on the module. This microprocessor
controls the power sequencing for the FPGA. High efficiency DC/DC converters are
used to generate the lower voltages.

The MSP430 microprocessor also controls the reset structure for the SMT321. There are
two possible reset sources for the SMT321:

1. A reset is received over the TIM connector

2. After power up an internal POR in the MSP430 causes a reset

The MSP430 distributes the reset to the FPGA. The following two diagrams illustrate the
power distribution and the reset distribution on the SMT321:

= 1.2V) and the FPGA Auxiliary voltage (V

CCINT

= 3.3V) is taken straight from the TIM mounting holes.

CCO

= 2.5V) is generated.

CCAUX

Figure 3. SMT321 Power Structure.