Sundance SMT319 User Manual
SMT319
User Manual
User Manual (QCF42); Version 3.0, 5/2/01; © Sundance Multiprocessor Technology Ltd. 2001
Version 1.0.7 Page 2 of 45 SMT319 User Manual
Revision History
Date Comments Engineer Version
22/09/03 First rev, based on 365 JPA 1.0.0
16/06/04 Updated: output flag register @9007C000 SM 1.0.1
16/07/04 Added: Virtex memory Map SM 1.0.2
03/09/04 Added: J1, J2, J3, J4 connectors reference SM 1.0.3
06/09/04 Added: Video cables reference SM 1.0.4
21/01/05 Updated: PCB layout SM 1.0.5
18/05/05 Added: Caution Global Bus not implemented SM 1.0.6
13/10/05 Added: Ordering information section to
distinguish between PAL and NTSC variations.
GP 1.0.7
Version 1.0.7 Page 3 of 45 SMT319 User Manual
Table of Contents
Revision History....................................................................................................... 2
Contacting Sundance............................................................................................... 7
Contacting Sundance............................................................................................... 7
Notational Conventions ........................................................................................... 8
C60 ......................................................................................................................... 8
SDB ........................................................................................................................ 8
Register Descriptions.............................................................................................. 8
Outline Description .................................................................................................. 9
Block Diagram ........................................................................................................ 10
Architecture Description........................................................................................ 10
TMS320C6416 ......................................................................................................... 11
Boot Mode............................................................................................................. 11
Flash Boot......................................................................................................... 11
HPI Boot............................................................................................................ 11
EMIF Control Registers......................................................................................... 12
SDRAM ................................................................................................................. 13
FLASH .................................................................................................................. 13
Virtex FPGA ...................................................................................................... 13
Reprogramming the firmware and boot code ...................................................... 13
Interrupts................................................................................................................. 14
Sundance Digital Links.......................................................................................... 14
SDB.......................................................................................................................... 14
SDB Clock selection ............................................................................................. 14
Global bus............................................................................................................... 15
Video interfaces...................................................................................................... 16
Video Output Mode Control Register .................................................................... 22
Video Output Status.............................................................................................. 23
Video Input Status................................................................................................. 24
Output Flag Register............................................................................................. 25
Input Flag Register................................................................................................ 25
Interrupt Control Register...................................................................................... 26
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Connectors location .............................................................................................. 27
Connectors reference ........................................................................................... 27
Video cables reference ......................................................................................... 27
Available resources............................................................................................... 28
Video input interface ............................................................................................. 28
Video output interface ........................................................................................... 29
LED Setting............................................................................................................. 31
CONFIG & NMI ........................................................................................................ 32
Timer........................................................................................................................ 32
IIOF interrupt........................................................................................................... 32
Code Composer...................................................................................................... 33
Application Development....................................................................................... 34
Software .................................................................................................................. 35
Introduction ........................................................................................................... 35
Functions description ............................................................................................ 35
Sundance Graphical Interface ........................................................................... 35
Video Decoder library ........................................................................................ 36
Video Encoder library ........................................................................................ 37
Operating Conditions............................................................................................. 38
Safety.................................................................................................................... 38
EMC...................................................................................................................... 38
General Requirements.......................................................................................... 38
Power Consumption.............................................................................................. 38
PCB Layout Details ................................................................................................ 39
Component Side ................................................................................................... 39
Virtex Memory Map................................................................................................. 40
SHB pin-out............................................................................................................. 41
SMT319 Schematics/FPGA Pin-Out ...................................................................... 42
Ordering Information.............................................................................................. 43
Index........................................................................................................................ 45
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List of tables
Table 1: EMIF control registers................................................................................. 12
Table 2: SDB clock selection .................................................................................... 14
Table 3: Video output mode control register ............................................................. 22
Table 4: Video output status..................................................................................... 23
Table 5:Video input status ........................................................................................ 24
Table 6: output flag register...................................................................................... 25
Table 7: Interrupt control register.............................................................................. 26
Table 8: overall available FPGA resources............................................................... 28
Table 9: Video output module resources usage ....................................................... 30
Version 1.0.7 Page 6 of 45 SMT319 User Manual
List of figures
Figure 1: SMT319 block diagram.............................................................................. 10
Figure 2: SMT319 SDBs location ............................................................................. 14
Figure 3: Video interface block diagram ................................................................... 17
Figure 4: Text overlay example ................................................................................ 19
Figure 5: FPGA video control registers..................................................................... 21
Figure 6: Video connector location ........................................................................... 27
Figure 7: Video connectors....................................................................................... 27
Figure 8: Video input module files ............................................................................ 29
Figure 9: Video output module files .......................................................................... 29
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Contacting Sundance
You can contact Sundance for additional information by login onto the support
system
support.sundance.com or sending an email to support@sundance.com.
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Notational Conventions
C60
The terms C60, C64xx and TMS320C64xx will be used interchangeably throughout
this document.
SDB
The term SDB will be used throughout this document to refer to a 16 bit data bus
carried by either an SDB connector or an SHB connector. The SHB connector can
carry two such SDB buses.
Register Descriptions
The format of registers is described using diagrams of the following form:
31–24 23–16 15–8 7–0
OFLAGLEVEL
R,00000000 RW,10000000 R,00000000 R,10000000
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R Readable by the CPU
W Writeable by the CPU
RW Readable and writeable by the CPU
Binary digits indicate the value of the field after reset.
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Outline Description
The SMT319 is a C64xx-based size 1 TIM offering the following features:
TMS320C6416 processor running at 600MHz
Four 20MB/s Sundance Digital Links (SDL)
32 MB of SDRAM
2MByte Flash ROM for boot code and FPGA programming
Global expansion connector (Global Bus interface not implemented in this version
of the board)
High bandwidth data I/O via 2 Sundance Digital Buses (SDB).
PAL/NTSC/SECAM video input (This is a manufacturing option. Please state
video format when ordering.)
PAL/NTSC video output
CAUTION:
First release of SMT319 : 2 SDB, 4 SDL, Video input and Video output.
Doesn’t implement the Global Bus interface. Therefore, you HAVE
TO plug the SMT319 in the second TIM Site of the carrier board
(i.e. SMT310Q) and connect the T1C3 to T2C3 if the SMT319 is
used alone in the system.
Doesn’t implement text overlay feature.
Version 1.0.7 Page 10 of 45 SMT319 User Manual
Block Diagram
Figure 1: SMT319 block diagram
Architecture Description
The SMT319 TIM consists of a Texas Instruments TMS320C6416 running at up to
600MHz. Modules are populated with 32Mbytes SDRAM.
A Field Programmable Gate Array (FPGA) is used to manage global bus accesses
and implement four Sundance Digital links (SDL) and two Sundance Digital Buses.
This is a Xilinx VirtexII device.
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TMS320C6416
The processor will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the C60, which then
multiplies this by 12 internally.
Boot Mode
The SMT319 can be configured to use one of two boot modes after a reset. These
are HPI (host port interface) and Flash.
Flash Boot
1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT319 then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance High-speed Buses.
This step must have been completed before data can be sent to the SDL from
external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the four
SDLs until data appears on one of them. The bootstrap will then load a
program in boot format from that port; the loader will not read data arriving on
other ports.
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 1s for a SMT319 (600MHz clock).
A typical time to wait after releasing the board reset should be in excess of this
delay, but no damage will result if any of the I/Os are used before they are fully
configured. In fact, the comm. Ports will just produce a not ready signal when data
is attempted to be transferred during this time, and then continue normally after
the FPGA is configured.
HPI Boot
The C60’s HPI (16 bit data interface) is connected directly to the FPGA. This
mode is therefore only used by custom FPGA configurations.
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EMIF Control Registers
The C6416 has two external memory interfaces (EMIFs). One of these is 64 bits
wide, the other 8 bits.
The C60 contains several registers that control the external memory interfaces
(EMIFs). A full description of these registers can be found in the C60 Peripherals
Reference Guide[0].
The standard bootstrap will initialise these registers to use the following
resources:
Table 1: EMIF control registers
Memory
space
(EMIFA)
CE0 SDRAM 0x80000000 - 0x81FFFFFF
CE1 VirtexII 0x90000000 - 0x9FFFFFFF
Memory space
(EMIFB)
CE1 Flash 0x64000000 – 0x641FFFFF
Resource Address range
Internal program memory
0x00000000 - 0x000FFFFF
(1Mbyte)
Resource Address range
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SDRAM
Memory space CE0 is used to access 32MB of SDRAM over EMIFA. The SDRAM
operates at EMIF clock speed (typically 100MHz).
FLASH
A 2MByte Flash ROM device is connected to the C60 EMIFB.
The ROM holds boot code for the C6x, configuration data for the FPGA, and optional
user-defined code.
A software protection algorithm is in place to prevent programs accidentally altering
the ROM’s contents. Please contact Sundance for further information about reprogramming this device.
Virtex FPGA
The SMT319 incorporates a Xilinx Virtex XC2V2000 FPGA. This device controls the
majority of the I/O functionality on the module, including SDLs, SHBs, Global Bus,
timers and interrupts.
This device requires configuring after power-up (the Virtex technology is an SRAM
based logic array). This configuration is performed by the DSP as part of the boot
process.
Reprogramming the firmware and boot code
Sundance Flash Programming Utility (SMT6001) supports SMT319.
The SMT6001, allows you to manipulate the contents of the Flash ROM and perform
the following operations:
• Install or update the bootloader
• Install or update the FPGA data
• Store, enable and disable a user application
• Display information about the contents of the ROM
Please refer to the following link for more information about SMT6001:
http://www.sundance.com/docs/SMT6001 User Manual.pdf
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Interrupts
See general firmware description [7]
Sundance Digital Links
The SMT319 provides 4 SDLs. They are SDL0, 1, 3, and 4.
See general firmware description [7]
SDB
The SMT319 provides two Sundance Digital Buses (SDB).
They are numbered SDB0 for SDBA and SDB2 for SDBC.
SDBC SDBA
Figure 2: SMT319 SDBs location
See general firmware description [7]
SDB Clock selection
At any time you can change the speed of an SDB clock by altering SDBCLK.
Table 2: SDB clock selection
Module SDBCLK Clock Speed
SMT319
0 50MHz
1 100MHz
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