Sundance SMT317 User Manual
SMT317
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Version 6.1 Page 2 of 24 SMT317 User Manual
Revision History
Date Comments Engineer Version
20/03/01 First Issue MM 1.0
10/09/01 Minor changes SS 2.0
16/11/01 Major changes E.P 3.0
28/11/01 Reduction to Comm-port 3 only for ADC control
E.P 3.1
Comm-port.
13/12/01 SMT317v2:
E.A 4.0
• Xilinx XCV300 Virtex FPGA only
• Addition of a internal trigger
• Addition of features in the ADC control
21/02/02 Addition of Bookmarks and hyperlinks
E.A 4.1
Changes in the control word
28/02/02 Explanation of the trigger signal
E.A 4.2
Overflowed FIFOs
21/04/02 Addition of paragraph 11.x
E.A 5
Up dates related to the firmware v2.2
08/07/02 Paragraph 14.2: jumper position correction
E.A. 5.1
Explanation of the output frequency on the SDB
29/11/02 Minor changes E.A. 5.2
01/09/05 Data packeting detailed. Addition of 1 extra bit in
E.P 6.0
control register for burst size. Remove of 100
MHz SDB clock option. New SMT6500 support
24/01/06 Minor changes SM 6.1
Version 6.1 Page 3 of 24 SMT317 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents....................................................................................................... 3
Table of figures........................................................................................................... 4
Table of tables............................................................................................................ 4
Overview..................................................................................................................... 5
1. EMC................................................................................................................. 6
2. Power............................................................................................................... 6
3. Notational convention ...................................................................................... 6
4. Outline Description........................................................................................... 7
5. Power up sequence......................................................................................... 8
6. ADC Sub-System............................................................................................. 8
6.1. Input Level................................................................................................ 8
6.2. Output Codes............................................................................................ 8
7. Communication ports....................................................................................... 9
7.1. Overview................................................................................................... 9
8. SDB ............................................................................................................... 10
9. Data formatting.............................................................................................. 10
10. Clock selection........................................................................................... 11
10.1. ADCs Sampling clock.......................................................................... 11
10.2. SDB output clock................................................................................. 11
10.3. Overflowed FIFOs............................................................................... 12
11. FPGA ......................................................................................................... 12
11.1. Fpga configuration .............................................................................. 12
12. ADCs Clock Source.................................................................................... 12
13. ADC Control............................................................................................... 13
13.1. Programmable Clock Divider............................................................... 14
13.2. LED 1.................................................................................................. 14
13.3. Synchronization signal........................................................................ 14
13.4. Trigger................................................................................................. 14
13.5. Control register description ................................................................. 15
14. Connectors and Jumpers Positions............................................................ 17
Version 6.1 Page 4 of 24 SMT317 User Manual
15. Connectors................................................................................................. 18
16. Jumpers ..................................................................................................... 19
16.1. JMP1: Control Comm-port Select........................................................ 19
16.2. JMP2: SDB Clock speed select and external trigger........................... 20
17. Input Circuitry............................................................................................. 21
17.1. SDB Pinout.......................................................................................... 22
18. Example Code............................................................................................ 23
Table of figures
Figure 1: Register Format........................................................................................... 6
Figure 2: Notational convention.................................................................................. 6
Figure 3: Block Diagram............................................................................................. 7
Figure 4: ADCs control register ................................................................................ 13
Figure 5: SMT317v2 top view................................................................................... 17
Figure 6: JUMPER JMPx.......................................................................................... 19
Figure 7: ADC Input circuitry..................................................................................... 21
Table of tables
Table 1: Control Register description ....................................................................... 16
Table 2: Comm-port selection................................................................................... 19
Table 3: Clock speed selection................................................................................. 20
Table 4: SDB Pinout................................................................................................. 22
Version 6.1 Page 5 of 24 SMT317 User Manual
Overview
The SMT317v2 is a size 1 TIM offering the following features:
• Communication ports for control
• 8 channels, 16-bit simultaneous sample ADC
• High bandwidth data output via a single 16-bit SDB (Sundance Digital Bus)
Version 6.1 Page 6 of 24 SMT317 User Manual
1. EMC
This module is designed to operate from within an enclosed host system, which is
built to provide EMC shielding. Operation within the EU EMC guidelines is not
guaranteed unless it is installed within an adequate host system.
This module is protected from damage by fast voltage transients originating from
outside the host system, which may be introduced through the output cables.
Short-circuiting any output to ground does not cause the host PC system to lock up
or reboot.
2. Power
This module must be fixed to a TIM40 compliant carrier board. Additionally, a 3v3
power source must be provided to the fixings. This is normally achieved by means of
a power source provided directly through conducting pillars on the carrier board. Onboard dc-dc converters provide power for the analog components on this module.
All of the analog circuitry is shielded on the top and bottom of the module using
custom RFI shielding cans.
3. Notational convention
The format of registers is described using a diagram of the following form:
31–20 19–17 16–8 7–0
LED[4:2]
W,000000000000 W,100 W,000000000 W,10000000
Figure 1: Register Format
The digits at the top of the diagram indicate bit positions within the register and the
central section names bits or bit fields. The bottom row describes what may be done
to the field and its value after reset. Shaded fields are reserved and should only ever
be written with zeroes.
R
W
Readable by the CPU
Writeable by the CPU
RW
Readable and writeable by the CPU
Binary digits indicate the value of the field after reset
Figure 2: Notational convention
Version 6.1 Page 7 of 24 SMT317 User Manual
4. Outline Description
The SMT317v2 module is an ADC-based size 1 TIM offering the following features:
• Eight 16-bits ADCs running at an output word rate of up to 1.2 MHz for input
bandwidths up to 460 kHz.
• a Xilinx XCV300 Virtex FPGA.
• FPGA programming via communication port (comm-port3).
• High bandwidth data I/O via 1 Sundance Digital Bus (SDB).
JUMPERS
SYNC
Clock Buffer
ADC SUB-SYSTEM
8 ADCs
4 LEDs
4 I/Os
selection
Control Comm-port
Clock
Local clock
37.6 MHz
External clock
External SYNC
Sample clock
CONFIG CPLD
on Comm-port3
Clock select
Internal sync
Comm-port 3
PRIMARY
Figure 3: Block Diagram
VIRTEX
Comm-port 3
1 SDB
S
D
B
Version 6.1 Page 8 of 24 SMT317 User Manual
5. Power up sequence
At power up the config CPLD waits for a bitstream to configure the FPGA.
The Virtex FPGA from Xilinx is volatile in nature, and requires reconfiguring every
time the module is powered on.
From the moment the module is powered on to the time when the FPGA is
configured:
• The ADC sampling clock is the external clock (beware to respect the
maximum frequency rating, see
ADC Datasheet AD7723)
• The ADC SYNC (See
keep the ADCs in reset state
After the FPGA is configured the ADC controls default to the values in
Table 1: Control Register description.
ADC Datasheet AD7723) signal is maintained high to
6. ADC Sub-System
It consists of 8 Analog Devices AD7723 converters. These provide an overall system
performance with an ENOB of 14 (minimum) for each of the eight channels.
All ADCs simultaneously sample using the same clock.
6.1. Input Le vel
The input to the ADC module is DC coupled with a pk-pk level of 4v. This is centred
about 0v.
Vmin= -2v, Vmax= +2v.
6.2. Output Codes
The converted samples are presented on the SDB connector as 16 bits twos
complement binary.
Code 0x8000 is equivalent to –Vmax
Code 0x0000 is equivalent to 0V
Code 0x7FFF is equivalent to +Vmax
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