Sundance SMT310Q User Manual
SMT310Q
User Manual
User Manual (QCF42); Version 3.1, 31/03/03; © Sundance Multiprocessor Technology Ltd. 2003
Version 2.1 Page 2 of 55 SMT310Q User Manual
Revision History
Date Comments
31-10-01 Original Document SP 0.8
20-11-01 Global Bus Accessing AJP 0.9
15-01-02 Final Re-Editing SP 1.0
22-01-02 JTAG performance figures SP 1.1
04-03-02 Comport Mirrors SP 1.2
06-03-02 Comport Int_Control Mirror SP 1.3
29-05-02 Installation Update SP 1.4
13-06-02 AJP 1.5
28-01-03 Editing SP 1.6
24-03-03 General revision PSR 1.7
23-06-03 Firmware upgrade links HV 1.8
07-01-05 EPLDs and EPROM reprogramming SM 1.9
15-07-05 Complement: Section 15. Firmware Updates SM 2.0
20-12-05 Complement: Section 18. LED description MS 2.1
Engineer Version
Version 2.1 Page 3 of 55 SMT310Q User Manual
Table of Contents
1. Introduction ....................................................................................................... 6
2. Installing the SMT310Q ..................................................................................... 7
2.1 Software installation ..................................................................................... 7
2.2 Hardware installation.................................................................................... 7
2.3 Testing the hardware.................................................................................... 7
3. Hardware Overview ........................................................................................... 9
3.1 Local Bus ..................................................................................................... 9
3.2 V363EPC PCI Bridge Chip......................................................................... 10
3.3 JTAG controller .......................................................................................... 10
3.4 Shared SRAM ............................................................................................ 10
3.5 Control EPLD ............................................................................................. 10
3.6 Onboard resources..................................................................................... 11
3.6.1 SDB..................................................................................................... 11
3.6.2 Host comport link ................................................................................ 11
4. Comports ......................................................................................................... 12
4.1 C_BUF ....................................................................................................... 12
4.2 Buffered External Comport......................................................................... 16
4.3 Comport to PCI Interface............................................................................ 16
4.3.1 Comport Registers (BAR1, Offset 1016) .............................................. 16
4.3.2 Control Register (BAR1, Offset 1416, WRITE-ONLY).......................... 17
4.3.3 Status Register (BAR1, Offset 1416, Read-Only)................................. 18
4.3.4 Interrupt Control Register (BAR1, Offset 1816) .................................... 19
4.4 Comport Direction ...................................................................................... 19
5. Sundance Digital Bus (SDB)........................................................................... 20
6. JTAG Controller............................................................................................... 21
6.1 Using the SMT310Q External/Internal JTAG with TI Tools. ....................... 22
7. Global/Local Bus Transfers, DSP ↔ PCI. ...................................................... 23
7.1 Mailbox Accesses....................................................................................... 23
7.1.1 Doorbell Interrupts............................................................................... 24
7.2 DSP Interrupt Control ................................................................................. 24
7.3 DSP To Local Aperture 0 control and Accessing ....................................... 25
7.4 DSP Signals ............................................................................................... 26
Version 2.1 Page 4 of 55 SMT310Q User Manual
8. Interrupts.......................................................................................................... 29
8.1 SMT310Q-To-PCI Interrupts ...................................................................... 29
8.2 PCI-To-SMT310Q Interrupts ...................................................................... 30
8.3 Interrupt Registers...................................................................................... 30
8.3.1 INTREG Register (BAR1, Offset 4016) ................................................ 31
9. Memory Maps .................................................................................................. 32
9.1 PCI Bus Memory Map ................................................................................ 32
9.1.1 PCI Bridge Chip Internal Register (BAR0) .......................................... 32
9.1.2 I/O Space Register Assignments (BAR1)............................................ 32
9.1.3 Memory Space Assignments (BAR2).................................................. 33
9.1.4 DMA Engine........................................................................................ 33
9.2 Local Bus Memory Map.............................................................................. 34
10. Stand-Alone Mode........................................................................................... 35
11. Specifications .................................................................................................. 36
11.1 Performance Figures.................................................................................. 36
11.2 Relative JTAG speed ................................................................................. 37
11.3 Mechanical Dimensions ............................................................................. 37
11.4 Power consumption.................................................................................... 37
12. Cables and Connectors .................................................................................. 38
12.1 SDB............................................................................................................ 38
12.1.1 SDB Connector ................................................................................... 38
12.2 Comports.................................................................................................... 38
12.2.1 FMS Cabling ....................................................................................... 38
12.2.2 Buffered Comport Cabling................................................................... 39
12.3 JTAG cabling.............................................................................................. 40
12.4 Reset and Config headers.......................................................................... 44
13. Expansion Header (J2).................................................................................... 45
14. JTAG Interface circuits ................................................................................... 46
14.1 Signal Description ...................................................................................... 46
15. Firmware Upgrades ......................................................................................... 48
15.1 CPLD and EPROM reprogramming ........................................................... 49
15.1.1 CPLDs updating .................................................................................. 49
15.1.2 EPROM updating ................................................................................ 51
Version 2.1 Page 5 of 55 SMT310Q User Manual
16. Checking for hardware resource conflicts.................................................... 52
17. Where’s that Jumper?..................................................................................... 54
18. LED description............................................................................................... 55
Version 2.1 Page 6 of 55 SMT310Q User Manual
1. Introduction
The SMT310Q is a full-length PCI board that can carry up to four, industry-standard,
TIM format processor modules. Sundance provides a large range of these TIMs.
Features:
• Processor interconnection using comports. Direct comport and SDB access to the
host is also provided;
• A software-configurable routing matrix to allow certain comport connectivity
without needing external cables;
• 1MB of shared SRAM between the host and TIM site 1 (the Master TIM site);
• On-board JTAG controller to allow debugging using Code Composer. The board
can also be used as a JTAG master for debugging remote systems;
• On-board PCI bridge chip to provide DMA, mailbox events, and interrupts;
• PCI access between the host and the Master TIM site at burst speeds in the
range 60–100MB/s.
Version 2.1 Page 7 of 55 SMT310Q User Manual
2. Installing the SMT310Q
2.1
Software installation
You should install the SMT6300 software package before plugging the
hardware into your PC. The SMT6300 sets up device drivers and test utilities for
the Sundance range of carrier boards.
2.2 Hardware installation
1. Plug your TIMs into the SMT310Q slots. You should normally always
have a TIM in the Master TIM site (nearest the board’s end plate). Note
that many TIMs require a 3.3V supply. This is taken from the mounting
pillars, so it is important you bolt down the modules securely.
2. Power-down the PC;
3. Insert the SMT310Q into a spare PCI slot;
4. Power-up your PC. If you are using1 Windows 2000 or Windows XP, the
hardware wizard should appear (Figure 1);
5. Click “Next >”. The wizard should indicate that the SMT310Q has been
installed successfully (Figure 2);
6. Click “Finish”.
2.3 Testing the hardware
The SMT6300 comes with a utility called SmtBoardInfo.exe. You should start
this and run its confidence test, found under “Tools”.
1
Windows NT users: No hardware wizard will appear, but you should ensure there are no resource
conflicts. See Checking for hardware resource conflicts
Version 2.1 Page 8 of 55 SMT310Q User Manual
Figure 1 - Hardware wizard
Figure 2 - Hardware wizard detected the Sundance hardware
Version 2.1 Page 9 of 55 SMT310Q User Manual
3. Hardware Overview
Buffered External
JTAG connector
JTAG In, Internal
JTAG Out, Internal
e
g
d
i
r
B
I
C
P
3
V
32-bit
GLOBAL BUS
SRAM
HOST
comport
Connection
control
HOST
SDB
16-bit
JTAG
TIM 1 TIM 2 TIM 3 TIM 4
8-bit
Buffered
Comport
6 ports
COMPORT CONNECTION MATRIX
8-bit 8-bit 8-bit 8-bit
CBuf FMS FMS FMS
6 ports
7
6 ports
Figure 3 - SMT310Q Block Diagram
6 ports
3.1 Local Bus
The SMT310Q uses a Local Bus
resources. The bus has a 33MHz clock that is available on the CLKIN pin of the
Master TIM site. The TIM in this site should be set to select the local bus clock
in preference to its own oscillator to allow it to synchronise accesses across the
PCI Bridge. Details of this can usually be found in the TIM documentation under
“Global Bus Control Register”.
2
The Local Bus is not shown explicitly in the SMT310Q block diagram.
2
to control transfers amongst the various
Version 2.1 Page 10 of 55 SMT310Q User Manual
3.2 V363EPC PCI Bridge Chip
The PCI Bridge connects the host PCI bus to various devices on the local bus:
• Quick Logic EPC363 bridge chip. This has a 32-bit, 33MHz PCI
interface that supports I2C control, mailbox register access, and direct
memory reads and writes;
• Input and output FIFO. This is capable of transferring 256 32-bit words
of data to and from the DSP at 33MHz, bursting at a maximum local bus
transfer rate of 132MB/s;
• Address apertures. These provide access to the V363EPC bridge chip
configuration registers or bridging functions. The apertures respond to
addresses on both the PCI and Local buses. The following apertures are
available on the SMT310Q:
o Four data transfer apertures to transfer data across the bridge.
Two apertures are for PCI to local transfers (BAR1 and BAR2)
and two are for local to PCI transfers (Local-to-PCI Aperture 0 and
Local-to-PCI Aperture 1).
o Two apertures to access the bridge chip’s internal registers: one
aperture for Local Bus (PCI Bridge Register) accesses and one for
PCI bus (BAR0) accesses.
3.3 JTAG controller
The JTAG controller is based on the TI 8990 device; Code Composer Studio
drivers are available from Sundance, Part Number SMT6012. The presence of
a TIM in a module site causes its SENSE pin to switch the module into the
JTAG chain.
3.4 Shared SRAM
The Master TIM can access the SRAM over the Local Bus at transfer rates up
to 100MB/s. The number of wait-states required by the Master TIM varies
depending on the speed of the module. Maximum access rates use a 20ns
strobe cycle.
3.5 Control EPLD
The EPLD acts as an on-board arbitration unit that controls which device has
access to the Local Bus resources.
Version 2.1 Page 11 of 55 SMT310Q User Manual
3.6 Onboard resources
3.6.1 SDB
The on-board SDB connector is accessible via the Host PCI interface. It can
be configured with a jumper (J18) to be either an input port or an output port.
It is not intended as a high-speed link as it only has a single 16-bit data
register. You can join this connector with an SDB cable to one of the SDB
connectors on any TIM plugged into the board.
3.6.2 Host comport link
The normal means of communication between the host PC and the Master
TIM on an SMT310Q is through the host comport. A programmable switch
selects how this comport is connected.
Version 2.1 Page 12 of 55 SMT310Q User Manual
4. Comports
The SMT310Q gives access to all six comports on each of the four TIM sites3. All of
these comports can be presented at an FMS connector on the rear of the carrier
card. The connectors are marked TxCy, where “x” indicates the TIM site (1–4) and
“y” the comport number (0–5). You can connect pairs of comports by plugging cables
into these FMS connectors. Details of the connections can be found in FMS Cabling.
As an alternative to cables you can use on-board connections that allow for a subset
of the possible topologies. These on-board connections are selected by means of
Quick Switches, programmed from the Host. Figure 4 shows the possible
connections. When the SMT310Q comes out of reset, all the quick switches will be in
the 0 state.
There is a connection from the PCI interface to T1C3. This is enabled by default and
is intended for booting the system. The connection can be changed with the quick
switch controlled by bit D15 in the COM-SWITCH register. The two settings are:
0. Connect the Host Link to T1C3, and connect the C_BUF FMS connector to the
external buffered comport. This allows any of the remaining comports on sites
1—4 to be connected to the external buffered comport with an FMS cable.
In this state, the FMS connector for T1C3 must not be used.
1. Connect the Host Link to the external buffered comport and connect T1C3 to
the C_BUF FMS connector.
4.1 C_BUF
Bit D15 in the COM-SWITCH register determines the connection of the C_BUF
FMS connector (J15):
D15=0 C_BUF FMS is connected to the buffered comport. With jumper J7
fitted, C_BUF FMS will reset as an input. With J7 removed, C_BUF
FMS will reset as an output. See Figure 17.
D15=1 C_BUF FMS is connected to T1C3; this resets to an input.
D15 J7 fitted J7 removed
0 Connect C_BUF to an output comport. Connect C_BUF to an input comport.
1 Connect C_BUF to an output comport.
Not to be used
3
Some TIMs do not implement all six possible comports.
Version 2.1 Page 13 of 55 SMT310Q User Manual
A
A
A
r
BC
1
4
1
4
1
4
2
Site 4
5
2
Site 3
5
2
Site 2
5
3
0
3
0
3
0
Host Link
Ex t e r n a l
1
4
Site 1
2
5
3
0
Bu f f e r e d
Comport
- FMS Connecto
- Quic k Switc h
BC
BC
Figure 4: Comport Switching Matrix
Version 2.1 Page 14 of 55 SMT310Q User Manual
The Quick Switches are controlled by the COM-SWITCH register (BAR1, offset
2416). The Quick Switch controlled by bit D15 of the COM-SWITCH register has
the following effect:
T1C3
Host Link C BUF
Quick Switch off (0)
Jumper J7 fitted
External
Buffered
Comport
T1C3
T1C3
Host Link C BUF
Quick Switch off (0)
Jumper J7 removed
External
Buffered
Comport
External
Buffered
Comport
Host Link C BUF
Quick Switch on (1)
The switches controlled by all other bits of the COM-SWITCH register have the
following effect:
FMS A FMS B
CP A CP B
Quick Switch off (0) Quick Switch on (1)
CP A CP B
FMS A FMS B
Figure 5: Operation of quick switches
Version 2.1 Page 15 of 55 SMT310Q User Manual
D15 D14 D13 D12
PCI-External
T3C3-T4C0 T3C2-T4C5 T3C1-T4C4
T1C3—C_BUF
D11 D10 D9 D8
T2C3-T3C0 T2C2-T3C5 T2C1-T3C4 T1C3-T2C0
D7 D6 D5 D4
T1C2-T2C5 T1C1-T2C4 C-T1C0 B-T1C5
D3 D2 D1 D0
A-T1C4 T4C3-C T4C2-B T4C1-A
Table 1: COM-SWITCH Register
Bit Clear (0) Set (1) Bit Clear (0) Set (1)
D0 T4C1—FMS
D1 T4C2—FMS
T4C1—T1C4
D8
(Requires D3 set)
T4C2—T1C5
D9
(Requires D4 set)
T1C3—FMS
T1C3—T2C0
T2C0—FMS
T2C1—FMS
T2C1—T3C4
T3C4—FMS
D2 T4C3—FMS
D3 T1C4—FMS
D4 T1C5—FMS
D5 T1C0—FMS
T1C1—FMS
D6
T2C4—FMS
T1C2—FMS
D7
T2C5—FMS
T4C3—T1C0
D10
(Requires D5 set)
T1C4—T4C1
D11
(Requires D0 set)
T1C5—T4C2
D12
(Requires D1 set)
T1C0—T4C3
D13
(Requires D2 set)
T2C2—FMS
T2C2—T3C5
T3C5—FMS
T2C3—FMS
T2C3—T3C0
T3C0—FMS
T3C1—FMS
T3C1—T4C4
T4C4—FMS
T3C2—FMS
T3C2—T4C5
T4C5—FMS
T1C1—T2C4 D14 T3C3—FMS T3C3—T4C0
T1C2—T2C5 D15
C_BUF—External
Buffered Comport
PCI—T1C3
PCI— External
Buffered Comport
T1C3—C_BUF
Version 2.1 Page 16 of 55 SMT310Q User Manual
4.2 Buffered External Comport
The buffer consists of an FCT245AT type device with 64mA pull-down ability. All
signals are pulled up to +3.3 volts with 100-ohm resistors and the active devices
are mounted as closely as possible to the connector they serve. The back panel
connector is a 26 pin 3M type (3M part number 10226-5212JL).
As well as ground signals and the 12 C4x comport signals, there are 6 additional
signals. These signals are NOT essential for communications:
Name Description
I/O_OUT Output high when port is outputting, output low when port is receiving.
I/O_IN Input which prevents bus contention if connected to I/O_OUT
/RST_OUT Active low open collector copy of the board reset drive.
/RST_IN Active low board reset input, pulled up to 3.3V by 100 ohms.
VCC 1 AMP +5 Volt supply, with resetable 1 Amp fuse, to power a remote buffer, if
required.
SHIELD Overall cable shield, connected to plug shells and chassis.
Table 2: Buffered Comport Additional Signals
You can synchronise resetting a number of boards by chaining them together
with /RST_OUT of one driving /RST_IN of the next.
The SMT502-Buffer is the recommended cable assembly for the buffered
comport and can be purchased separately.
4.3 Comport to PCI Interface
The comport interface is memory-mapped to the PCI bridge as illustrated in
Table 8. The comport uses the control and data registers to detect the state of
the input and output FIFOs. The following section describes the bit definitions
for these registers.
4.3.1 Comport Registers (BAR1, Offset 1016)
The host can be connected to TIM site 1 using comport 3 (T1C3). This port is
bi-directional and will automatically switch direction to meet a request from
either the host or the DSP. Both input and output registers are 32 bits wide.
Data can only be written to COMPORT_OUT when STATUS [OBF] is 0. When
a word is received from the DSP, it is stored in COMPORT_IN and STATUS
[IBF] is set to 1. Reading COMPORT_IN will clear STATUS [IBF] and allow
another word to be received from the DSP.
Version 2.1 Page 17 of 55 SMT310Q User Manual
4.3.2 Control Register (BAR1, Offset 1416, WRITE-ONLY)
The CONTROL register contains various control flags:
7-4 3 2 1 0
IIOF2 IIFO1 IIOF0 RESET
RESET Write a 1 to this bit to assert the reset signal to all the TIM modules on
the SMT310Q.
IIOF0
IIOF1
IIOF2
These bits connect to the corresponding pins on the TIM in module site
1. Writing 0 causes the corresponding IIOF line to go low.
Table 3: Control Register
Note. On PCI system reset, RESET is asserted to all TIM sites.
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