SMT310
User Manual V1.6
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Page 2 of 50 SMT310 User Manual V1.6
Revision History
Date Comments Engineer Version
11/04/00 Initial SMT310 Draft AJP 0.5
21/08/00 ComPort + JTAG sections TJW 0.6
02/10/00 SDB Interface AJP 0.7
30/10/00 JTAG Pin information AJP 0.8
6/11/00 Amendments, addition of software section TJW 0.9
2/2/2001 Syntax updates AJP 1.0
16/01/02 Re-edit SP 1.1
20/02/02 SP 1.2
06/03/02 ComPort Mirrors SP 1.3
29/05/02 Installation Procedure SP 1.4
22/01/04 Update for V5 board and editing SP 1.5
15/03/06 Firmware v4.8 new ComPort features, updated
ComPort configuration register & Quick Switch
behaviour, updated Fig.1: ComPort connection
diagram.
JJW 1.6
Page 3 of 50 SMT310 User Manual V1.6
Table of Contents
1 Introduction ..................................................................................................................................... 8
2 Functional Description .................................................................................................................... 9
3 Setting Up the SMT310................................................................................................................. 10
4 Memory Map................................................................................................................................. 11
4.1 PCI Bridge Chip Internal Register (BAR0)........................................................................... 11
4.2 I/O Space Register Assignments (BAR1) ............................................................................ 11
4.3 Memory Space Assignments(BAR2).................................................................................... 12
5 DSP Resource Memory Map........................................................................................................13
6 Shared Memory Resource............................................................................................................ 14
7 Sundance Digital Bus (SDB)......................................................................................................... 15
8 ComPorts...................................................................................................................................... 16
8.1 Buffered ComPort................................................................................................................. 17
9 ComPort to PCI Interface....................................................................................................... .......19
9.1 ComPort Registers (Offset 0x10, BAR1).............................................................................. 19
9.2 Control Register (Offset 0x14, BAR1).................................................................................. 19
9.3 Status Register (Offset 0x14, BAR1 , Read-Only)............................................................... 20
9.4 Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 21
10 JTAG Controller ............................................................................................................................ 23
11 Using the SMT310 External/Internal JTAG with TI Tools............................................................. 24
12 Firmware Upgrades ...................................................................................................................... 25
13 Global/Local Bus Transfers, DSP <-> PCI................................................................................... 27
13.1 Mailbox Accesses................................................................................................................. 27
13.1.1 Doorbell Interrupts....................................................................................................... 28
13.2 DSP Interrupt Control...........................................................................................................28
13.3 DSP To Local Aperture 0 control and Accessing................................................................. 29
13.3.1 Global bus access protocol ......................................................................................... 31
14 Interrupts....................................................................................................................................... 34
14.1 SMT310-To-PCI Interrupts................................................................................................... 34
14.2 PCI-To-SMT310 Interrupts................................................................................................... 35
14.3 Interrupt Registers................................................................................................................ 35
14.3.1 PCI Interrupt Configuration Register(Offset 0x4C, BAR0) .......................................... 35
14.3.2 PCI Interrupt Status Register(Offset 0x48, BAR0)...................................................... 37
14.3.3 Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 38
14.3.4 Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 39
14.3.5 PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read
0xD2, BAR0)................................................................................................................................. 39
Page 4 of 50 SMT310 User Manual V1.6
14.3.6 Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0
Read 0xD6, BAR0) ....................................................................................................................... 40
14.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA,
BAR0) 41
14.3.8 INTREG Register(Offset 0x40, BAR1)........................................................................ 41
14.4 Example ............................................................................................................................... 42
15 Performance Figures .................................................................................................................... 44
16 Mechanical Dimensions................................................................................................................ 45
17 Power consumption ...................................................................................................................... 45
18 Cables and Connectors ................................................................................................................ 46
18.1 SDB...................................................................................................................................... 46
18.1.1 SDB Connector............................................................................................................ 46
18.2 ComPorts ............................................................................................................................. 46
18.3 Buffered ComPort Cabling ................................................................................................... 46
18.4 JTAG cabling................................................................................................................... .....48
19 Where’s that Jumper?...................................................................................................................50
Page 5 of 50 SMT310 User Manual V1.6
Table of Tables
Table 1 : Table of Abbreviations..................................................................................7
Table 2 : I/O address space map...............................................................................11
Table 3 : Memory space map....................................................................................12
Table 4 : Memory space map....................................................................................13
Table 5 : SDB Control Register .................................................................................15
Table 6 : ComPort configuration register...................................................................17
Table 7 : Comport selection.......................................................................................17
Table 8 : Control Register..........................................................................................19
Table 9 : Status Register...........................................................................................21
Table 10 : Interrupt Control Register..........................................................................22
Table 11 : JTAG Header pin function.........................................................................26
Table 12 : PCI Interrupt Configuration Register.........................................................37
Table 13 : PCI Interrupt Status Register....................................................................38
Table 14 : Local Bus Interrupt Mask Register...........................................................39
Table 15 : Local Bus Interrupt Status Register..........................................................39
Table 16 : PCI Mailbox WRITE/READ Interrupt Control Register..............................40
Table 17 : Local Bus Mailbox WRITE/READ Interrupt Control Register....................40
Table 18 : Mailbox Write/Read Interrupt Status Register...........................................41
Table 19 : INTREG Register......................................................................................42
Table 20: SDB Pin-out...............................................................................................46
Table 21 : Buffered ComPort connector pin out.........................................................47
Table 22 : Buffered JTAG connector pin functionality as JTAG master.....................49
Table 23 : Internal JTAG out (XDS-510) pin descriptions..........................................49
Page 6 of 50 SMT310 User Manual V1.6
Table of Figures
Figure 1: ComPort connection diagram.....................................................................16
Figure 2 : TBC Data Routing .....................................................................................23
Figure 3 : JTAG header pin numbers.........................................................................26
Figure 4 : Local Bus to DSP Connectivity..................................................................27
Figure 5 : DSP Transfer via the Local Aperture 0......................................................30
Figure 6 : Timing diagram for DSP local bus access.................................................32
Figure 7 : SMT310 to PCI Interrupts..........................................................................34
Figure 8 : PCI to SMT310 Interrupts..........................................................................35
Figure 9 : Jumper Finder Diagram.............................................................................50
Page 7 of 50 SMT310 User Manual V1.6
Table Of Abbreviations
BAR Base Address Region
DMA Direct Memory Access
EPLD Electrically Programmable Logic Device
PCI Peripheral Component Interconnect
SDB Sundance Digital Bus
SRAM Static Random Access Memory
TBC Test Bus Controller
TIM Texas Instruments Module
Table 1 : Table of Abbreviations
1 Introduction
The SMT310 is a single site module carrier board that provides access to a TIM
module over the PCI bus.
An on-board JTAG controller allows systems to be debugged using Code Composer
Studio. This JTAG controller also has buffered outputs that can be accessed using
connectors on the carrier’s back panel. This allows off-board devices to be connected
into the JTAG chain.
A single buffered ComPort with conflict protection is also available on the chassis
back panel. This will have the versatility to access any of four ComPorts on the TIM.
The main connection to the PCI bus is via the module Global Bus. A single ComPort
is also be mapped to the PCI bus providing support for application boot and data
transfer.
A 1 MB of SRAM is mapped on to the Global Bus and can be accessed by the TIM as
a global resource or by the PCI Bridge.
The board requires a 3.3 volt supply that is taken from the PCI edge connector and is
made available at the fixing pillars for the module.
An ‘on-board’ SDB interface to the PCI Bridge allows the card to be interfaced to SDB
standard modules.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
2 Functional Description
The PCI interface connects to a Quick Logic EPC363 Bridge device. It has a 32-bit
33MHz PCI interface that supports I2C control, mailbox register access, and direct
memory reads and writes. The PCI bus is translated to a Local PCI bus, which is
connected to the following devices:
• Shared SRAM 1MB
• Control EPLD that manages ComPort access and the SDB interface
• JTAG controller
• Module Global Bus
• PCI Bridge device
An on-board arbitration unit controls which device, Master Module or PCI Bridge, has
access to this local PCI bus resource.
The local PCI bus has a 33MHz clock to control transfers between the various
resources. This is available on the CLKIN pin on the Master site and should be
selected in preference to the on-board oscillator to allow the DSP to synchronise its
accesses to and from the PCI Bridge registers. The PCI Bridge has an input and
output FIFO capable of transferring 256 32-bit words of data to and from the DSP at
33MHz, thus bursting a maximum local bus transfer rate of 132MB/s.
The Master Module can access the SRAM over the PCI local bus at transfer rates up
to 100MB/s. The number of wait states required by the Master Module will vary
depending on the speed of the module. Maximum access rates use a 20ns strobe
cycle.
The JTAG controller is based on the TI 8990 device, and drivers can be supplied for
Code Composer Studio (Part Number
SMT6012).
The on-board SDB connector can be configured with a jumper to be either an input
port or an output port, accessible via the Host PCI interface. It is not intended as a
high-speed link as it has only a single 16-bit FIFO.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
3 Setting Up the SMT310
The SMT310 should be set up in the following way.
• Turn the PC off and insert the Card into a spare PCI slot.
• Switch on PC and wait for the OS to boot up.
• Windows 95/98/NT/2000 will detect a new hardware.
• Windows should automatically find the drivers from the CD, if not browse to the
CD or if you downloaded from the ftp site to the folder where you unzipped the
SMT6300 software.
• When you run it, 3L application software will be able to detect the SMT310
provided the SET TISLINK variable is set to SMT320.
• You can run the SMTBoardInfo application to detect the number of SMT310s in
your system and report their slot positions and I/O addresses. This information is
required when setting up code composer for the board. SMTBoardInfo is installed
as part of the SMT6300 package.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
4 Memory Map
All address information is given in bytes :
4.1 PCI Bridge Chip Internal Register (BAR0)
Please see V363EPC Local Bus PCI Bridge User Manual V1.04
(http://www.quicklogic.com/home.asp?PageID=223&sMenuID=114#Docs) for details
of internal registers.
Note: Where required, registers from the V3 datasheet have been included.
4.2 I/O Space Register Assignments (BAR1)
In target mode, the SMT310 is accessed by a host device across the PCI bus. This
allows access to the target mode registers. The operating system or BIOS will
normally allocate a base address for the target mode registers of each SMT310.
Access to each register within the SMT310 is then specified by this base address and
the offset shown in the table below.
The I/O address space is decoded as shown in the table below.
Offset Register(Write) Register(Read) Width
0x0 - -
0x4 - -
0x8 - -
0x0C - -
0x10 COMPORT_OUT COMPORT_IN 32
0x14 CONTROL STATUS 32
0x18 INT_CONTROL 32
0x1C - -
0x20 to 0x3F COMPORT Configuration COMPORT Configuration
0x24 COM_SWITCH COM_SWITCH 16
0x40 INTREG INTREG 16
0x80 to 0xAF TBC Write TBC Read 16
Table 2 : I/O address space map
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
4.3 Memory Space Assignments(BAR2)
Address Description Notes
0x0000 0000 – 0x000F FFFF Shared Memory Bank 1MB SRAM
0x00200090
ComPort Data
Mirror
Mirror of COMPORT_OUT /
COMPORT_IN in
I/O Space
Register Assignments
(BAR1)
See Note 2
0x00200094
ComPort Status
Mirror
Mirror of Control / Status in I/O
Space Register
Assignments (BAR1)
See Note 2
0x00200098
ComPort Int_Control
Mirror
Mirror of Int_Control in I/O
Space Register
Assignments (BAR1)
See Note 2
0x0020 0000-0x0020 007F Global Bus See Note 1
0x0020 0240 – 0x0020 025F SDB Data Register Input/Output 16 bit SDB Interface
0x0020 0260 – 0x0020 027F SDB Control Register SDB Control/Status
Table 3 : Memory space map
Note 1: In order for the TIM to respond to accesses for this area address line
GADD30 and GADD19 of the TIM site connector must be decoded as high and
GADD7 and GADD5 must be decoded as low.
Note 2: These mirrors of Addresses in the I/O Space (BAR1) allow increased transfer
speeds across the host ComPort link (in excess of 10X increase).
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
5 DSP Resource Memory Map
The Master module on the SMT310 can access the various resources available,
including the Shared SRAM and the PCI Bridge. Access to the PCI Bridge allows the
DMA engine in the PCI Bridge to be initiated by the DSP, mailbox registers can also
be manipulated. The table below illustrates the resources and their corresponding
address region when accessed by the Master module.
C60 Address Access Description Notes
0xD000 0000 – 0xD00F FFFF Shared Memory Bank 1Mbyte SRAM
0x1C00 0000 – 0x1C00 00FF PCI Bridge Registers PCI Bridge Internal resisters
0x1800 0000 – 0x183F FFFF Local-to-PCI Aperture 0 PCI Bridge Aperture 0 Space
Table 4 : Memory space map
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
6 Shared Memory Resource
The shared memory on the SMT310 is 1 MB of SRAM, which can be accessed by the
PCI host and the TIM module. This allows applications to transfer data between the
host PC and the DSP at data rates approaching 100MB/s. The address of the shared
memory is shown in the memory map.
The PCI Bridge DMA processor sees the shared memory at a different address from
that used for normal accesses. For normal memory access the memory base address
register offset is 0x0000 0000. For DMA access address line A28 (On hardware
interface) must be high, therefore DMA memory access starts at 0x4000 0000 (Not
0x1000 0000 as addressing is in bytes).
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
7 Sundance Digital Bus (SDB)
A growing number of Sundance’s Modules have an on-board SDB. The SDB is
described on the Sundance web site at www.sundance.com/html/pdf_info.htm .
The following register controls the carrier’s SDB.
D7 D6 D5 D4 D3 D2 D1 D0
X X OFFF IPFF RW RW RW RXNTX
Table 5 : SDB Control Register
The SDB control and status register is located at BAR2 offset 0x00200260. The bit
definitions are shown below:
RXNTX
SDB Direction. The SDB direction is set using Jumper J8 (
Figure 9 : Jumper Finder Diagram) on the SMT310, When the jumper is
out the SDB is set for receive mode; when the jumper is in the SDB is set
for transmit mode. This bit indicates the direction set: 0=Receive,
1=Transmit.
RW
IPFF
General scratch bits
Input FIFO full: When set, a 16-bit value has been latched in the data
register ready for reading. This bit is automatically cleared on a read from
the data register.
OPFF
Output FIFO full: This bit is set when a 16-bit value is written to the FIFO
and is automatically cleared when it has been sent out of the SDB.
The SDB data register is located at BAR2 offset 0x00200240. You can write 16-bit
values to this location to transfer them over the SDB interface as long as the OPFF
flag in the status register is clear and J8 jumper is in.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
8 ComPorts
The SMT310 gives access to all six TIM site ComPorts. One of four ComPorts can be
connected through a high drive buffer to a connector on the rear panel of the card.
This connection and switching is achieved using Quick Switch B, alleviating the need
for patch cables.
Two of the TIM site ComPorts are connected straight to 14-way surface-mount FMS
connectors for connection to other ComPort compatible devices within the same
chassis.
There is a connection from the PCI interface to ComPort 3 for booting the TIM. This
connection can be severed with Quick Switch C (clear CENc ) allowing ComPort 3 to
be used for other purposes. This also allows the PCI interface ComPort to be used
independently of the TIM as it is also wired to a 14-way surface-mount FMS
connector.
Buffered
Comm Port
Quick
Switch B
Buffer
J4
J1
FMS FMS
FMS FMS
J2 J3
140235
Comm-ports
Module Site
Global Bus
PCI Bridge
Comm-
port
CPLD
Quick
Switch C
PCI Connector
Figure 1: ComPort connection diagram
The configuration of the ComPorts on the SMT310 can be set using the ComPort
configuration register (I/O Offset 0x20).
Default state = 0x2C (Assuming no FMS cables connected)
D7 D6 D5 D4 D3 D2 D1 D0
X X CENc CENb SELC
Read/Write Read/Write
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
1
Read-only Read-only
SELB
2
SEL1 SEL0
Read/Write Read/Write
Page 17 of 50 SMT310 User Manual V1.6
Table 6 : ComPort configuration register
The table below illustrates the different setting of the register.
CENc CENb SEL1 SEL0 Function
1 X X X Connects DSP ComPort 3 to PCI Host
0 X X X Disconnects DSP ComPort 3 to PCI Host
X 0 X X Disables all DSP connections to Buffered ComPort
X 1 0 0 Connect DSP ComPort 0 to Buffered ComPort
X 1 0 1 Connect DSP ComPort 2 to Buffered ComPort
X 1 1 0 Connect DSP ComPort 3 to Buffered ComPort
X 1 1 1 Connect DSP ComPort 5 to Buffered ComPort
Table 7 : Comport selection
1
SELC is a read-only bit that indicates, when 0, the detection of an FMS cable at J2. If SELC is
0 then CENc is overridden, since PCI Host is now connected to the external FMS connector J2.
2
SELB is a read-only bit that indicates, when 0, the detection of an FMS cable at J1. If SELB is
0 then CENb is overridden, since buffered ComPort is now connected to external FMS
connector J1.
1
2
2
2 3
2
The state of SEL1 also determines the direction (at reset) of the buffered ComPort,
because ComPorts 0 and 2 are defined (at reset) as outputs, and likewise 3 and 5 (at
reset) as inputs.
Important note for firmware v4.8 onwards:
An additional feature is supported from firmware v4.8, March 2007: Fitting jumper
JP9 links TIM site ComPort 3 directly to J2.
Specifically, JP9 forces Quick Switch C on and at the same time disables the PCI
Host ComPort CPLD. This connects TIM site ComPort 3 directly to the FMS
connector J2, and disconnects any link to the PCI Host. This setting overrides the
usual functions of CENc, and SELC but has no effect on CENb or CELB.
3
Care must be taken when JP9 is fitted, not to connect ComPort3 to the
Buffered ComPort also, or contention will occur.
8.1 Buffered ComPort
From the TIM site, 4 ComPorts are taken to a back panel mounted connector via
quick switches. All signals are pulled up to +3.3 volts with 330 ohm resistors. The
active devices are mounted as close as possible to the connector they serve.
The back panel mounted connector is a 26 pin 3M type, (3M part number 102265212JL). The connector pin-out is given in the following table, with pair numbers for
13 off twisted pair cable (3M part number KUCKMPVVSB28-13PAIR).
The buffer circuit for the connector is designed such that the reset direction is defined
by the TIM ComPort number to which it is connected. The quick switch arrangement
Page 18 of 50 SMT310 User Manual V1.6
allows cable less connection between the TIM site and the buffer. There is also a 14way surface-mount FMS connector allowing the buffer to be connected to some
external source of data. When this connector is used, all other quick switch TIM site
connections are removed.
As well as the 12 C4x ComPort signals and signal grounds, there are 6 additional
signals. Note that these signals are NOT essential for communications:
Name Description
I/O_OUT Output high when port is outputting data, output low when
port is receiving data.
I/O_IN Input which prevents bus contention if connected to I/O_OUT
/RST_OUT Active low open collector copy of the board reset drive.
/RST_IN Active low board reset input, pulled up to 3.3V by 100 ohms.
VCC 1 AMP +5 Volt supply, with resettable 1 Amp fuse, to power a
remote buffer, if required.
SHIELD Overall cable shield, connected to plug shells and chassis.
The /RST_OUT is intended to allow synchronised reset of a number of boards by
driving the /RST_IN input.
The ComPort configuration register controls the way in which the quick switches
route the TIM site ComPorts to the buffer (see table 4). There is also an overall
enable bit CENb that must be set to enable the quick switches.
9 ComPort to PCI Interface
The ComPort interface is memory mapped to the PCI Bridge as illustrated in table 1 :
I/O address space map. The ComPort uses the Control and Data registers to detect
the state of the input and output FIFO. The following section describes the bit
definitions for these registers.
9.1 ComPort Registers (Offset 0x10, BAR1)
The host is connected to the first TIM site using ComPort 3. This port is bi-directional
and will automatically switch direction to meet a request from either the host or the
DSP. Both input and output registers are 32 bits wide. Data can only be written to
COMPORT_OUT when STATUS[OBF] is 0. Data received from the DSP is stored in
COMPORT_IN and STATUS[IBF] is set to 1. Reading COMPORT_IN will clear
STATUS[IBF] and allow another word to be received from the DSP.
9.2 Control Register (Offset 0x14, BAR1)
The CONTROL register can only be written. It contains flags, which control the boot
modes of the first TIM site.
7-5 4 3 2 1 0
notNMI IIOF2 IIOF1 IIOF0 RESET
RESET Write a 1 to this bit to assert the reset signal to the TIM
module on the SMT310.
IIOF0
IIOF1
These bits connect to the corresponding pins on the TIM site
1. Writing 0 causes the corresponding IIOF line to go low.
IIOF2
NotNMI A 0 written to this bit will assert the active low NMI to the
TIM.
Table 8 : Control Register
Note. On PCI system reset, RESET is asserted to the TIM site.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
9.3 Status Register (Offset 0x14, BAR1 , Read-Only)
31:22 21 20 19 18 17 16 15:12 11 10 9 8
CONFIG_L TBC
RDY
0 MASTER IBF OBF
IM2 IM1 IM0 INTD
7 6 5 4 3 2 1 0
C40 INT TBC INT IBF INT OBE INT C40 IE TBC IE IBF IE OBE IE
OBE IE Set if ComPort output buffer empty interrupts enabled.
IBF IE Set if ComPort input buffer full interrupts enabled
TBC IE Set if JTAG interrupts enabled
C40 IE Set if interrupt from TIM DSP enabled
OBE INT Set if the ComPort output buffer becomes empty. Cleared by writing a
1 to the corresponding bit in the interrupt control register.
IBF INT Set if the ComPort input buffer receives a word. Cleared by writing a
1to the corresponding bit in the interrupt control register
TBC INT Set when the TBC asserts its interrupt. Cleared by removing the
source of the interrupt in the TBC.
C40 INT Set when the TIM DSP sets its host interrupt bit. Cleared by writing a
1 to the corresponding bit in the interrupt control register.
INTD The logical OR of bits 7—4 in this register gated with each one’s
enable bit.
OBF Set when a word is written to the ComPort output register. Cleared
when the word has been transmitted to the DSP.
IM0 Interrupt mask 0. Returns Interrupt Control Register Bit 8.
IM1 Interrupt mask 1. Returns Interrupt Control Register Bit 9.
IM2 Interrupt mask 2. Returns Interrupt Control Register Bit 10.
IBF Set when a word is in the ComPort input register.
MASTER Set when the SMT310 Bridge owns the ComPort interface token.
TBC RDY Reflects the current state of the TBC RD Y pin. This bit is active high
and therefore and inversion of the TBC pin.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Page 21 of 50 SMT310 User Manual V1.6
CONFIG_L Reflects the state of the TIMs’ CONFIG signal. Active low.
Table 9 : Status Register
INTD is the input interrupt into the PCI Bridge from the SMT310, this can be routed to
either INTA, INTB, or INTC using the PCI Interrupt Configuration Register (offset
0x4C, BAR0)
9.4 Interrupt Control Register (Offset 0x18, BAR1)
This write-only register controls the generation of interrupts on the PCI bus. Each
interrupt source has an associated enable and clear flag. This register can be written
with the contents of bits 7:0 of the Status Register.
10 9
DSP-PC IIOF2 En DSP-PC IIOF1 En
8 7 6 5 4 3 2 1 0
DSP-PC
IIOF0 En
CLEAR
C40 INT
0 CLEAR
IBF INT
CLEAR OBE
INT
C40 IE TBC IE IBF IE OBE IE
DSP-PC IIOF2 En Enables DSP-PC interrupts on IIOF2
DSP-PC IIOF1 En Enables DSP-PC interrupts on IIOF1
DSP-PC IIOF0 En Enables DSP-PC interrupts on IIOF0
IBF IE ComPort Input Buffer Full Interrupt Enable. Allows an
interrupt to be generated when the host ComPort input
register is loaded with data from the C40.
OBE IE ComPort Output Buffer Empty Interrupt. Allows an interrupt to
be generated when the host ComPort register has transmitted
its contents.
TBC IE Test Bus Controller Interrupt Enable. Interrupts from the
Texas JTAG controller are enabled when set.
C40 IE C40 Interrupt Enable. Allows a programmed interrupt to be
generated by the C40 when set.
CLEAR OBE INT Write a one to this bit to clear the interrupt resulting from a
ComPort output event.
CLEAR IBF INT Write a one to this bit to clear the interrupt event resulting
from ComPort input.
CLEAR C40 INT Write a one to this bit to clear down the C40 INT event.
Page 22 of 50 SMT310 User Manual V1.6
Table 10 : Interrupt Control Register
The JTAG controller which generates TBC INT must be cleared of all interrupt
sources in order to clear the interrupt.
(
)
10 JTAG Controller
The SMT310 has an on board Test Bus Controller (TBC). The TBC is controlled from
the PCI bus giving access to the on site TIM and/or any number of external TIMs.
The TBC is a SN74ACT8990 from Texas Instruments. Please refer to the Texas
Instruments data sheet for details of this controller. The TBC is accessed in I/O space
at the Base address + 0x80.
TIM Site
Buffer
TBC
8990
PCI Bus
Out
In0
In1
Switch
External
JTAG ou t
Connector
Internal
JTAG out
XDS-510
Figure 2 : TBC Data Routing
The Test Bus Controller drives the JTAG scan chain through the TIM site on the
SMT310. If the site is not populated with a TIM then the modules SENSE signal is
used to enable a tri-state buffer connecting the TDI and TDO on the site (JTAG Data
In and Data Out) allowing TBC test data to appear at the external and internal JTAG
out connectors on the board. This switching is automatic. The External JTAG out
Connector is intended to connect to JTAG slaves external to the system chassis. The
Internal JTAG out (XDS-510) Header is for use with JTAG slaves within the system
chassis. Important Note – These connectors may
not be used simultaneously.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
11 Using the SMT310 External/Internal JTAG with TI Tools.
For details on using the SMT310 with T.I. Code Composer range, see the SMT6012
documentation.
The SMT6012 is Sundance’s driver for the T.I. Code Composer range of products
and can be purchased separately. The SMT6012 is free of charge when the SMT310
is bought with the Code Composer software from Sundance.
The Texas Instruments Evaluation Module (EVM) kits can be used as stand-alone
devices with a SMT310 as the JTAG master. When running with the EVM kits ensure
that the EVM jumper has been set up correctly. i.e. External JTAG has been selected
and the DSP boot location is valid (set for internal memory space).
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
r
12 Firmware Upgrades
Much of the SMT310’s control interface is achieved using CPLD’s. Sometime
customers require slightly different interface protocols (i.e. SDB interface), which can
be catered for by a firmware upgrade. To upgrade firmware Xilinx JTAG
programming software is required together with a lead to connect to the SMT310’s
header. The image below shows the location of pin 1 of the JTAG connector J21.
This connector is a 2x3 2mm pin header.
Pin 1 JTAG Programmer
Heade
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4
2
6
1
3
5
Figure 3 : JTAG header pin numbers
Pin Number Function
1 Vcc (5v)
2 Gnd
3 TCK
4 TDO
5 TDI
6 TMS
Table 11 : JTAG Header pin function
13 Global/Local Bus Transfers, DSP <-> PCI.
The traditional global bus interface on C6x DSP modules interfaces to the SMT310
via a local bus. This allows Global bus transfers on the DSP to be converted into
local bus accesses. This allows direct DSP accesses to the PCI Bridge chip.
The resources in the PCI Bridge chip are illustrated in the figure below.
PCI Bridge Device
MailBox
Read/Write
Interrupt Control
Local To PCI Bus
Apperture Contro l
LOCAL <-> PCI
Apperture 0
16MB Address
Space
Local Bus
Arbitration
Unit
DSP Global
Bus Access
Figure 4 : Local Bus to DSP Connectivity
13.1 Mailbox Accesses
The mailbox registers can be used if small amounts of data or commands between
the PCI bus and the DSP, via the local bus, need to be transferred. Rather than
sending ComPort data, and therefore require the DSP to be checking its ComPort for
commands, a mailbox write by the PCI bus can be initialized to generate an interrupt
on an DSP IIOF line indicating, to the DSP, that data is available. The PCI Bridge
device provides 16 8-bit mailbox registers, which may be used to transmit and
receive data between the DSP and Host.
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The mailbox registers are accessed from the DSP through the Local-to-Internal
Register (LB_IO_BASE) aperture. As illustrated in section 5, table 4 of this document
this region is accessed by the DSP via a global bus access to the PCI Bridge
Registers (Address : 0x1C00 0000).
The mailbox registers themselves are on byte boundaries with offsets 0xC0 -> 0xCF,
from the LB_IO_BASE. As DSP global bus accesses are carried out on WORD (32bit) boundaries a write access over the global bus to 0x1C00 0000 + 0xC0 will write
to the first 4 mailbox registers in the PCI Bridge device.
The mailbox registers are accessed from the PCI bus through the PCI-to-Internal
Register (PCI_IO_BASE) aperture. This is accessed via the PCI Bridge Chip Internal
Register (BAR0), byte offset 0xC0 -> 0xCF.
13.1.1 Doorbell Interrupts
Each of the 16 mailbox registers can generate four different interrupt requests called
doorbell interrupts. Each of these requests can be independently masked for each
mailbox register. The four doorbell interrupt types are:
• DSP interrupt request on read from PCI side
• DSP interrupt request on write from PCI side
• PCI interrupt request on read from DSP side
• PCI interrupt request on write from DSP side
The PCI read and DSP read interrupts are OR’d together and latched in the mailbox
read interrupt status register (MAIL_RD_STAT). Similarly, the PCI write and DSP
write interrupts are OR’d together and latched in the mailbox write interrupt status
register (MAIL_WR_STAT). All of the interrupt request outputs from the status
registers are OR’d together to form a single mailbox unit interrupt request and routed
to both the Local and PCI Interrupt Control Units.
When a block of mailbox registers are accessed simultaneously, for example when 4
mailbox registers are read as a word quantity, then each register affected will request
a separate interrupt if programmed to do so.
See section 14 for further information on Interrupts.
13.2 DSP Interrupt Control
Interrupts can be enabled from a number of different sources i.e. DSP-> Host and
Host -> DSP. See section 14 for a description of these functions.
13.3 DSP To Local Aperture 0 control and Accessing
The quickest way to transfer information from the DSP to PCI Bus or vice versa is to
use the Local-to-PCI Aperture 0 in the PCI Bridge device. A DSP unit may be
required to transfer large amounts of acquired data to the PC host for data storage or
post-processing etc. Allowing the DSP to take control of the PCI bus means that the
HOST only requires to transfer data, from an internal allocated region of memory,
after the transfer has been completed by the DSP. Alerting the Host that data has
been transferred can be accomplished in a number of ways i.e. writing to the mailbox
register, which can then generate an interrupt.
As shown in Table 4, section 5. The Local-to-PCI Aperture 0 is mapped as a region of
addressable space from 0x1800 0000 – 0x183F FFFF (words).
There are a number of registers in initialise before data can be read or written via this
address space.
• Unlock the PCI Bridge System register. This requires a write to
• Write the upper 8 bits of your destination address (in bytes) to the upper 8 bits
of the 32-bit Local Bus to PCI Map 0 register (LB_MAP0_RES, offset in bytes
0x5c ).
• Convert you lower 24-bit address to a word aligned value.
• Write/Read data from Local-to-PCI Aperture 0 .
The diagram below illustrates this procedure.
In the example below the WritetoPCIregisters(offset,data) function writes data over
the DSP’s Global bus, at a base address of 0x1800 0000 (words), the first parameter
passed to this function in the offset address in words, and the second is the data to
be written.
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Receive Target address via Com-Port
Link
i.e. 0xFE12 3000
#define LB_CFG_SYSTEM (0x78>>2) (divide by 4 to word align offset address of PCI
bridge register)
WritePCIRegisters((unsigned int)LB_CFG_SYSTEM,0xA05F); // Unlock Code
WritePCIRegisters((unsigned int)LB_CFG_SYSTEM,0x22008800); // Restore Value
Unlock the system register in PCI Bridge
Write Lower 24 bits of byte TargetAddress to the LB_MAP0_RES register
#define LB_MAP0_RES (0x5C>>2)
#define LB_MAP0_MEMORY_RW 0x00060000
#define LB_MAP0_ADDRESS_MASK 0xFF000000
WritePCIRegisters((unsigned int)LB_MAP0_RES,(unsigned int)(TargetAddress &
LB_MAP0_ADDRESS_MASK ) | LB_MAP0_MEMORY_RW);
// The LB_MAP0_MEMORY_RW must be Or’ed with the data to ensure the other register in
// the 32-bit word has its correct value.
WritePCIApperture0((ByteToWord32(((TargetAddress) & ~LB_MAP0_ADDRESS_MASK))),Length,buffer);
Where
void WritePCIApperture0(unsigned int address,unsigned lon g Length,unsigned int *buffer)
{
unsigned int Index;
Write WORD Aligned data to Local Aperture space 0.
globalbuswriteClockMB(0x18000000 + address , Length , buffer);
}
Figure 5 : DSP Transfer via the Local Aperture 0
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13.3.1 Global bus access protocol
In Figure 6, the WritePCIApperture function calls a function
C6xGlobalWriteClockMB().
This function enables the DSP’s global bus to transfer Length words from the DSP’s
internal memory map pointed to by buffer. The function puts the Global bust into burst
mode. This interface allows a synchronous stream of data to be written to the 256
WORD input FIFO of the Local To PCI aperture 0. For more information on setting
this mode from the DSP can be found in the SMT335 Users Guide. This section
concentrates on the burst mode interface and arbitration mechanism for the DSP to
PCI Bridge aperture access.
The Global bus interface of the DSP uses the following signals to interface to the
local bus of the SMT310.
DSP Signals.
AE*, DE*, CE0*
AE*/DE* are active low address/Data enable signal driven by the SMT310, when the
DSP has ownership of the Bus this signal is driven low by the SMT310 allowing the
DSP to drive the Address pins and Data pins.
CE0* is the Tri-state control for the DSP’s global bus control pins. This is permanently
tied low by the SMT310 as the control signal is always enable.
STRB1*
Data strobe signal from the DSP’s global bus. This is driven low when the DSP is
carrying out an access cycle. The DSP waits for the RDY1* to be driven low by the
SMT310 to indicate transfer has been completed. This interface is carried out in
synchronous burst mode. This requires the DSP to indicate when the burst transfer
is completed. This is accomplished by the DSP by pulling STAT0 low.
RDY1*
Active low transfer acknowledgement. This is driven by the SMT310 to indicate that
the current transfer has been completed.
STAT0..3
DSP Status line. When all of the signals are logic ‘1’ then the DSP Global bus
interface is in an idle state. When any of these signals is driven low the DSP
requesting ownership of the SMT310’s local bus. STAT0 has a special status and
indicates the last data packet transfer when driven low by the DSP.
A0..A30
DSP’s global Bus address lines
D0..D31
DSP’s global Bus data lines
IIOF0, IIOF1 & IIOF2
DSP’s Interrupt signals. These are open collector signals on the SMT310. They can
be driven by the DSP to generate an interrupt to the host, or they can be driven by
the host to interrupt the DSP.
In the timing diagram below all signals change relative to the rising LCLK signal. This
signal is the H1 clock signal of the DSP when using the DSP global bus in
synchronous mode (see SMT335 User Guide).
LCLK
STAT[1.3]
STRB1
RDY1
STA 0 T
AE E /D
A[30..0]
D[31..0]
TIMReq FIFO Full
Figure 6 : Timing diagram for DSP local bus access
* LCLK Period =30nS, frequency is 33MHz.
The DSP initiates a global bus R/W by asserting the STRB1 low and STAT[1:3}
change (see TIM Spec for details of STAT[1..3] details). Once the arbitration unit
detects this, it waits for the last cycle of the Local bus to be completed by the PCI
Bridge, before allowing the DSP to become Bus Master. Once the DSP is Master the
arbitration unit drives AE and DE low to enable the DSP’s address and data lines.
RDY1 is driven low by the arbitor to indicate to the DSP, on the next rising LCLK, that
the data packet has been transferred. If the input FIFO (256 Words Deep) becomes
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full, the arbitration logic de-asserts the RDY1 signal to indicate a hold-off state. Once
the data has been transferred from the FIFO to the PCI bus RDY1 is re-asserted to
continue the transfer. The end of the burst access is indicated by asserting STAT0
low. If RDY1 is not active then STAT0 should remain asserted until ready is asserted
and the final data transaction has been completed.
Situations can arise where a deadlock condition car arrive, i.e. the PCI bus is trying to
read from the SMT310 resources while the DSP is reading from the PCI Bus. If this
situation arises the arbitration unit gives the PCI Bridge device priority and services
the HOST PCI access before giving bus ownership back to the DSP.
When running code composer applications to debug the DSP a reduction in the
speed of the debugger will be noticed. The DSP has priority when accessing the
local bus and any other accesses will only occur under the following conditions.
• Burst access is finished
• Deadlock condition occurs which releases DSP ownership of the Bus.
For multi-threaded applications the length of the DSP burst can be lowered to allow
PCI bus R/W cycles to snatch cycles from the DSP.
14 Interrupts
14.1 SMT310-To-PCI Interrupts
CONTROL EPLD
INTERRUPT
CONTROL
REGISTER
C40 IE
IBF IE
OBE IE
INTD
PCI Bridg e
INTD
INTA
TIMIIOF0
TIM IIOF1
TIMIIOF2
INTERRUPT
CONTROL
REGISTER
DSP IIOF0
ENABLE
DSP IIOF1
ENABLE
DSP IIOF2
ENABLE
STA TUS
REGISTER
DSP INT
IBF INT
OBE INT
INTB
JT AG INT
TBC INT
TBC IE
INTC
Figure 7 : SMT310 to PCI Interrupts
Interrupts can also be caused by the SMT310 by writing or reading the mailbox
registers in the PCI Bridge.
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14.2 PCI-To-SMT310 Interrupts
CONTROL CPLD
CONTROL
REGISTER
PCI
Bridge
LINT c an
be caused
by any PCI
interrupt
e.g. Mailbox
LINT
Figure 8 : PCI to SMT310 Interrupts
LINT
IIOF0
IIOF1
IIOF2
INTREG
REGISTER
TIMIIOF0 IE
TIMIIOF1 IE
TIMIIOF2 IE
TIMIIOF0
TIMIIOF 1
TIMIIOF2
14.3 Interrupt Registers
The following register are used to control PCI-To-DSP and DSP-To-PCI interrupts:
Note that Control Register (Offset 0x14, BAR1) and Interrupt Control Register (Offset
0x18, BAR1) are also used to control interrupts.
14.3.1 PCI Interrupt Configuration Register(Offset 0x4C, BAR0)
Bits Name Description
31 MAILBOX Mailbox Interrupt Enable: Enables a PCI interrupt from the
mailbox unit
30 LOCAL Local Bus Direct Interrupt Enable: Enables direct local bus
to PCI interrupts
29 MASTER_PI PCI Master Local Interrupt Enable: (see V3 datasheet)
28 SLAVE_PI PCI Slave Local Interrupt Enable: (see V3 datasheet)
27 OUT-POST I2O Outbound Post List Not Empty: (see V3 datasheet)
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26 - Reserved
25 DMA1 DMA Channel 1 interrupt enable
24 DMA0 DMA Channel 0 interrupt enable
23-22 MODE_D INTD interrupt mode: Determines use of corresponding
interrupt pin
00 Active low level triggered input
01 High-to-low edge triggered input
10 Software cleared output. INTD pin is asserted via
an interrupt event and cleared through
PCI_INT_STAT register
11 Reserved
21-20 MODE_C INTC interrupt mode (as MODE_D)
19-18 MODE_B INTB interrupt mode (as MODE_D)
17-16 MODE_A INTA interrupt mode (as MODE_D)
15 INTD_TO_LB 1=INTD will request LICU interrupts when the input is
active
0=INTD will never request LICU interrupts
14 INTC_TO_D When set INTC will act as interrupt request for INTD
output
13 INTB_TO_D When set INTB will act as interrupt request for INTD
output
12 INTA_TO_D When set INTA will act as interrupt request for INTD
output
11 INTD_TO_C When set INTD will act as interrupt request for INTC
output
10 INTC_TO_LB 1=INTC will request LICU interrupts when the input is
active
0=INTC will never request LICU interrupts
9 INTB_TO_C When set INTB will act as interrupt request for INTC
output
8 INTA_TO_C When set INTA will act as interrupt request for INTC
output
7 INTD_TO_B When set INTD will act as interrupt request for INTB
output
6 INTC_TO_B When set INTC will act as interrupt request for INTB
output
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5 INTB_TO_LB 1=INTB will request LICU interrupts when the input is
active
0=INTB will never request LICU interrupts
4 INTA_TO_B When set INTA will act as interrupt request for INTB
output
3 INTD_TO_A When set INTD will act as interrupt request for INTA
output
2 INTC_TO_A When set INTC will act as interrupt request for INTA
output
1 INTB_TO_A When set INTB will act as interrupt request for INTA
output
0 INTA_TO_LB 1=INTA will request LICU interrupts when the input is
active
0=INTA will never request LICU interrupts
Table 12 : PCI Interrupt Configuration Register
14.3.2 PCI Interrupt Status Register(Offset 0x48, BAR0)
Bits Name Description
31 MAILBOX Mailbox Interrupt:
1=Mailbox interrupt request active
0=No mailbox interrupts pending
Cleared by clearing MAIL_RD_STAT and
MAIL_WR_STAT
30 LOCAL Local bus direct interrupt:
1=Local bus master requests a PCI interrupt
0=No operation
This bit is set by writing 1 and cleared by writing 0
29-28 - Reserved
27 OUT_POST I2O outbound post list not empty: (see V3 datasheet)
26 - Reserved
25 DMA1 DMA channel 1 interrupt
24 DMA0 DMA channel 0 interrupt
23-15 - Reserved
14 INTC_TO_D INTD output from INTC input: when set (1) an interrupt has
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occurred on INTC
13 INTB_TO_D INTD output from INTB input: when set (1) an interrupt has
occurred on INTB
12 INTA_TO_D INTD output from INTA input: when set (1) an interrupt has
occurred on INTA
11 INTD_TO_C INTC output from INTD input: when set (1) an interrupt has
occurred on INTD
10 - Reserved
9 INTB_TO_C INTC output from INTB input: when set (1) an interrupt has
occurred on INTB
8 INTA_TO_C INTC output from INTA input: when set (1) an interrupt has
occurred on INTA
7 INTD_TO_B INTB output from INTD input: when set (1) an interrupt has
occurred on INTD
6 INTC_TO_B INTB output from INTC input: when set (1) an interrupt has
occurred on INTC
5 - Reserved
4 INTA_TO_B INTB output from INTA input: when set (1) an interrupt has
occurred on INTA
3 INTD_TO_A INTA output from INTD input: when set (1) an interrupt has
occurred on INTD
2 INTC_TO_A INTA output from INTC input: when set (1) an interrupt has
occurred on INTC
1 INTB_TO_A INTA output from INTB input: when set (1) an interrupt has
occurred on INTB
0 - Reserved
Table 13 : PCI Interrupt Status Register
14.3.3 Local Bus Interrupt Mask Register(Offset 0x77, BAR0)
Bits Name Description
7 MAILBOX Global mailbox interrupt enable
6 PCI_RD PCI read error interrupt enable
5 PCI_WR PCI write error interrupt enable
4 PCI_INT Global PCI interrupt to local interrupt enable
3 PCI_PERR PCI parity error interrupt enable
2 I2O_QWR I2O inbound post queue write interrupt enable
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1 DMA1 DMA channel 1 interrupt enable
0 DMA0 DMA channel 0 interrupt enable
Table 14 : Local Bus Interrupt Mask Register
14.3.4 Local Bus Interrupt Status Register(Offset 0x76, BAR0)
Bits Name Description
7 MAILBOX 1=interrupt has been requested by one or more of the
mailbox registers
0=no mailbox interrupts pending
6 PCI_RD See V3 datasheet
5 PCI_WR See V3 datasheet
4 PCI_INT See V3 datasheet
3 PCI_PERR See V3 datasheet
2 I2O_QWR See V3 datasheet
1 DMA1 See V3 datasheet
0 DMA0 See V3 datasheet
Table 15 : Local Bus Interrupt Status Register
14.3.5 PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read 0xD2, BAR0)
Bits Name Description
15 EN15 Local interrupts on PCI bus writes/reads to mailbox15
enable
14 EN14 Same as above for mailbox 14
13 EN13 Same as above for mailbox 13
12 EN12 Same as above for mailbox 12
11 EN11 Same as above for mailbox 11
10 EN10 Same as above for mailbox 10
9 EN9 Same as above for mailbox 9
8 EN8 Same as above for mailbox 8
7 EN7 Same as above for mailbox 7
6 EN6 Same as above for mailbox 6
5 EN5 Same as above for mailbox 5
4 EN4 Same as above for mailbox 4
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3 EN3 Same as above for mailbox 3
2 EN2 Same as above for mailbox 2
1 EN1 Same as above for mailbox 1
0 EN0 Same as above for mailbox 0
Table 16 : PCI Mailbox WRITE/READ Interrupt Control Register
14.3.6 Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0 Read 0xD6, BAR0)
Bits Name Description
15 EN15 PCI interrupts on Local bus writes/reads to mailbox15
enable
14 EN14 Same as above for mailbox 14
13 EN13 Same as above for mailbox 13
12 EN12 Same as above for mailbox 12
11 EN11 Same as above for mailbox 11
10 EN10 Same as above for mailbox 10
9 EN9 Same as above for mailbox 9
8 EN8 Same as above for mailbox 8
7 EN7 Same as above for mailbox 7
6 EN6 Same as above for mailbox 6
5 EN5 Same as above for mailbox 5
4 EN4 Same as above for mailbox 4
3 EN3 Same as above for mailbox 3
2 EN2 Same as above for mailbox 2
1 EN1 Same as above for mailbox 1
0 EN0 Same as above for mailbox 0
Table 17 : Local Bus Mailbox WRITE/READ Interrupt Control Register
14.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA, BAR0)
Bits Name Description
15 EN15 1=Mailbox 15 has requested a PCI or Local write/read
interrupt
0=Mailbox 15 has not requested a PCI or Local write/read
interrupt
14 EN14 Same as above for mailbox 14
13 EN13 Same as above for mailbox 13
12 EN12 Same as above for mailbox 12
11 EN11 Same as above for mailbox 11
10 EN10 Same as above for mailbox 10
9 EN9 Same as above for mailbox 9
8 EN8 Same as above for mailbox 8
7 EN7 Same as above for mailbox 7
6 EN6 Same as above for mailbox 6
5 EN5 Same as above for mailbox 5
4 EN4 Same as above for mailbox 4
3 EN3 Same as above for mailbox 3
2 EN2 Same as above for mailbox 2
1 EN1 Same as above for mailbox 1
0 EN0 Same as above for mailbox 0
Register cleared by writing 1, writing 0 has no effect
Table 18 : Mailbox Write/Read Interrupt Status Register
14.3.8 INTREG Register(Offset 0x40, BAR1)
Bits Name Description
15 - Reserved
14 - Reserved
13 - Reserved
12 - Reserved
11 - Reserved
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10 - Reserved
9 - Reserved
8 - Reserved
7 - Reserved
6 - Reserved
5 - Reserved
4 - Reserved
3 - Reserved
2 IIOF2EN PC to DSP TIMIIOF2 interrupt enable
1 IIOF1EN PC to DSP TIMIIOF1 interrupt enable
0 IIOF0EN PC to DSP TIMIIOF0 interrupt enable
Table 19 : INTREG Register
14.4 Example
The example below shows how the DSP can cause an interrupt on the PC by writing
to mailbox register 0.
The PC must first enable the interrupts, to do this the following register bits must be
altered, and an interrupt thread handler needs to be created.
PCI Interrupt Configuration Register(Offset 0x4C, BAR0) – bit 31 must be set.
Local Bus Interrupt Mask Register(Offset 0x77, BAR0) – bit 7 must be set.
PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read
0xD2, BAR0)
– bit 0 of the write register (0xD4) must be set.*
An Interrupt service routine must be set up, in this the following register will need to
be cleared.
Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA,
BAR0) – bit 0 of the write register (0xD8) must be cleared.**
Local Bus Interrupt Status Register(Offset 0x76, BAR0) – bit 7 must be cleared.
To cause the interrupt the DSP needs to write to the mailbox register in the V3 chip,
this is done by writing to address 0x1C0000C0 (this will write to the first four
mailboxes).
*These are two separate registers, one to enable interrupts on reads from the
mailbox registers the other to enable interrupts on writes to the mailbox registers.
**These are two separate registers, one shows interrupt status for reads from the
mailbox register the other to show interrupt status on writes to the mailbox registers.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
15 Performance Figures
Following are the performance figures for the SMT310. Performance figures are
stated for the SMT310 with the Rev. A1 V3 PCI bridging device fitted. Further
performance figures will be issued as faster V3 PCI bridging devices become
available and are fitted to the SMT310.
Transfer type Speed in
Mbytes/second
Standard read from Global bus TBA
Standard write to Global bus TBA
DMA read from Global bus TBA
DMA write to Global bus TBA
DMA read from shared memory 75-100 Will Vary depending on PCI traffic
DMA write to shared memory 75-100 Will Vary depending on PCI traffic
DMA read from SDB 75-100 Will Vary depending on PCI traffic
DMA write to SDB 75-100 Will Vary depending on PCI traffic
DMA read from ComPort TBA
DMA write to ComPort TBA
Comments
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
16 Mechanical Dimensions
The board size is 108 mm by 175 mm
17 Power consumption
The SMT310 is powered from the PC’s internal power supply. The card uses the 3.3v
and 5v supplies. The following current consumption figures were measured using a
LEM current clamp during a quiescent period.
Current drawn from 3.3v supply : 260mA
Current drawn from 5v supply : 160mA
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
18 Cables and Connectors
18.1 SDB
No SDB cables are supplied with the SMT310. You can order them separately from
Sundance with part number SMT510-SDBxx, where xx is the cable length in
centimetres.
18.1.1 SDB Connector
Function Pin Pin Function Function Pin Pin Function
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2 1
4 3
6 5
8 7
10 9
12 11
14 13
16 15
18 17
20 19
CLK D9
D0 D10
D1 D11
D2 D12
D3 D13
D4 D14
D5 D15
D 6 USERDEF0
D7 WEN
D8 USERDEF1
Table 20: SDB Pin-out
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
GND
GND
GND
GND
GND
GND
GND
GND
REQ
ACK
18.2 ComPorts
The cables used with FMS connectors are not supplied with the SMT310. You can
order them separately from Sundance with part number SMT500-FMSxx, where xx is
the cable length in centimetres.
18.3 Buffered ComPort Cabling
Connecting between buffered ComPorts requires a 1 to 1 cable; the SMT502-Buffer
is the recommended cable assembly and can be purchased separately.
Cable plugs 3M Scotchflex 10126-6000EL FES part 038740A
Plug shells 3M Scotchflex 10326-A200-00 FES part 038760D
Cable type 3M Scotchflex KUCKMPVVSB28-13PAIR FES part 038781E
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Page 47 of 50 SMT310 User Manual V1.6
This cable has 13 individual pairs, with an overall shield, and an outer diameter of
7mm. Cable length should be as short as possible. The maximum tested cable length
is 1 meter.
On reset, each ComPort initialises to being either an input or an output.
Do not connect ‘Reset to Input’ ComPorts together.
Do not connect ‘Reset to Output’ ComPorts together.
However if this should occur, no damage will result, because ComPort direction
signals disable relevant ComPorts.
The following table shows connector pin-out and cable pair connections. This is
important, as the critical signals must be paired with a ground as shown. The
allocation to twisted pairs is based on grouping the data signals because they change
at the same time, so that crosstalk is not an issue. Each control signal has its own
ground:
Pin Twisted
Pair
1 1 I/O_OUT I/O_IN 15 8 D2 D2
2 1 GND GND 16 8 D3 D3
3 2 I/O_IN I/O_OUT 17 9 D4 D4
4 2 GND GND 18 9 D5 D5
5 3 /CSTRB /CSTRB 19 10 D6 D6
6 3 GND GND 20 10 D7 D7
7 4 /CRDY /CRDY 21 11 VCC VCC
8 4 GND GND 22 11 GND GND
9 5 /CREQ /CREQ 23 12 /RST_OUT /RST_IN
10 5 GND GND 24 12 GND GND
11 6 /CACK /CACK 25 13 /RST_IN /RST_OUT
12 6 GND GND 26 13 GND GND
13 7 D0 D0 SHELL - SHIELD SHIELD
14 7 D1 D1
RTI
Signal
RTO
Signal
Pin Twisted
Pair
RTI Signal RTO Signal
Table 21 : Buffered ComPort connector pin out
The overall shield is attached to the body of the metal plug shell.
The signal VCC is fused on the board at 1 amp; it automatically resets when the load
is removed.
Page 48 of 50 SMT310 User Manual V1.6
When the buffered ComPort is reset to input, pins 1 and 23 are always driven and
pins 3 and 25 are always receivers. When the buffered ComPort is reset to output,
pins 3 and 25 are always driven and pins 1 and 23 are always receivers.
18.4 JTAG cabling
Two cable options exist for the SMT310; SMT501-JTAG is designed to connect two
SMTxxx carrier boards ie, SMT310 controlling an SMT328 VME carrier. The length of
SMT501 is 1 meter. A variation of the SMT501-JTAG is the SMT510-XDS. This
provides an XDS-510 14-way connector and will interface to a range of nonSundance products.
The 20-way JTAG connectors require the following cabling components:
Cable plugs 3M Scotchflex 10120-6000EL, FES part 038739R
Plug shells 3M Scotchflex 10320-A200-00, FES part 038759A
Cable type 3M Scotchflex KUCKMPVVSB28-10PAIR, FES part 038780G
When using the SMT310s Buffered JTAG connector to connect to a JTAG slave, the
buffered connector pins are used as follows:
Pin Signal Direction Description
1 TDI OUT JTAG data out
2 GND
3 TDO IN JTAG data in
4 GND
5 TMS OUT JTAG Test mode select
6 GND
7 TCK OUT JTAG clock 10MHz
8 GND
9 TCK_RET IN JTAG clock return
10 GND
11 /TRST OUT JTAG Reset
12 GND
13 /RESET OUT Board Reset out
14 PD IN Presence detect when pulled high
15 /DETECT OUT Detect external JTAG controller when
grounded
Page 49 of 50 SMT310 User Manual V1.6
16 CONFIG OPEN COLL Global open collector C4x CONFIG
17 EMU0 IN Buffered EMU0 output
18 EMU1 IN Buffered EMU1 output
19 SPARE1
20 SPARE2
Table 22 : Buffered JTAG connector pin functionality as JTAG master
Internal JTAG (XDS-510 compatible) pin header pin information:
Pin Signal Direction Description
1
TMS
Out
2 /TRST Out
3 TDI Out
JTAG Test mode select
JTAG Reset
JTAG data out
4 GND
5 PD (+5)
5v Power
6 Key No pin fitted
7 TDO In
JTAG data in
8 GND
9 TCK_RET In
JTAG clock return
10 GND
11 TCK Out
JTAG clock 10MHz
12 GND
13 EMU0 In
14 EMU1 In
Buffered EMU0 In
Buffered EMU1In
Table 23 : Internal JTAG out (XDS-510) pin descriptions
Page 50 of 50 SMT310 User Manual V1.6
19 Where’s that Jumper?
Below is a diagram to help locate the jumpers:
-
Figure 9 : Jumper Finder Diagram
J7 and J10 are test points and should not be connected.
J9 TIM ComPort3 –>J2
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