Sundance SMT310 User Manual v.1.6
SMT310
User Manual V1.6
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
Page 2 of 50 SMT310 User Manual V1.6
Revision History
Date Comments Engineer Version
11/04/00 Initial SMT310 Draft AJP 0.5
21/08/00 ComPort + JTAG sections TJW 0.6
02/10/00 SDB Interface AJP 0.7
30/10/00 JTAG Pin information AJP 0.8
6/11/00 Amendments, addition of software section TJW 0.9
2/2/2001 Syntax updates AJP 1.0
16/01/02 Re-edit SP 1.1
20/02/02 SP 1.2
06/03/02 ComPort Mirrors SP 1.3
29/05/02 Installation Procedure SP 1.4
22/01/04 Update for V5 board and editing SP 1.5
15/03/06 Firmware v4.8 new ComPort features, updated
ComPort configuration register & Quick Switch
behaviour, updated Fig.1: ComPort connection
diagram.
JJW 1.6
Page 3 of 50 SMT310 User Manual V1.6
Table of Contents
1 Introduction ..................................................................................................................................... 8
2 Functional Description .................................................................................................................... 9
3 Setting Up the SMT310................................................................................................................. 10
4 Memory Map................................................................................................................................. 11
4.1 PCI Bridge Chip Internal Register (BAR0)........................................................................... 11
4.2 I/O Space Register Assignments (BAR1) ............................................................................ 11
4.3 Memory Space Assignments(BAR2).................................................................................... 12
5 DSP Resource Memory Map........................................................................................................13
6 Shared Memory Resource............................................................................................................ 14
7 Sundance Digital Bus (SDB)......................................................................................................... 15
8 ComPorts...................................................................................................................................... 16
8.1 Buffered ComPort................................................................................................................. 17
9 ComPort to PCI Interface....................................................................................................... .......19
9.1 ComPort Registers (Offset 0x10, BAR1).............................................................................. 19
9.2 Control Register (Offset 0x14, BAR1).................................................................................. 19
9.3 Status Register (Offset 0x14, BAR1 , Read-Only)............................................................... 20
9.4 Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 21
10 JTAG Controller ............................................................................................................................ 23
11 Using the SMT310 External/Internal JTAG with TI Tools............................................................. 24
12 Firmware Upgrades ...................................................................................................................... 25
13 Global/Local Bus Transfers, DSP <-> PCI................................................................................... 27
13.1 Mailbox Accesses................................................................................................................. 27
13.1.1 Doorbell Interrupts....................................................................................................... 28
13.2 DSP Interrupt Control...........................................................................................................28
13.3 DSP To Local Aperture 0 control and Accessing................................................................. 29
13.3.1 Global bus access protocol ......................................................................................... 31
14 Interrupts....................................................................................................................................... 34
14.1 SMT310-To-PCI Interrupts................................................................................................... 34
14.2 PCI-To-SMT310 Interrupts................................................................................................... 35
14.3 Interrupt Registers................................................................................................................ 35
14.3.1 PCI Interrupt Configuration Register(Offset 0x4C, BAR0) .......................................... 35
14.3.2 PCI Interrupt Status Register(Offset 0x48, BAR0)...................................................... 37
14.3.3 Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 38
14.3.4 Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 39
14.3.5 PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read
0xD2, BAR0)................................................................................................................................. 39
Page 4 of 50 SMT310 User Manual V1.6
14.3.6 Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0
Read 0xD6, BAR0) ....................................................................................................................... 40
14.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA,
BAR0) 41
14.3.8 INTREG Register(Offset 0x40, BAR1)........................................................................ 41
14.4 Example ............................................................................................................................... 42
15 Performance Figures .................................................................................................................... 44
16 Mechanical Dimensions................................................................................................................ 45
17 Power consumption ...................................................................................................................... 45
18 Cables and Connectors ................................................................................................................ 46
18.1 SDB...................................................................................................................................... 46
18.1.1 SDB Connector............................................................................................................ 46
18.2 ComPorts ............................................................................................................................. 46
18.3 Buffered ComPort Cabling ................................................................................................... 46
18.4 JTAG cabling................................................................................................................... .....48
19 Where’s that Jumper?...................................................................................................................50
Page 5 of 50 SMT310 User Manual V1.6
Table of Tables
Table 1 : Table of Abbreviations..................................................................................7
Table 2 : I/O address space map...............................................................................11
Table 3 : Memory space map....................................................................................12
Table 4 : Memory space map....................................................................................13
Table 5 : SDB Control Register .................................................................................15
Table 6 : ComPort configuration register...................................................................17
Table 7 : Comport selection.......................................................................................17
Table 8 : Control Register..........................................................................................19
Table 9 : Status Register...........................................................................................21
Table 10 : Interrupt Control Register..........................................................................22
Table 11 : JTAG Header pin function.........................................................................26
Table 12 : PCI Interrupt Configuration Register.........................................................37
Table 13 : PCI Interrupt Status Register....................................................................38
Table 14 : Local Bus Interrupt Mask Register...........................................................39
Table 15 : Local Bus Interrupt Status Register..........................................................39
Table 16 : PCI Mailbox WRITE/READ Interrupt Control Register..............................40
Table 17 : Local Bus Mailbox WRITE/READ Interrupt Control Register....................40
Table 18 : Mailbox Write/Read Interrupt Status Register...........................................41
Table 19 : INTREG Register......................................................................................42
Table 20: SDB Pin-out...............................................................................................46
Table 21 : Buffered ComPort connector pin out.........................................................47
Table 22 : Buffered JTAG connector pin functionality as JTAG master.....................49
Table 23 : Internal JTAG out (XDS-510) pin descriptions..........................................49
Page 6 of 50 SMT310 User Manual V1.6
Table of Figures
Figure 1: ComPort connection diagram.....................................................................16
Figure 2 : TBC Data Routing .....................................................................................23
Figure 3 : JTAG header pin numbers.........................................................................26
Figure 4 : Local Bus to DSP Connectivity..................................................................27
Figure 5 : DSP Transfer via the Local Aperture 0......................................................30
Figure 6 : Timing diagram for DSP local bus access.................................................32
Figure 7 : SMT310 to PCI Interrupts..........................................................................34
Figure 8 : PCI to SMT310 Interrupts..........................................................................35
Figure 9 : Jumper Finder Diagram.............................................................................50
Page 7 of 50 SMT310 User Manual V1.6
Table Of Abbreviations
BAR Base Address Region
DMA Direct Memory Access
EPLD Electrically Programmable Logic Device
PCI Peripheral Component Interconnect
SDB Sundance Digital Bus
SRAM Static Random Access Memory
TBC Test Bus Controller
TIM Texas Instruments Module
Table 1 : Table of Abbreviations
1 Introduction
The SMT310 is a single site module carrier board that provides access to a TIM
module over the PCI bus.
An on-board JTAG controller allows systems to be debugged using Code Composer
Studio. This JTAG controller also has buffered outputs that can be accessed using
connectors on the carrier’s back panel. This allows off-board devices to be connected
into the JTAG chain.
A single buffered ComPort with conflict protection is also available on the chassis
back panel. This will have the versatility to access any of four ComPorts on the TIM.
The main connection to the PCI bus is via the module Global Bus. A single ComPort
is also be mapped to the PCI bus providing support for application boot and data
transfer.
A 1 MB of SRAM is mapped on to the Global Bus and can be accessed by the TIM as
a global resource or by the PCI Bridge.
The board requires a 3.3 volt supply that is taken from the PCI edge connector and is
made available at the fixing pillars for the module.
An ‘on-board’ SDB interface to the PCI Bridge allows the card to be interfaced to SDB
standard modules.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
2 Functional Description
The PCI interface connects to a Quick Logic EPC363 Bridge device. It has a 32-bit
33MHz PCI interface that supports I2C control, mailbox register access, and direct
memory reads and writes. The PCI bus is translated to a Local PCI bus, which is
connected to the following devices:
• Shared SRAM 1MB
• Control EPLD that manages ComPort access and the SDB interface
• JTAG controller
• Module Global Bus
• PCI Bridge device
An on-board arbitration unit controls which device, Master Module or PCI Bridge, has
access to this local PCI bus resource.
The local PCI bus has a 33MHz clock to control transfers between the various
resources. This is available on the CLKIN pin on the Master site and should be
selected in preference to the on-board oscillator to allow the DSP to synchronise its
accesses to and from the PCI Bridge registers. The PCI Bridge has an input and
output FIFO capable of transferring 256 32-bit words of data to and from the DSP at
33MHz, thus bursting a maximum local bus transfer rate of 132MB/s.
The Master Module can access the SRAM over the PCI local bus at transfer rates up
to 100MB/s. The number of wait states required by the Master Module will vary
depending on the speed of the module. Maximum access rates use a 20ns strobe
cycle.
The JTAG controller is based on the TI 8990 device, and drivers can be supplied for
Code Composer Studio (Part Number
SMT6012).
The on-board SDB connector can be configured with a jumper to be either an input
port or an output port, accessible via the Host PCI interface. It is not intended as a
high-speed link as it has only a single 16-bit FIFO.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
3 Setting Up the SMT310
The SMT310 should be set up in the following way.
• Turn the PC off and insert the Card into a spare PCI slot.
• Switch on PC and wait for the OS to boot up.
• Windows 95/98/NT/2000 will detect a new hardware.
• Windows should automatically find the drivers from the CD, if not browse to the
CD or if you downloaded from the ftp site to the folder where you unzipped the
SMT6300 software.
• When you run it, 3L application software will be able to detect the SMT310
provided the SET TISLINK variable is set to SMT320.
• You can run the SMTBoardInfo application to detect the number of SMT310s in
your system and report their slot positions and I/O addresses. This information is
required when setting up code composer for the board. SMTBoardInfo is installed
as part of the SMT6300 package.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
4 Memory Map
All address information is given in bytes :
4.1 PCI Bridge Chip Internal Register (BAR0)
Please see V363EPC Local Bus PCI Bridge User Manual V1.04
(http://www.quicklogic.com/home.asp?PageID=223&sMenuID=114#Docs) for details
of internal registers.
Note: Where required, registers from the V3 datasheet have been included.
4.2 I/O Space Register Assignments (BAR1)
In target mode, the SMT310 is accessed by a host device across the PCI bus. This
allows access to the target mode registers. The operating system or BIOS will
normally allocate a base address for the target mode registers of each SMT310.
Access to each register within the SMT310 is then specified by this base address and
the offset shown in the table below.
The I/O address space is decoded as shown in the table below.
Offset Register(Write) Register(Read) Width
0x0 - -
0x4 - -
0x8 - -
0x0C - -
0x10 COMPORT_OUT COMPORT_IN 32
0x14 CONTROL STATUS 32
0x18 INT_CONTROL 32
0x1C - -
0x20 to 0x3F COMPORT Configuration COMPORT Configuration
0x24 COM_SWITCH COM_SWITCH 16
0x40 INTREG INTREG 16
0x80 to 0xAF TBC Write TBC Read 16
Table 2 : I/O address space map
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
4.3 Memory Space Assignments(BAR2)
Address Description Notes
0x0000 0000 – 0x000F FFFF Shared Memory Bank 1MB SRAM
0x00200090
ComPort Data
Mirror
Mirror of COMPORT_OUT /
COMPORT_IN in
I/O Space
Register Assignments
(BAR1)
See Note 2
0x00200094
ComPort Status
Mirror
Mirror of Control / Status in I/O
Space Register
Assignments (BAR1)
See Note 2
0x00200098
ComPort Int_Control
Mirror
Mirror of Int_Control in I/O
Space Register
Assignments (BAR1)
See Note 2
0x0020 0000-0x0020 007F Global Bus See Note 1
0x0020 0240 – 0x0020 025F SDB Data Register Input/Output 16 bit SDB Interface
0x0020 0260 – 0x0020 027F SDB Control Register SDB Control/Status
Table 3 : Memory space map
Note 1: In order for the TIM to respond to accesses for this area address line
GADD30 and GADD19 of the TIM site connector must be decoded as high and
GADD7 and GADD5 must be decoded as low.
Note 2: These mirrors of Addresses in the I/O Space (BAR1) allow increased transfer
speeds across the host ComPort link (in excess of 10X increase).
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
5 DSP Resource Memory Map
The Master module on the SMT310 can access the various resources available,
including the Shared SRAM and the PCI Bridge. Access to the PCI Bridge allows the
DMA engine in the PCI Bridge to be initiated by the DSP, mailbox registers can also
be manipulated. The table below illustrates the resources and their corresponding
address region when accessed by the Master module.
C60 Address Access Description Notes
0xD000 0000 – 0xD00F FFFF Shared Memory Bank 1Mbyte SRAM
0x1C00 0000 – 0x1C00 00FF PCI Bridge Registers PCI Bridge Internal resisters
0x1800 0000 – 0x183F FFFF Local-to-PCI Aperture 0 PCI Bridge Aperture 0 Space
Table 4 : Memory space map
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
6 Shared Memory Resource
The shared memory on the SMT310 is 1 MB of SRAM, which can be accessed by the
PCI host and the TIM module. This allows applications to transfer data between the
host PC and the DSP at data rates approaching 100MB/s. The address of the shared
memory is shown in the memory map.
The PCI Bridge DMA processor sees the shared memory at a different address from
that used for normal accesses. For normal memory access the memory base address
register offset is 0x0000 0000. For DMA access address line A28 (On hardware
interface) must be high, therefore DMA memory access starts at 0x4000 0000 (Not
0x1000 0000 as addressing is in bytes).
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
7 Sundance Digital Bus (SDB)
A growing number of Sundance’s Modules have an on-board SDB. The SDB is
described on the Sundance web site at www.sundance.com/html/pdf_info.htm .
The following register controls the carrier’s SDB.
D7 D6 D5 D4 D3 D2 D1 D0
X X OFFF IPFF RW RW RW RXNTX
Table 5 : SDB Control Register
The SDB control and status register is located at BAR2 offset 0x00200260. The bit
definitions are shown below:
RXNTX
SDB Direction. The SDB direction is set using Jumper J8 (
Figure 9 : Jumper Finder Diagram) on the SMT310, When the jumper is
out the SDB is set for receive mode; when the jumper is in the SDB is set
for transmit mode. This bit indicates the direction set: 0=Receive,
1=Transmit.
RW
IPFF
General scratch bits
Input FIFO full: When set, a 16-bit value has been latched in the data
register ready for reading. This bit is automatically cleared on a read from
the data register.
OPFF
Output FIFO full: This bit is set when a 16-bit value is written to the FIFO
and is automatically cleared when it has been sent out of the SDB.
The SDB data register is located at BAR2 offset 0x00200240. You can write 16-bit
values to this location to transfer them over the SDB interface as long as the OPFF
flag in the status register is clear and J8 jumper is in.
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999
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