Sundance SMT300Q User Manual v.1.6

SMT300Q

SMT300Q User Guide V1.6

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Page 2 of 61 SMT300Q SMT300Q User Guide V1.65

Date Comments

Engineer Version

30-09-02 Original Document SP 1.1 23/04/04 PLL register SP 1.2 21/05/04 Power connector part number correction TJW 1.3 16/11/04 Added: TIM sites location SM 1.4 26/11/05 Corrected: location Pin 1 of J21 SM 1.5 7/12/05 Removed SDB references AJP 1.6

Page 3 of 61 SMT300Q SMT300Q User Guide V1.65

Table of Contents

1 Introduction ..................................................................................................................................... 8

2 Functional Description .................................................................................................................... 9

2.1 Block Diagram......................................................................................................................10

2.2 ComPort Switching Matrix.................................................................................................... 11

2.3 TIM Sites location.................................................................................................................12

3 Setting Up the SMT300Q.............................................................................................................. 13

4 Host Memory Map......................................................................................................................... 14

4.1 CompactPCI Bridge Chip Internal Register (BAR0)............................................................. 14

4.2 I/O Space Register Assignments (BAR1) ............................................................................ 14

4.3 Memory Space Assignments(BAR2).................................................................................... 15

5 DSP Resource Memory Map........................................................................................................ 16

6 Shared Memory Resource............................................................................................................ 17

7 ComPorts...................................................................................................................................... 18

7.1 ComPort Switching (Quick Switches)................................................................................... 18

7.2 Buffered ComPort................................................................................................................. 19

8 ComPort to CompactPCI Interface ............................................................................................... 23

8.1 ComPort Registers (Offset 0x10, BAR1).............................................................................. 23

8.2 Control Register (Offset 0x14, BAR1).................................................................................. 23

8.3 Status Register (Offset 0x14, BAR1 , Read-Only)............................................................... 24

8.4 Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 25

9 PLL................................................................................................................................................ 26

9.1 PLLREG1 (BAR1 Offset 6016).............................................................................................. 26

9.2 PLLREG2 (BAR1 Offset 6416).............................................................................................. 26

9.3 Frequency Select (Bank 2, 3 and 4)..................................................................................... 26

9.4 Phase Shift Select (Bank 2) ................................................................................................. 27

9.5 Phase Shift Select (Bank 3 and 4)....................................................................................... 27

10 JTAG Controller ............................................................................................................................ 28

11 Using the SMT300Q External/Internal JTAG with TI Tools.......................................................... 30

12 Firmware Upgrades ...................................................................................................................... 31

13 Global/Local Bus Transfers, DSP <-> CompactPCI.................................................................... 33

13.1 Mailbox Accesses................................................................................................................. 33

13.1.1 Doorbell Interrupts....................................................................................................... 34

13.2 DSP Interrupt Control...........................................................................................................34

13.3 DSP To Local Aperture 0 control and Accessing................................................................. 35

13.3.1 Global bus access protocol ......................................................................................... 36

14 Interrupts....................................................................................................................................... 40

14.1 SMT300Q-To-CompactPCI Interrupts.................................................................................. 40

14.2 CompactPCI-To-SMT300Q Interrupts.................................................................................. 41

14.3 Interrupt Registers................................................................................................................ 41

14.3.1 CompactPCI Interrupt Configuration Register(Offset 0x4C, BAR0)............................ 41

14.3.2 CompactPCI Interrupt Status Register(Offset 0x48, BAR0)........................................ 43

14.3.3 Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 44

Page 4 of 61 SMT300Q SMT300Q User Guide V1.65

14.3.4 Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 45

14.3.5 CompactPCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0,

BAR0 Read 0xD2, BAR0)............................................................................................................. 45

14.3.6 Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset Write 0xD4, BAR0

Read 0xD6, BAR0) ....................................................................................................................... 46

14.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA, BAR0) 47

14.3.8 INTREG Register(Offset 0x40, BAR1)........................................................................ 47

14.4 Example ............................................................................................................................... 48

14.4.1 An Interrupt service routine must be set up, in this the following register will need to be

cleared 48

15 Stand-Alone Mode........................................................................................................................ 50

16 Performance Figures .................................................................................................................... 51

16.1 Relative JTAG speeds.......................................................................................................... 52

17 Mechanical Dimensions................................................................................................................ 53

18 Power consumption ...................................................................................................................... 53

19 Cables and Connectors ................................................................................................................ 54

19.1 ComPorts ............................................................................................................................. 54

19.2 Buffered ComPort Cabling ................................................................................................... 54

19.3 JTAG back panel cabling ..................................................................................................... 56

20 Where’s that Jumper?................................................................................................................... 58

21 Expansion Header (J2)................................................................................................................. 59

22 JTAG Interface circuits.................................................................................................................. 60

22.1 Signal Description ................................................................................................................ 60

Page 5 of 61 SMT300Q SMT300Q User Guide V1.65

Table of Figures

Figure 1 : Block Diagram for SMT300Q (Master site only) ........................................10

Figure 2: ComPort Switching Matrix ..........................................................................11

Figure 3: TIM sites location........................................................................................12

Figure 4 : Operation of quick switches.......................................................................18

Figure 5 : TBC Data Routing .....................................................................................28

Figure 6 : JTAG header pin numbers.........................................................................32

Figure 7 : Local Bus to DSP Connectivity..................................................................33

Figure 8 : DSP Transfer via the Local Aperture 0......................................................36

Figure 9 : Timing diagram for DSP local bus access.................................................38

Figure 10 : SMT300Q to CompactPCI Interrupts.......................................................40

Figure 11 : CompactPCI to SMT300Q Interrupts.......................................................41

Figure 12 : Auxiliary Power Connector ......................................................................50

Figure 13 : JTAG speed Comparison chart ...............................................................52

Figure 14 : Jumper Finder Diagram...........................................................................58

Figure 15 : Expansion Header Pin Out Diagram........................................................59

Figure 16 : JTAG Slave circuit...................................................................................61

Page 6 of 61 SMT300Q SMT300Q User Guide V1.65

Table of Tables

Table 1 : Table of Abbreviations..................................................................................7

Table 2 : I/O address space map...............................................................................14

Table 3 : Memory space map....................................................................................15

Table 4 : Memory space map....................................................................................16

Table 6 : COM-SWITCH Register..............................................................................19

Table 7: Buffered ComPort 1 connections.................................................................20

Table 8: Buffered ComPort 2 connections.................................................................20

Table 9: Buffered ComPort 3 connections.................................................................20

Table 10: Buffered ComPort 4 connections...............................................................20

Table 11: Buffered ComPort 5 connections...............................................................21

Table 12: Buffered ComPort 6 connections...............................................................21

Table 13: Buffered ComPort 7 connections...............................................................21

Table 14: Buffered ComPort 8 connections...............................................................22

Table 15 : Buffered ComPort Additional Signals........................................................22

Table 16 : Control Register........................................................................................ 23

Table 17 : Status Register.........................................................................................24

Table 18 : Interrupt Control Register..........................................................................25

Table 19 : PLLREG1 Register ...................................................................................26

Table 20 : PLLREG2 Register ...................................................................................26

Table 21 : PLL Frequency Select ..............................................................................26

Table 22 : PLL Phase Shift Select (Bank 2)...............................................................27

Table 23 : PLL Phase Shift Select (Bank 3 and 4).....................................................27

Table 24 : JTAG Header pin function.........................................................................32

Table 25 : CompactPCI Interrupt Configuration Register...........................................43

Table 26 : CompactPCI Interrupt Status Register......................................................44

Table 27 : Local Bus Interrupt Mask Register...........................................................45

Table 28 : Local Bus Interrupt Status Register..........................................................45

Table 29 : CompactPCI Mailbox WRITE/READ Interrupt Control Register................46

Table 30 : Local Bus Mailbox WRITE/READ Interrupt Control Register....................46

Table 31 : Mailbox Write/Read Interrupt Status Register...........................................47

Table 32 : INTREG Register......................................................................................48

Table 33 : Performance Figures ................................................................................ 51

Table 35 : Buffered ComPort connector pin out.........................................................55

Table 36 : Buffered JTAG connector pin functionality as JTAG source.....................56

Table 37 : Buffered JTAG connector pin functionality as JTAG master.....................57

Page 7 of 61 SMT300Q SMT300Q User Guide V1.65

Table Of Abbreviations

BAR Base Address Region

DMA Direct Memory Access

EPLD Electrically Programmable Logic Device

CompactPCI Compact Peripheral Component Interconnect

SRAM Static Random Access Memory

TBC Test Bus Controller

TIM Texas Instruments Module

Table 1 : Table of Abbreviations

1 Introduction

The SMT300Q is a quad-site module carrier board that provides access to TIM modules over the CompactPCI bus.

The carrier can hold up to four ‘C6x modules and these can exchange data using ComPorts. A ComPort routing matrix, using electronic “quick switches”, is provided to allow module connectivity without external cables.

The first TIM on the carrier is known as the “Master Module” and an enhanced CompactPCI interface allows data packets to be exchanged between this module and the CompactPCI bus at burst speeds in the range of 60–100MB/s. The DSP has access to the CompactPCI Bridge internal registers to control DMAs, mailbox events, and interrupts.

1MB of SRAM is mapped on to the Global Bus and can be accessed as a global resource by the Host system across the CompactPCI Bridge or by the Master Module.

An on-board JTAG controller allows systems to be debugged using Code Composer Studio. This JTAG controller also has buffered outputs and inputs that can be accessed using connectors on the carrier’s back panel. This allows off-board devices to be connected into the JTAG chain.

Headers are provided for RESET_IN and RESET_OUT to allow multiple SMT300Q carriers to be connected together and synchronised.

The board requires a 3.3-volt supply that is taken from the CompactPCI connector and is made available at the fixing pillars for each module.

The SMT300Q may also be used with ‘C4x-based TIMs. When using these ‘C4x modules you must ensure that a Master ‘C4x Module does not use its global memory (if any is available) as this will prevent the SMT300Q from working.

If your SMT300Q does not have the Global Interface connector fitted (an ordering option), the Master Module will still be able to use its global bus resources. The module will not have access to the SMT300Q global resources, such as SRAM and CompactPCI Bridge, but full ComPort and JTAG control will still be available.

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

2 Functional Description

Figure 1 gives the block diagram of the SMT300Q. The Slave Module sites (2–4) are not shown, as they do not have any direct interface to the CompactPCI Bus, SRAM, ComPort or JTAG sections of the design. The connectivity of slave sites is shown in Figure 2.

The CompactPCI interface connects to a Quick Logic EPC363 bridge device. It has a 32-bit 33MHz CompactPCI interface that supports I2C control, mailbox register access, and direct memory reads and writes. The CompactPCI bus is translated to a Local bus, which is connected to the following devices:

• Shared SRAM 1MB

• Control EPLD that manages ComPort access

• JTAG controller

• Module Global Bus

• CompactPCI Bridge device

An on-board arbitration unit controls which device, Master Module or CompactPCI Bridge, has access to this local bus resource.

The local bus has a 33MHz clock to control transfers between the various resources. This is available on the CLKIN pin on the Master site and should be selected in preference to the on-board oscillator to allow the DSP to synchronise its accesses to and from the CompactPCI Bridge registers. The CompactPCI Bridge has an input and output FIFO capable of transferring 256 32-bit words of data to and from the DSP at 33MHz, thus bursting a maximum local bus transfer rate of 132MB/s.

The Master Module can access the SRAM over the local bus at transfer rates up to 100MB/s. The number of wait states required by the Master Module will vary depending on the speed of the module. Maximum access rates use a 20ns strobe cycle.

The JTAG controller is based on the TI 8990 device, and drivers can be supplied for Code Composer Studio (Part Number SMT6012 module site causes its SENSE pin to switch the module into the JTAG chain.

ComPort communication from the Host to the Master Module site is switched through a quick-switch, as illustrated in Figure 1. This allows the following connectivity:

). The presence of a TIM in a

• Connect the Host to the Master Module’s ComPort 3 (T1C3) and connect the FMS (C_BUF) directly to the external buffered ComPort. This allows any of the ComPorts on sites 1—4 to be connected to the external buffered ComPort with an FMS cable; or

• Connect the Host to the external buffered ComPort and connect ComPort 3 of the Master site to the FMS connector (C_BUF).

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Page 10 of 61 SMT300Q SMT300Q User Guide V1.65

2.1 Block Diagram

Figure 1 shows the block diagram of the SMT300Q. For simplicity, only CompactPCI, JTAG, and Buffered ComPort connectivity to the Master site is illustrated. Connectivity between the Master site and the three other sites is shown in the ComPort Switching Matrix block diagram, Figure 2.

ComPort Routing M atri x

340215

ComPor ts

Module Site

G lobal Bu s

HOST

ComPort

PCI Brid g e Da t a Bus (32 Bit )

Control

1 MB

PCI Bri dge Address Bus

EPLD

SRAM

8990

Buf f e r

PCI Brid g e

CPCI Connector

Buf f e re d

JTAG IN

Figure 1 : Block Diagram for SMT300Q (Master site only)

JTAG OUT

Page 11 of 61 SMT300Q SMT300Q User Guide V1.65

2.2 ComPort Switching Matrix

Cross Bar switch

Buffer

CPLD

Buffer

CPLD

Front Panel Sockets Front Panel SocketsFront Panel Sockets

To cPCI CPLD

Cross Bar switch

Buffer

Cross Bar switch

Buffer

Figure 2: ComPort Switching Matrix

Site 1 Site 2 Site 3 Site 4

CPLD

Comm 1 Comm 2 Comm 3 Comm 4 Comm 6Comm 5 Comm 7 Comm 8

Front Panel Sockets Front Panel SocketsFront Panel Sockets

Page 12 of 61 SMT300Q SMT300Q User Guide V1.65

2.3 TIM Sites location

cPCI

Connector

TIM Site 4 TIM Site 3

TIM Site 1

MASTER MODULE

TIM Site 2

Figure 3: TIM sites location

Page 13 of 61 SMT300Q SMT300Q User Guide V1.65

3 Setting Up the SMT300Q

The SMT300Q should be set up in the following way.

• Turn the PC off and insert the card into a spare CompactPCI slot.

• Switch on PC and wait for the O/S to boot up.

• Windows 95/98/NT/2000 will detect new hardware.

• Windows should automatically find the drivers from the CD, if not browse to the

CD or if you downloaded from the ftp site to the folder where you unzipped the SMT6300 software.

• You can run the SMTBoardInfo application to detect the number of SMT300Qs in your system and report their slot positions and I/O addresses. This information is required when setting up code composer for the board.

4 Host Memory Map

All address information is given in bytes :

4.1 CompactPCI Bridge Chip Internal Register (BAR0)

Please see V363EPC Local Bus CompactPCI Bridge User Manual (http://www.quicklogic.com/home.asp?PageID=223&sMenuID=114#Docs) for details of internal registers.

Where required, registers from the V3 datasheet have been included.

4.2 I/O Space Register Assignments (BAR1)

In target mode, a host device accesses the SMT300Q across the CompactPCI bus, which gives access to the target mode registers. The operating system or BIOS will normally allocate a base address for the target mode registers of each SMT300Q. Access to each register within the SMT300Q is then made at offsets from this base address as shown in the table below.

Offset (Hex) Register(Write) Register(Read) Width

0x00 - - 0x04 - - 0x08 - -

0x0C - -

0x10 COMPORT_OUT COMPORT_IN 32 0x14 CONTROL STATUS 32 0x18 INT_CONTROL 32

0x1C - -

0x20 to 0x3F COMPORT Configuration COMPORT Configuration

0x24 COM_SWITCH COM_SWITCH 16

0x2C COM_SWITCH_EX COM_SWITCH_EX 32

0x40 INTREG INTREG 16

0x80 to 0xAF TBC Write TBC Read 16

Table 2 : I/O address space map

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

4.3 Memory Space Assignments(BAR2)

Address (Hex) Description Notes

0x0000 0000 – 0x000F FFFF Shared Memory Bank 1MB SRAM

0x00200090 ComPort Data

Mirror

Mirror of COMPORT_OUT /

COMPORT_IN in

I/O Space

(BAR1)

See Note 2

0x00200094 ComPort Status

Mirror

0x00200098 ComPort Int_Control

Mirror

Mirror of Control / Status in

Space Register

Assignments (BAR1)

See Note 2

Mirror of Int_Control in

I/O

Space Register

I/O

Assignments (BAR1)

See Note 2

0x0020 0000-0x0020 007F Global Bus See Note 1

Table 3 : Memory space map

Note 1: In order for the TIM to respond to accesses for this area address line GADD30 and GADD19 of the TIM site connector must be decoded as high and GADD7 and GADD5 must be decoded as low.

Note 2: These mirrors of Addresses in the I/O Space (BAR1) allow increased transfer speeds across the host ComPort link (in excess of 10X increase).

5 DSP Resource Memory Map

The Master module on the SMT300Q can access the various board resources, including the Shared SRAM and the CompactPCI Bridge. This allows the DSP to control the CompactPCI Bridge’s DMA engine and manipulate mailbox registers. The table below illustrates the resources and their corresponding address region when accessed by the Master module.

C60 Address Access Description Notes

0xD000 0000 – 0xD00F FFFF Shared Memory Bank 1MB SRAM

0x1C00 0000 – 0x1C00 00FF CompactPCI Bridge

Registers

0x1800 0000 – 0x183F FFFF Local-to-CompactPCI

Aperture 0

Table 4 : Memory space map

CompactPCI Bridge Internal

resisters

CompactPCI Bridge Aperture 0

Space

6 Shared Memory Resource

The SMT300Q has 1 MB of shared SRAM that can be accessed by both the CompactPCI host and the Master module. This allows applications to transfer data between the host PC and the DSP at data rates approaching 100MB/s. The address of the shared memory is shown in the memory map.

The CompactPCI Bridge DMA processor sees the shared memory at a different address from that used for normal accesses. For normal memory access the memory base address register offset is 0x0000 0000. For DMA access address line A28 (On hardware interface) must be high, therefore DMA memory access starts at 0x4000 0000 (Not 0x1000 0000 as addressing is in bytes).

7 ComPorts

Figure 2 shows how the ComPorts of each TIM site are connected. The SMT300Q gives access to all six ComPorts on each of the four TIM sites. All of

the ComPorts can be connected buffered connectors on the front panel of the carrier card.

There is a connection from the CompactPCI interface to ComPort 3 on TIM site 1 for booting the TIM. This connection can be severed with a quick switch (COM-SWITCH register offset 0x24, BAR1 bit 15)

7.1 ComPort Switching (Quick Switches)

Several of the TIM ComPorts can be linked together without the need for external cables. This is done using quick switches controlled by the COM-SWITCH register (BAR1, offset 0x24)

For all of the quick switches expect the one controlled by bit 15 of the COM-SWITCH register, the following diagrams show the effects of setting or clearing the control bit.

CPa

Quick Switch Off (0)

CPb

CPa

Quick Switch On (1)

CPb

Figure 4 : Operation of quick switches

Page 19 of 61 SMT300Q SMT300Q User Guide V1.65

D15 D14 D13 D12 D11 D10 D9 D8

CompactP

CI-T1C3

T3C3-

T4C0

T3C2-

T4C5

T3C1-

T4C4

T2C3-

T3C0

T2C2-

T3C5

T2C1-

T3C4

D7 D6 D5 D4 D3 D2 D1 D0

T1C2-

T2C5

T1C1-

T2C4

T4C3-

T1C0

Table 5 : COM-SWITCH Register

T4C2-

T1C5

T4C1-

T1C4

T4C3-

T1C0

T4C2-

T1C5

Bit Clear (0) Set (1) Bit Clear (0) Set (1)

Not

Connected

Not

Connected

Not

Connected

Not

Connected

T4C1—T1C4

T4C2—T1C5

T4C3—T1C0

T1C4—T4C1

D10

D11

Not Connected

T1C3—T2C0

T2C1—T3C4

T2C2—T3C5

T2C3—T3C0

T1C3-

T2C0

T4C1-

T1C4

Not

Connected

Not

Connected

Not

Connected

Not

Connected

T1C5—T4C2

D12

T1C0—T4C3

D13

T1C1—T2C4 D14

T1C2—T2C5 D15

Not Connected

CompactPCI—

T1C3

T3C1—T4C4

T3C2—T4C5

T3C3—T4C0

CompactPCI—

External

Buffered

ComPort 2

7.2 Buffered ComPort

The buffered ComPorts on the front panel can be connected to ComPorts of the Tim Sites. Four of the buffered ComPorts are output only (BUF 2,4,6 and 8) and four are input only (BUF 1,3,5 and 7).

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