Sundance SMT166 User Manual
Sundance Multiprocessor Technology Limited
Product Specification
Unit / Module Description:
Unit / Module Number:
Document Issue Number:
Issue Date:
Original Author:
SMT166
User Guide
FlexTiles Development Platform
www.flextiles.eu
www.flextiles.biz
Form : QCF42
Template Date :
Dual Virtex-6 SLB Platform for embedded
solutions
SMT166 - FlexTiles Development Board
1.01
8th February 2013
Philippe Robert
10 November 2010
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2012
Product Specification SMT166 Page 1 of 44 Last Edited: 17/06/2014 16:12:00
Revision History
Issue
Changes Made
Date
Initials
1 Original Document created based on product spec. 8/2/13 GKP
1.01 Crrected sys_clock freq to 100MHz.
Added pin-out for RS232 connectors.
28/2/13 GKP
Typical installation with SLB and TIM modules attached.
Product Specification SMT166 Page 2 of 44 Last Edited: 17/06/2014 16:12:00
Table of Contents
1
Introduction .................................................................................................................... 5
2
Related Documents ........................................................................................................ 6
3
System Photograph ........................................................................................................ 7
4
Functional Description .................................................................................................. 8
5
Verification, Review and Validation Procedures ..................................................... 29
6
Safety .............................................................................................................................. 29
7
EMC ................................................................................................................................. 29
8
Timing Diagrams .......................................................................................................... 29
9
Circuit Description / Diagrams.................................................................................. 30
4.1 Block Diagram ................................................................................................................ 8
4.2 Module Description ..................................................................................................... 10
4.2.1 Connectors available on the board ..................................................................... 10
4.2.1.1 SLB connectors and cables .......................................................................... 10
4.2.1.2 TIM Site ............................................................................................................ 12
4.2.1.3 External clocks ............................................................................................... 13
4.2.1.4 PCI Express ..................................................................................................... 13
4.2.1.5 SATA 3.0 .......................................................................................................... 14
4.2.1.6 Ethernet ........................................................................................................... 14
4.2.1.7 RS232 headers ............................................................................................... 14
4.2.1.8 Power supply .................................................................................................. 15
4.2.2 FPGAs ........................................................................................................................ 16
4.2.2.1 FPGA Power supplies .................................................................................... 16
4.2.2.2 FPGA Clock structure ................................................................................... 17
4.2.2.3 FPGA Configuration ...................................................................................... 17
4.2.3 DIP Switch Settings / FPGA Configuration ....................................................... 19
4.2.4 DDR3 Memory ......................................................................................................... 21
4.2.5 On-board reset ........................................................................................................ 22
4.2.6 Clock circuitry (optional) ...................................................................................... 22
4.2.7 General purpose IOs .............................................................................................. 23
4.2.8 RS232 ......................................................................................................................... 23
4.2.9 USB ............................................................................................................................. 23
4.2.10Ethernet..................................................................................................................... 23
4.2.11SATA3.0 .................................................................................................................... 24
4.2.12RSLs to Master module ..........................................................................................
4.2.13Inter-FPGA RSL links .............................................................................................. 24
4.2.14Inter-FPGA channels ............................................................................................... 24
4.2.15LEDs ........................................................................................................................... 25
4.3 Cooling of the board ................................................................................................... 26
4.4 Data Flow Block Diagram ........................................................................................... 27
4.5 SLB IO voltages ............................................................................................................. 28
9.1 Clock circuitry: ............................................................................................................. 30
24
Product Specification SMT166 Page 3 of 44 Last Edited: 17/06/2014 16:12:00
9.2 CPLD and FPGA configuration: ................................................................................. 31
10 Layout ............................................................................................................................ 36
11 Pinout ............................................................................................................................. 37
12 Board Options ............................................................................................................... 43
13 Physical Properties ....................................................................................................... 43
14 Safety .............................................................................................................................. 44
15 EMC ................................................................................................................................. 44
Table of Figures
NOTE:
RED
9.3 DDR3 Memory: ............................................................................................................. 31
9.4 RS232: ............................................................................................................................ 32
9.5 RSL: ................................................................................................................................. 32
9.6 SLB: .................................................................................................................................. 33
9.7 SLB Aux Site: ................................................................................................................. 33
9.8 TIM Site: ......................................................................................................................... 34
9.9 USB: ................................................................................................................................. 34
9.10 Inter-FPGA Channels: .................................................................................................. 35
Figure 1 - SMT166 Block Diagram. ........................................................................................... 8
Figure 2 - SLB cable - FlexiPCB. ................................................................................................ 11
Figure 3 - SLB cable - Blue ribbon cable. ............................................................................... 11
Figure 4 - PCIe cables. ............................................................................................................... 13
Figure 5 - ATX Power connectors. .......................................................................................... 15
Figure 6 - FPGA power requirement. ...................................................................................... 16
Figure 7 - FPGA Bitstream sizes. ............................................................................................. 17
Figure 8 - Configuration Block Diagram. .............................................................................. 18
Figure 9 - Crossflow blower. .................................................................................................... 26
Figure 10 - Data Flow Diagram. ............................................................................................... 27
Figure 11 - SLB Selection ........................................................................................................... 28
Figure 12 - PCB Layout. ............................................................................................................. 36
Please pay particular attention to comments in
Product Specification SMT166 Page 4 of 44 Last Edited: 17/06/2014 16:12:00
.
1
Introduction
The SMT166 is an SLB Platform designed around two Xilinx Virtex-6 FPGAs. It can
receive up to 4 SLB mezzanine modules and one TIM or SLB base module. The
SMT166 shows a symmetrical architecture in order to suit needs for 2
systems.
Each FPGA is responsible for routing data to/from half of the SLB connections on
the board.
Connections (parallel and serial) between FPGAs are available for inter FPGA
communications.
Each FPGA is coupled with 2 banks of DDR3 memory, 32-bit wide and able to store
up to 256 Mbytes of data (per bank) at a maximum rate of 4.2 Gbytes/s.
FPGAs can be programmed using a simple Xilinx USB Programming Cable (JTAG)
whilst in the development phase. Final applications can be stored into an on-board
flash memory. There is one flash for both FPGAs in order to avoid initial conflicts
while FPGA are being programmed. The flash memory can also be accessed from a
host PC through a USB link. Equally, the flash on the master module can also be
accessed from the host though the USB (through Comport 3). A CPLD is responsible
for routing and managing accesses. Configuration selection can be made via a DIP
switch. Host accesses can be initiated by the SMT6002 software package.
Two types of cable PCIe connectors will be available on each half of the board, the
first one for a 4-lane PCI Express link and the second for a 1-lane PCI Express link.
They can be used as a link to a host system or in order to make this SMT166
platform scalable and cascade several of them, keeping the need for only one host
connection. All Express links are Gen1.
Two SATA 3.0 links and two 1Gigabit Ethernet links are available for fast transfers
to/from a remote host or an external storage unit.
SLB connectors are manufactured by Samtec. The data connector is part of the
QSH/QTH family and the power connector is part of the BKS/BKT family.
The SMT166 receives a standard 24-pin ATX power. A switch on the board is
available to turn on or off the ATX power supply used.
An optional clock synchroniser and clock distributor is available. This allows
generating clocks for SLB mezzanine modules.
n
and scalable
Product Specification SMT166 Page 5 of 44 Last Edited: 17/06/2014 16:12:00
2
Related Documents
Xilinx - Virtex-6 Families
Texas Instrument - clock distribution chip (optional)
Micron – DDR3 Memory
Samtec QSH/QTH connectors
Samtec BKS/BKT connectors
Huber-Suhner – MMCX series
Molex – PCIe x1 vertical connector:
Molex – Male-Male PCIe x1 cable:
Molex – PCIe x4 connector receptacle and housing (with key)
Molex – PCIe x4:
Sundance SLB Specifications
Sundance SMT6002 software
http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/lxt.htm
http://www.xilinx.com/products/silicon-devices/fpga/virtex-6/sxt.htm
http://focus.ti.com/docs/prod/folders/print/cdce72010.html
:
http://www.micron.com/products/ProductDetails.html?product=products/dram/ddr
3_sdram/MT41J256M8HX-15E
http://www.samtec.com/signalintegrity/final_inch/qxh_case4.aspx
http://www.samtec.com/ProductInformation/TechnicalSpecifications/Overview.aspx?
series=BKS
http://www.samtec.com/ProductInformation/TechnicalSpecifications/Overview.aspx?
series=BKT
http://www.hubersuhner.com/hs-p-rf-con-gr-series-mmcx.htm
:
:
:
:
http://www.molex.com/pdm_docs/sd/766410001_sd.pdf
http://www.molex.com/pdm_docs/sd/745760001_sd.pdf
http://www.molex.com/pdm_docs/sd/755860010_sd.pdf
http://www.molex.com/pdm_docs/sd/745400501_sd.pdf
:
http://www.molex.com/pdm_docs/sd/745460400_sd.pdf
http://www.sundance.com/login.php?file=/Docs/SLB%20-
%20Sundance%20Local%20Bus%20Specification.pdf
http://www.sundance.com/prod_info.php?board=SMT6002
:
:
Product Specification SMT166 Page 6 of 44 Last Edited: 17/06/2014 16:12:00
3
System Photograph
A typical system showing the SMT166 FPGA carrier board, four SMT943 quad ADCs, and an
SMT372T dual DSP TIM.
Product Specification SMT166 Page 7 of 44 Last Edited: 17/06/2014 16:12:00
4
Functional Description
4.1
Block Diagram
SMT166
–
SLB Carrier Board
SLB Bus
Rocket IOs
Parallel Bus
An SLB cable can be used to link the SLB on the Master module to the SLB on the SMT
166 while using RSLs.
PCIe cable connectors can be used as a link to a host PC. 4 and 1-
lane cables are available as well as Host Interface Board to communicate to a
PC
.
FPGA_0
Virtex
6
LX
130
T-
LX
365T
SX315
T
-SX
475T
PSU
Section
DDR3
Memory
Bank 2
SLB
Mezzanine 0
SLB
SLB
Mezzanine 1
SLB
SLB
Mezzanine 2
SLB
SLB
Mezzanine 3
SLB
FPGA
_1
Virtex 6
LX130T-LX365T
SX315T-SX475T
DDR3
Memory
Bank
3
DDR3
Memory
Bank 0
DDR3
Memory
Bank 1
Full
SLB
i
Full SLB
j
Full
SLB
l
Full SLB
k
RSL x2
m
RSL x
2
n
Half SLB
n
Half SLB
m
RSL x4
o
i
Channels x2
PCIe
Cable
x4
x4
l
Master
Module
SLB Connector
R
S
L
R
S
L
PCIe
Cable
x
4
x
4
j
PCIe
Cable
x1
x
1
i
PCIe
Cable
x1
x1
k
USB+
CPLD
+Flash
To configure
Virtex6
FPGAs and
access
Master
Module Flash
Clock
Synthesiser
Synchroniser
Top TIM Connector
Bottom TIM Connector
Dual
SATA3.0
x
2
q
Dual
SATA3
.0
x2
p
1Gigabit
Ethernet
1
Gigabit
Ethernet
Figure 1 - SMT166 Block Diagram.
Below is shown the block diagram of the SMT166 board:
Product Specification SMT166 Page 8 of 44 Last Edited: 17/06/2014 16:12:00
The tables below detail the SLB, RSL and Channel links:
SLB Links
i
j
k
l
m
n
RSL Links
i
lane express
j
lane express
k
lane express
l
lane express
m
n
o
Channel Links
i
bit bus (unidirectional), a clock, a
Two channels are between the FPGA0 and
Full SLB between FPGA0 and SLB site 0.
Full SLB between FPGA0 and SLB site 1.
Full SLB between FPGA1 and SLB site 2.
Full SLB between FPGA1 and SLB site 3.
Half SLB between FPGA0 and extra SLB connector.
Half SLB between FPGA1 and extra SLB connector.
Gen1 x1 express link between FPGA0 and 1connector. Also carries a reference clock and a reset.
Gen1 x4 express link between FPGA0 and 4connector. Also carries a reference clock and a reset.
Gen1 x1 express link between FPGA1 and 1connector. Also carries a reference clock and a reset.
Gen1 x4 express link between FPGA1 and 4connector. Also carries a reference clock and a reset.
x2 RSL link between FPGA0 and Master module.
x2 RSL link between FPGA1 and Master module.
x4 RSL link between FPGA0 and FPGA1.
One channel is defined as a 32write and a ready signal.
FPGA1.
Product Specification SMT166 Page 9 of 44 Last Edited: 17/06/2014 16:12:00
4.2
Module Description
4.2.1
Connectors available on the board
4.2.1.1 SLB connectors and cables
The mounting posts and securing bolts for the SLBs and TIM are at 3.3V NOT GND.
SLB sites can receive SLB mezzanine modules. Connections are made via power and
data SLB connectors (Samtec connectors).
Shown below is an example SLB module. This is the SMT909 composite video input
module.
A fifth SLB data connector is available (not coupled with a power connector). Half of
the IOs are connected to the first FPGA and the second half to the second FPGA.
They can be used as general purpose IOs or be connected to the Master Module by
using an SLB cable.
Product Specification SMT166 Page 10 of 44 Last Edited: 17/06/2014 16:12:00
Two types of cable are available: flexiPCB type and blue ribbon cable type (shown
Figure 2 - SLB cable - FlexiPCB.
Figure 3 - SLB cable - Blue ribbon cable.
below).
Product Specification SMT166 Page 11 of 44 Last Edited: 17/06/2014 16:12:00
4.2.1.2 TIM Site
A TIM site (Texas Instruments Module) is provided adjacent to the fifth SLB
connector. The positioning of these two allows a simple 1-1 cable connection from
th
the 5
SLB connector directly to the SLB connector on the TIM (where available).
Other connections from the TIM site are a ComPort connection to the USB interface,
RSL connections to both Virtex 6 FPGAs, and a JTAG connection allowing for
debugging using Code Composer Studio.
An example TIM is shown below. This is the SMT372T which has twin 6-core DSP
devices.
Product Specification SMT166 Page 12 of 44 Last Edited: 17/06/2014 16:12:00
4.2.1.3 External clocks
4.2.1.4 PCI Express
Figure 4 - PCIe cables.
One External clock and one reference are fed to the board via MMCX connectors
(Huber-Suhner). They can be used to synchronise the on-board optional clock
circuitry to an external system clock domain.
PCI Express (x1 and x4) connectors are horizontal connectors (female) and
manufactured by Molex. Connections between 2 boards or between one board and a
host can be implemented using a male-male PCI Molex cable.
FPGAs populated on the SMT166 features two PCI Express blocks, which means that
both express interfaces can be used simultaneously.
The SMT166 will receive a Gen1 PCI Express core (Endpoint with Link speed of
2.5Gbits/s and user clock of 125MHz) but has the capabilities of receiving a Gen2
version of the core (Endpoint with Link speed of 5GBits/s and user clock of
250MHz).
Typical cable examples are shown here:
The 4-lane Express core can be implemented using PCIE_X0Y1.
Product Specification SMT166 Page 13 of 44 Last Edited: 17/06/2014 16:12:00
4.2.1.5 SATA 3.0
4.2.1.6 Ethernet
4.2.1.7 RS232 headers
This 10-pin header is NOT directly compatible with a standard PC COM port.
Two SATA3.0 connectors are available per FPGA.Virtex-6 Rocket IOs have got the
ability to be configured as 3Gbit/s or 6Gbit/s SATA links.
Virtex6 rocket IOs a connected in direct, which means that the FPGA acts as a host
and can write or read to/from a connected hard disk.
Links between 2 boards would require cross-over SATA cables.
Optionally, the SMT166 can receive a 1-gigabit Ethernet connector. Xilinx has made
available a 1-gigabit Ethernet core that can be implemented in a Virtex6 and using a
TEMAC block. A purchased license might be required in order to get full capabilities
of the core.
The RS232 will have simple 2mm header. A custom made cable is required for
connection to a host machine as each header contains 4 transmit and 4 receive
signals.
Product Specification SMT166 Page 14 of 44 Last Edited: 17/06/2014 16:12:00
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