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SMT148FX
User Manual
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Sundance SMT148FX User Manual

Sundance Multiprocessor Technology Limited
User Manual
Form : QCF42 Date : 6 July 2006
Unit / Module Description: Unit / Module Number: Document Issue Number: Issue Date: Original Author:
User Manual
SMT148FX
DC and ATX versions
1.4
3/8/09
GKP
for
Sundance Multiprocessor Technology Ltd, Chiltern House,
Waterside, Chesham, Bucks. HP5 1PS.
This document is the property of Sundance and may not be copied
nor communicated to a third party without prior written
permission.
© Sundance Multiprocessor Technology Limited 2006
User Manual SMT148FX Page 1 of 48 Last Edited: 03/08/2009 11:42:00
Revision History
Issue Changes Made Date Initials
1.0 First release 4/6/07 GKP
1.1 Minor updates 2/7/07 GKP
1.2 Update LVDS FPGA connectivity. 20/8/07 GKP
1.2.1 Added LVDS buffer drawing. 20/8/07 GKP
1.3 Differentiated DC and ATX versions. 13/6/08 GKP
1.3.1 Corrected LVDs connector pin-out tables.
Added additional detail about IL715 isolators.
1.3.2 Added connector info for RS485. 19/8/08 GKP
1.4 Spartan firmware explanation 3/8/09 FS
Important comments or cautions are displayed next to this symbol.
3/7/08 GKP
User Manual SMT148FX Page 2 of 48 Last Edited: 03/08/2009 11:42:00
Table of Contents
1 Introduction..................................................................................................................... 5
2 Related Documents........................................................................................................ 6
2.1 Referenced Documents.............................................................................................. 6
3 Acronyms, Abbreviations and Definitions.............................................................. 6
3.1 Acronyms and Abbreviations................................................................................... 6
4 Functional Description.................................................................................................. 7
4.1 Block Diagram.............................................................................................................. 7
4.1.1 Virtex 4 FX ............................................................................................................... 8
4.1.2 Spartan 3.................................................................................................................. 8
4.1.3 TIM Sites................................................................................................................... 8
4.1.4 10/100/1000 Ethernet Phy................................................................................... 8
4.1.5 LVDS Isolators......................................................................................................... 9
4.1.6 Firewire................................................................................................................... 12
4.1.7 USB2........................................................................................................................ 12
4.1.8 RS232...................................................................................................................... 14
4.1.9 Flash........................................................................................................................ 14
4.1.10 RS485...................................................................................................................... 15
4.1.11 SHB.......................................................................................................................... 15
4.1.12 LEDs ........................................................................................................................ 15
4.1.13 ZBT Memory .......................................................................................................... 15
4.1.14 RSL .......................................................................................................................... 16
4.1.15 External ComPorts ............................................................................................... 17
4.1.16 Internal ComPorts................................................................................................ 19
4.1.17 Power input (DC version).................................................................................... 20
4.1.18 Power input (ATX version).................................................................................. 21
4.1.19 Power output......................................................................................................... 22
4.1.20 JTAG........................................................................................................................ 22
4.1.21 Local Clock for ADCs etc. ................................................................................... 23
4.1.22 Fan Power............................................................................................................... 23
4.1.23 Reset Scheme ........................................................................................................ 23
4.1.24 External FPGA Clock Input ................................................................................. 24
4.1.25 FPGA (Virtex4 and Spartan) configuration...................................................... 24
5 Jumper Position/Function..........................................................................................25
6 Footprint.........................................................................................................................26
6.1 Top View..................................................................................................................... 26
User Manual SMT148FX Page 3 of 48 Last Edited: 03/08/2009 11:42:00
6.2 Bottom View............................................................................................................... 27
7 Virtex4 FPGA Pin Allocation......................................................................................28
8 Virtex4 FPGA Bank Allocation ..................................................................................29
9 Programming the Cpld................................................................................................31
10 Application to program the Flash ............................................................................32
10.1 Connections provided on the SMT148FX ............................................................. 32
11 Accessing the Flash......................................................................................................33
11.1 Programming the Spartan ....................................................................................... 33
11.2 Erase and Program of the Flash ............................................................................. 33
11.3 Booting the Spartan and Virtex 4 from flash ...................................................... 34
12 Firmware for the Spartan. ..........................................................................................34
12.1 Hardwired comport connections ........................................................................... 36
13 RSL and Comport connections..................................................................................37
13.1 RSL connections ........................................................................................................ 37
13.2 Comport connections............................................................................................... 39
14 Spartan firmware explanation................................................................................... 42
15 DIP Switches ..................................................................................................................45
16 Support Packages .........................................................................................................46
17 Physical Properties.......................................................................................................46
18 Thermal Management..................................................................................................47
19 Safety...............................................................................................................................48
20 EMC ..................................................................................................................................48
21 Ordering Information..................................................................................................48
User Manual SMT148FX Page 4 of 48 Last Edited: 03/08/2009 11:42:00

1 Introduction

The SMT148FX is a four site stand-alone TIM carrier board with several external interfaces.
Connectors are provided to interface to:
• RS232 – From FPGA or USB controller
• LVDS (48 pairs)
• JTAG
• RSL
• SATA – Connectors carrying RSL signals only.
• SHB
• RS485 (16 pairs)
• USB2
• Firewire (1394) interface only (No IP core).
• Ethernet 10/100/1000
• LED (x32)
• ZBT memory
• Local clock buffer/generator output
User Manual SMT148FX Page 5 of 48 Last Edited: 03/08/2009 11:42:00
Sundance Multiprocessor Technology Limited
User Manual
Form : QCF42 Date : 6 July 2006

2 Related Documents

2.1 Referenced Documents

Sundance SLB specification (hyperlink).
Sundance RSL specification (hyperlink).
Datasheets as specified above.
Texas Instruments Module specification.
SMT118: Carrier with 3 Module sites and I/O facilities.
SMT180: Carrier with 8 Module sites.

3 Acronyms, Abbreviations an d Definitions

3.1 Acronyms and Abbreviations

A list of acronyms etc (hyperlink).
User Manual SMT148FX Page 6 of 48 Last Edited: 03/08/2009 11:42:00

4 Functional Description

4.1 Block Diagram

Flash
memory
CPLD
USB2
FPGA configuration control
JTAG
x4
TIM sites
x4
TIM sites
x4
TIM sites
x4
TIM sites
16x
ComPorts
5x
FPGA
Select map port
Spartan 3
ComPort switch
JTAGJTAG
ComPorts
External ComPort
via SHB connectors
External ComPorts x4
via 26-way 3m header
3x
ComPorts
Global Bus
Select map port
RS232
USB
connector
connector
JTAG
header
Firewire
connector
RJ45
ZBT
memory
x32
LEDs
PHY
IEEE1394
FPGA
1.2V core
FF1152 package
Virtex4 XC4VFX60
PHY
Ethernet
2x 2Mx18
2x 16-bit
SHB
8x 6-bit
16-bit
SHB
connector
LVDS connectors x4
RS485
connector
4 lanes
SATA
connectors
x4
4 lanes
RSL
connector
User Manual SMT148FX Page 7 of 48 Last Edited: 03/08/2009 11:42:00

4.1.1 Virtex 4 FX

The primary controlling device on the 148FX is the Xilinx Virtex4 FX60 FPGA. This device is an FF1152 package which provides 16 MGTs (high speed serial I/O) and 576 normal I/O signals.
This device can be configured via a Xilinx compatible JTAG header.
In normal operation, this device is configured by the CPLD (XC2C512). The configuration data is stored in flash memory, and is loaded using slave SelectMAP mode (8-bit parallel).

4.1.2 Spartan 3

The Xilinx Spartan 3 device is similar in nature to that employed on the SMT150Q and SMT329 carrier boards. It acts as a pre-configured ComPort routing switch.
Different ComPort routing schemes are easy to implement using supplied tools (requires Xilinx ISE development software).
This device is also configured by the CPLD, and uses slave SelectMAP mode (8-bit parallel), but is also part of the Xilinx JTAG chain.

4.1.3 TIM Sites

The 148FX provides 4 TIM sites. In addition to the standard specification requirements, the 148FX also provides the 3.3V supply to the two TIM mounting holes.
Each TIM site has 4 ComPorts connected directly to the Spartan 3 device. The two remaining ComPorts are used to create a simple pipe, with each site connecting to its nearest neighbours.
The TIM site’s interrupt, timer, config, and reset pins are all connected to the Virtex 4 FPGA. The reset signals are asserted during power-up, when pressing the on-board reset button, or when signalled to via one of the external ComPort connectors.
A global bus connection (16 bit data, 12 bit address) is also made from each site to the Virtex 4. The global bus connector normally contains one 16-bit SDB interface (this is unlike the TIM specification which describes the global bus as an Address/Data structure). These SDBs are the primary method of communication to the resources shared by the Virtex 4 (eg. USB, Firewire, etc).

4.1.4 10/100/1000 Ethernet Phy

A Marvell Ethernet PHY connects directly to the Virtex 4 FPGA. This interfaces to a 10/100/1000 network via a standard RJ45 socket. This socket has built-in magnetics.
The PHY is controlled by a MAC within the Virtex 4.
An Ethernet IP core is not supplied in the standard firmware. Please contact Sundance for further information.
User Manual SMT148FX Page 8 of 48 Last Edited: 03/08/2009 11:42:00

4.1.5 LVDS Isolators

48 single ended signals are connected from the Virtex 4 to LVDS drivers and receivers (SN65LVDS390/1) via galvanic isolators (type IL715-3). The transmitter part is enabled via control signals. The LVDS outputs are arranged in groups of 6., hence there are 8 control signals. The LVDS receivers are enabled continuously.
The isolation provided is up to 150V rms maximum.
The isolation provided is up to 150V rms, whilst still enabling a baud rate of up to 100Mbps.
The LVDS transmitters and receivers are external to the FPGA itself. The devices used are SN65LVDS390 and 391.
LVTTL input from
FPGA
Output Enable
(goes to 3 drivers)
LVTTL input from
FPGA
LVTTL output to
FPGA
LVDS driver
LVDS receiver
100 Ohm
termination
resistor
TX+
Differential output
to D-connector
TX-
RX+
Differential input
from D-connector
RX-
The IL715-3 galvanic isolators require a simple initialisation sequence before use. Simply toggle the driving pins from the FPGA to the IL715-3 devices at start-up.
User Manual SMT148FX Page 9 of 48 Last Edited: 03/08/2009 11:42:00
Typically. The TIMs are configured to route their McBSPs to the global bus connector pins, which, in turn, are routed to the LVDS I/O. The following table shows the pin­out for the 37-way D-type connectors. This is only applicable if the TIM is using non­standard firmware which routes McBSP signals onto the global bus. Contact Sundance for further information.
1 GND
2 McBSP_CLKR_Tx_0+
3 McBSP_FSR_Tx_0+
4 McBSP_DR_Tx_0+
5 GND
6 McBSP_CLKX_Tx_0+
7 McBSP_FSX_Tx_0+
8 McBSP_DX_Tx_0+
9 GND
10 GND
11 GND
12 McBSP_CLKR_Tx_1-
13 McBSP_FSR_Tx_1-
14 McBSP_DR_Tx_1-
15 GND
16 McBSP_CLKX_Tx_1-
17 McBSP_FSX_Tx_1-
18 McBSP_DX_Tx_1-
19 GND
Input/Output
I
I
I
O
O
O
I
I
I
O
O
O
20 GND
21 McBSP_CLKR_Tx_0-
22 McBSP_FSR_Tx_0-
23 McBSP_DR_Tx_0-
24 GND
25 McBSP_CLKX_Tx_0-
26 McBSP_FSX_Tx_0-
27 McBSP_DX_Tx_0-
28 GND
29 GND
30 McBSP_CLKR_Tx_1+
31 McBSP_FSR_Tx_1+
32 McBSP_DR_Tx_1+
33 GND
34 McBSP_CLKX_Tx_1+
35 McBSP_FSX_Tx_1+
36 McBSP_DX_Tx_1+
37 GND
User Manual SMT148FX Page 10 of 48 Last Edited: 03/08/2009 11:42:00
As the LVDS drivers are connected directly to the FX60 FPGA, they can be driven from this device without need for the above McBSP method. The following table shows the connectivity between the FPGA and the D-connectors (P2, 3, 4 & 5):
FPGA
signal pin
P2 P3 P4 P5
Signal D-
Conn
Pin
D-
Conn
Pin
Signal
FPGA
enable pin
P2 P3 P4 P5
GND 1 20 GND
D29 K29 M26 P31 RX0+ 2 21 RX0-
F31 C32 L30 P26 RX1+ 3 22 RX1-
E32 D32 L31 P27 RX2+ 4 23 RX2-
GND 5 24 GND
D31 E29 K31 M31 TX0+ 6 25 TX0-
E31 F29 K32 M32 TX1+ 7 26 TX1- H27 J30 H32 N32
C29 J29 M25 P30 TX2+ 8 27 TX2-
GND 9 28 GND
GND 10
GND 11 29 GND
C30 L28 M28 P29 RX3- 12 30 RX3+
D30 L29 N27 R29 RX4- 13 31 RX4+
G31 H29 M30 R27 RX5- 14 32 RX5+
GND 15 33 GND
H28 J31 J32 P32 TX3- 16 34 TX3+
F30 J27 N28 R31 TX4- 17 35 TX4+ G32 H30 N30 R28
G30 K28 N29 R32 TX5- 18 36 TX5+
GND 19 37 GND
The LVDS transmitters are enabled in groups. Two groups per D-connector.
Eg. FPGA pin J30 is the transmitter enable for connector P3’s TX pins.
The LVDS receivers are continuously enabled and terminated by a 100 Ohm resistor.
User Manual SMT148FX Page 11 of 48 Last Edited: 03/08/2009 11:42:00

4.1.6 Firewire

A single IEEE1394 interface is provided by an Agere FW801A PHY. The following table shows the pinout of the connector;
1 Cable Power
2 GND
3 TPB-
4 TPB+
5 TPA-
6 TPA+
This will allow high speed firewire data to be routed directly to the FPGA.
The standard FPGA firmware does not include an IEEE1394 IP core. These are available from 3 information.
rd
parties. Please contact Sundance for further

4.1.7 USB2

The USB2 interface is provided by the Cypress CY7C68013A device.
The Cypress part, in addition to providing USB functions with a FIFO type interface, also contains a USART, and an 8051 micro-controller.
The USB connector pin-out is shown here;
1 USB_ind
2 Data-
3 Data+
4 GND
The interface provided by this controller looks identical to a 16-bit SDB interface, and is routed directly to the Spartan FPGA and the CPLD.
The standard Cypress firmware does not include functions to control the USART. Please contact Sundance for further information.
The following table shows the Cypress pin connectivity to the Sundance SDB signal;
User Manual SMT148FX Page 12 of 48 Last Edited: 03/08/2009 11:42:00
SDB Signal Cypress Pin
CLK IFCLK
D0 PB0
D1 PB1
D2 PB2
D3 PB3
D4 PB4
D5 PB5
D6 PB6
D7 PB7
D8 PD0
D9 PD1
D10 PD2
D11 PD3
D12 PD4
D13 PD5
D14 PD6
D15 PD7
WEN RDY0
REQ CTL2
ACK RDY1
UD0 PA7
UD1 RDY3
User Manual SMT148FX Page 13 of 48 Last Edited: 03/08/2009 11:42:00

4.1.8 RS232

Two devices generate RS232 data (simple TX and RX); the FPGA and the USB2 controller.
The Rx data pin from a 9-way D-type connector is connected to both serial interfaces. The Tx data pin from each device is routed to a jumper block (JP12) which allows the selection of one Tx data output. The RS232 levels are generated using a MAX3227 converter.
1
2 Rx
3 Tx
4
5 GND
6
7
8
9
Insert only one jumper in positions shown in section 7.

4.1.9 Flash

The flash memory connected to the CPLD and contains configuration data for the two FPGAs.
Any additional space within this device can be used to store application programs.
The flash can be directly programmed by the CPLD only.
The external ComPort is directly connected to the CPLD. This allows the reprogramming of the flash using an identical procedure as that employed on the SMT348. After configuration, the CPLD ComPort is tri-stated and the external ComPort functions as an input to the ComPort switch (Spartan 3).
User Manual SMT148FX Page 14 of 48 Last Edited: 03/08/2009 11:42:00

4.1.10 RS485

Each of the 16 RS485 signal pairs is driven by an SN75HVD12. They are arranged into two groups of 8-bits each and have a single control signal which selects the group to be a transmitter or receiver.
Connector RS1 carries these signals.
Function pin pin Function S0- 1 2 S0+ S1- 3 4 S1+ S2- 5 6 S2+ S3- 7 8 S3+ S4- 9 10 S4+ S5- 11 12 S5+ S6- 13 14 S6+ S7- 15 16 S7+ GND 17 18 GND GND 19 20 GND
Function pin pin Function GND 21 22 GND GND 23 24 GND S8- 25 26 S8+ S9- 27 28 S9+ S10- 29 30 S10+ S11- 31 32 S11+ S12- 33 34 S12+ S13- 35 36 S13+ S14- 37 38 S14+ S15- 39 40 S15+

4.1.11 SHB

A single SHB connector (Samtec QSH-030-01) provides two independent 16-bit SDBs, or a single 32-bit SDB interface. These signals are connected directly to the FX60.

4.1.12 LEDs

32 LEDs are connected to the Virtex 4 FPGA in a matrix of 8x4.

4.1.13 ZBT Memory

Two 16-bit wide ZBT memories are connected directly to the FPGA. This provides a memory bank of 2Mx16 bits (4Mbytes).
The standard FPGA firmware does not include functions to control the ZBTRAM. VHDL test code is available. Please contact Sundance for further information.
User Manual SMT148FX Page 15 of 48 Last Edited: 03/08/2009 11:42:00
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