Sundance SMT130 User Manual v.1.0

SMT130

User Manual V1.0

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

Page 2 of 46 SMT130 User Manual V1.0

Revision History

Date Comments Engineer Version

24/05/04 Initial SMT130 Draft TJW 1.0

Page 3 of 46 SMT130 User Manual V1.0

Table of Contents

1 Introduction ..................................................................................................................................... 8

2 Functional Description .................................................................................................................... 9

3 Setting Up the SMT130................................................................................................................. 10

4 Memory Map................................................................................................................................. 11

4.1 PCI Bridge Chip Internal Register (BAR0)...........................................................................11

4.2 I/O Space Register Assignments (BAR1) ............................................................................ 11

4.3 Memory Space Assignments(BAR2).................................................................................... 12

5 DSP Resource Memory Map........................................................................................................13

6 Shared Memory Resource............................................................................................................ 14

7 Comports....................................................................................................................................... 15

8 Comport to PCI Interface.............................................................................................................. 16

8.1 Comport Registers (Offset 0x10, BAR1).............................................................................. 16

8.2 Control Register (Offset 0x14, BAR1).................................................................................. 16

8.3 Status Register (Offset 0x14, BAR1 , Read-Only)............................................................... 17

8.4 Interrupt Control Register (Offset 0x18, BAR1) ................................................................... 18

9 JTAG Controller ............................................................................................................................ 20

10 Using the SMT130 External/Internal JTAG with TI Tools............................................................. 22

11 Firmware Upgrades ...................................................................................................................... 23

12 Global/Local Bus Transfers, DSP <-> PCI................................................................................... 25

12.1 Mailbox Accesses................................................................................................................. 25

12.1.1 Doorbell Interrupts....................................................................................................... 26

12.2 DSP Interrupt Control...........................................................................................................26

12.3 DSP To Local Aperture 0 control and Accessing................................................................. 27

12.3.1 Global bus access protocol ......................................................................................... 29

13 Interrupts....................................................................................................................................... 32

13.1 SMT130-To-PCI Interrupts................................................................................................... 32

13.2 PCI-To-SMT130 Interrupts................................................................................................... 33

13.3 Interrupt Registers................................................................................................................ 33

13.3.1 PCI Interrupt Configuration Register(Offset 0x4C, BAR0) .......................................... 33

13.3.2 PCI Interrupt Status Register(Offset 0x48, BAR0)...................................................... 35

13.3.3 Local Bus Interrupt Mask Register(Offset 0x77, BAR0).............................................. 36

13.3.4 Local Bus Interrupt Status Register(Offset 0x76, BAR0) ............................................ 37

13.3.5 PCI Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD0, BAR0 Read

0xD2, BAR0)................................................................................................................................. 37

13.3.6 Local Bus Mailbox WRITE/READ Interrupt Control Register(Offset: Write 0xD4, BAR0

Read 0xD6, BAR0) ....................................................................................................................... 38

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13.3.7 Mailbox Write/Read Interrupt Status Register(Offset: Write 0xD8, BAR0 Read 0xDA, BAR0) 39

13.3.8 INTREG Register(Offset 0x40, BAR1)........................................................................ 39

13.4 Example ............................................................................................................................... 40

14 Stand-alone mode......................................................................................................................... 42

15 Performance Figures .................................................................................................................... 43

16 Mechanical Dimensions................................................................................................................ 44

17 Power consumption ...................................................................................................................... 44

18 Cables and Connectors ................................................................................................................ 45

18.1 Comports..............................................................................................................................45

19 Where’s that Jumper?...................................................................................................................46

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Table of Tables

Table 1 : Table of Abbreviations..................................................................................7

Table 2 : I/O address space map...............................................................................11

Table 3 : Memory space map....................................................................................12

Table 4 : Memory space map....................................................................................13

Table 5 : Comport connector reference.....................................................................15

Table 6 : Control Register..........................................................................................16

Table 7 : Status Register...........................................................................................18

Table 8 : Interrupt Control Register............................................................................19

Table 9 : JTAG Header pin function...........................................................................24

Table 10 : PCI Interrupt Configuration Register.........................................................35

Table 11 : PCI Interrupt Status Register....................................................................36

Table 12 : Local Bus Interrupt Mask Register...........................................................37

Table 13 : Local Bus Interrupt Status Register..........................................................37

Table 14 : PCI Mailbox WRITE/READ Interrupt Control Register..............................38

Table 15 : Local Bus Mailbox WRITE/READ Interrupt Control Register....................38

Table 16 : Mailbox Write/Read Interrupt Status Register...........................................39

Table 17 : INTREG Register......................................................................................40

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Table of Figures

Figure 1 : TBC Data Routing .....................................................................................20

Figure 2 : JTAG header pin numbers.........................................................................23

Figure 3 : Local Bus to DSP Connectivity..................................................................25

Figure 4 : DSP Transfer via the Local Aperture 0......................................................28

Figure 5 : Timing diagram for DSP local bus access.................................................30

Figure 6 : SMT130 to PCI Interrupts..........................................................................32

Figure 7 : PCI to SMT130 Interrupts..........................................................................33

Figure 8 : Jumper Finder Diagram.............................................................................46

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Table Of Abbreviations

BAR Base Address Region

DMA Direct Memory Access

EPLD Electrically Programmable Logic Device

PCI Peripheral Component Interconnect

SDB Sundance Digital Bus

SRAM Static Random Access Memory

TBC Test Bus Controller

TIM Texas Instruments Module

Table 1 : Table of Abbreviations

1 Introduction

The SMT130 is a single site module carrier board that provides access to a single TIM module over the PCI bus in a PCI-104 stack system.

An on-board JTAG controller allows systems to be debugged using Code Composer Studio. There is also a JTAG input and JTAG output connector on the SMT130. This allows the debugging of all the TIM modules in the PCI-104 stack from a single JTAG controller.

The main connection to the PCI bus is via the module Global Bus. A single Comport is also mapped to the PCI bus providing support for application boot and data transfer.

A 1 MB of SRAM is mapped on to the Global Bus and can be accessed by the TIM as a global resource or by the PCI Bridge.

A through board header is provided for RESET_IN and RESET_OUT to allow multiple SMT130 carriers in a stack to be synchronised.

The board requires a 5 volt supply only, which is taken from the PCI-104 stack connector or an auxiliary power connector from stand alone applications. The 3.3 volt supply required for supplying power to the TIM module is generated locally.

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

2 Functional Description

The PCI interface connects to a Quick Logic EPC363 Bridge device. It has a 32-bit 33MHz PCI interface that supports I

C control, mailbox register access and direct memory reads and writes. The PCI bus is translated to a Local PCI bus, which is connected to the following devices:

• Shared SRAM 1MB

• Control EPLD that manages Comport access

• JTAG controller

• Module Global Bus

• PCI Bridge device

An on-board arbitration unit controls which device, Master Module or PCI Bridge, has access to this local PCI bus resource.

The local PCI bus has a 33MHz clock to control transfers between the various resources. This is available on the CLKIN pin on the Master site and should be selected in preference to the on-board oscillator to allow the DSP to synchronise its accesses to and from the PCI Bridge registers. The PCI Bridge has an input and output FIFO capable of transferring 256 32-bit words of data to and from the DSP at 33MHz, thus bursting a maximum local bus transfer rate of 132MB/s.

The TIM Module can access the SRAM over the PCI local bus at transfer rates up to 100MB/s. The number of wait states required by the Master Module will vary depending on the speed of the module. Maximum access rates use a 20ns strobe cycle.

The JTAG controller is based on the TI 8990 device, and drivers can be supplied for Code Composer Studio (Part Number

SMT6012).

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

3 Setting Up the SMT130

The SMT130 should be set up in the following way.

• Turn the system off and add the SMT130 (With TIM already installed) to the PCI-

104 stack. Take care to ensure that all stacking connector pins locate correctly. Secure the SMT130 in the stack with the pillars and screws provided. Adjust rotary switch SW1 to ensure that the SMT130 has a unique stack position. No two cards in the PCI-104 stack must have the same setting. Note only positions 0 to 3 are valid.

• Switch on PC and wait for the OS to boot up.

• Windows 95/98/NT/2000 will detect a new hardware.

• Windows should automatically find the drivers from the CD, if not browse to the

CD or if you downloaded from the ftp site to the folder where you unzipped the SMT6300 software.

• 3L application software will detect the SMT130 if the SET TISLINK variable is set

to SMT320.

• You can run the SMTBoardInfo application to detect the number of SMT130s in

your system and report their stack positions and I/O addresses. This information is required when setting up code composer for the board. SMTBoardInfo is part of the SMT6300 package.

User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

4 Memory Map

All address information is given in bytes :

4.1 PCI Bridge Chip Internal Register (BAR0)

Please see V363EPC Local Bus PCI Bridge User Manual V1.04 (

http://www.quicklogic.com/home.asp?PageID=223&sMenuID=114#Docs) for details

of internal registers. Note: Where required, registers from the V

4.2 I/O Space Register Assignments (BAR1)

In target mode, the SMT130 is accessed by a host device across the PCI bus. This allows access to the target mode registers. The operating system or BIOS will normally allocate a base address for the target mode registers of each SMT130. Access to each register within the SMT130 is then specified by this base address and the offset shown in the table below.

datasheet have been included.

The I/O address space is decoded as shown in the table below.

Offset Register(Write) Register(Read) Width

0x0 - - 0x4 - - 0x8 - -

0x0C - -

0x10 COMPORT_OUT COMPORT_IN 32 0x14 CONTROL STATUS 32 0x18 INT_CONTROL 32

0x1C - -

0x20 to 0x3F COMPORT Configuration COMPORT Configuration

0x24 COM_SWITCH COM_SWITCH 16 0x40 INTREG INTREG 16

0x80 to 0xAF TBC Write TBC Read 16

Table 2 : I/O address space map

4.3 Memory Space Assignments(BAR2)

Address Description Notes

0x0000 0000 – 0x000F FFFF Shared Memory Bank 1MB SRAM

0x00200090

0x00200094

0x00200098

0x0020 0000-0x0020 007F Global Bus See Note 1 0x0020 0240 – 0x0020 025F SDB Data Register Input/Output 16 bit SDB Interface 0x0020 0260 – 0x0020 027F SDB Control Register SDB Control/Status

Comport Data

Mirror

Comport Status

Mirror

Comport Int_Control

Mirror

Table 3 : Memory space map

Mirror of COMPORT_OUT /

COMPORT_IN in

I/O Space

(BAR1)

See Note 2

Mirror of Control / Status in I/O

Space Register

Assignments (BAR1)

See Note 2

Mirror of Int_Control in I/O

Space Register

Assignments (BAR1)

See Note 2

Note 1: In order for the TIM to respond to accesses for this area address line GADD30 and GADD19 of the TIM site connector must be decoded as high and GADD7 and GADD5 must be decoded as low.

Note 2: These mirrors of Addresses in the I/O Space (BAR1) allow increased transfer speeds across the host Comport link (in excess of 10X increase).

5 DSP Resource Memory Map

The Master module on the SMT130 can access the various resources available, including the Shared SRAM and the PCI Bridge. Access to the PCI Bridge allows the DMA engine in the PCI Bridge to be initiated by the DSP, mailbox registers can also be manipulated. The table below illustrates the resources and their corresponding address region when accessed by the Master module.

C60 Address Access Description Notes

0xD000 0000 – 0xD00F FFFF Shared Memory Bank 1Mbyte SRAM

0x1C00 0000 – 0x1C00 00FF PCI Bridge Registers PCI Bridge Internal resisters

0x1800 0000 – 0x183F FFFF Local-to-PCI Aperture 0 PCI Bridge Aperture 0 Space

Table 4 : Memory space map

6 Shared Memory Resource

There is 1Mbyte of SRAM on the SMT130, this shared memory can be accessed by the PCI host and the TIM module. This allows applications to transfer data between the host PC and the DSP at data rates approaching 100MB/s. The address of the shared memory is shown in the memory map.

The PCI Bridge DMA processor sees the shared memory at a different address from that used for normal accesses. For normal memory access the memory base address register offset is 0x0000 0000. For DMA access address line A28 (On hardware interface) must be high, therefore DMA memory access starts at 0x4000 0000 (Not 0x1000 0000 as addressing is in bytes).

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Sundance SMT130 User Manual v.1.0

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