Sundance SMT128 User Manual
Preliminary
SMT128
User Manual
Preliminary Page 2 of 15 SMT128 User Manual
Revision History
Date Comments Engineer Version
13/6/00 Initial version AJP 1.0 05/9/00 Second Revision AJP 1.1 07/01/02 Modifications AJP 1.2 26/02/02 Several Modifications Made BM 1.3
Preliminary Page 3 of 15 SMT128 User Manual
Table of Contents
Revision History.......................................................................................................... 2
Table of Contents....................................................................................................... 3
Introduction................................................................................................................. 4
Functional Block Diagram ........................................................................................... 5
Memory Map............................................................................................................... 6
Virtex Registers.......................................................................................................... 6
WDOG RST............................................................................................................ 6
WDOG ENABLE..................................................................................................... 6
DIGIN Register........................................................................................................ 7
DIGOUT Register.................................................................................................... 7
VSTATUS Register................................................................................................. 7
VCNTRL Register................................................................................................... 8
FLASH Memory.......................................................................................................... 9
EEPROM.................................................................................................................... 9
UART.......................................................................................................................... 9
Com Port Control...................................................................................................... 10
Token Reset Control Registers............................................................................. 10
Token Reset Software Functions and Method...................................................... 10
J21,J24 – Virtext boot mode ................................................................................. 11
J21,J24 – Virtext boot mode ................................................................................. 12
J30 – Flash Write Protect...................................................................................... 12
J27,J28 – Com CPLD User I/O............................................................................. 12
DIN Connector Pinout............................................................................................... 13
DIN PL1 ................................................................................................................ 13
DIN PL2 ................................................................................................................ 14
Preliminary Page 4 of 15 SMT128 User Manual
Introduction
The SMT128 is a 3 site TIM carrier card with additional customised features, acting
as a supports environment for a DSP TIM and two other peripheral TIM’s. The
various ‘on-board’ peripherals available on the motherboard are listed below.
• TIM Site 1: Standard Single width TIM site capable of accepting any TIM
compatible card. For the most embedded projects this can be a DSP processing
card. It has full COMM-PORT and Global Expansion Bus interconnectivity. The
site is also capable of accepting C6x based DSP although only four com-ports are
available. These com-ports are routed to the PL2 DIN connector for inter-module
communication via com-ports (0,1,3,4) via a buffer CPLD.
• TIM Site 2: Standard Single Width TIM site with additional 26 way and 24 way
IDC sockets, see mechanical/electrical information. This is designed to accept
the SMT397 12 channel differential ADC/DAC TIM although other peripheral
TIM’s can be used.
• TIM Site 3: Standard Single Width TIM site with two additional 24 way IDC
sockets, see mechanical/electrical information. This is designed to accept the
SMT392 4 channel RS422 Transceiver/Digital IO TIM although other peripheral
TIM’s can be used..
• Motherboard Resources/Peripherals
• Power Supplies 3.3V, 5V +-15v all generated.
• Control FPGA
• Digital Inputs/Outputs
• Power Monitor & Watchdog
• 8K bytes of EEprom that can be used to store application parameters.
• JTAG Port
• 4Mbit FLASH ram for application Software
• Quad UART with links to the DIN connectors and also one to an RS232
connector.
The Motherboard has 2 DIN4162 connectors placed at the back of the board which
conform with the VME mechanical specifications. The Pin-out out the connectors is
given later in this specification. Four of the DSP com-ports are available on the back
panel connectors to allow multiple boards to communicate with each other. Each
com-port has a control circuitry to allow motherboard in a system to be ‘hot
swappable’.
Preliminary Page 5 of 15 SMT128 User Manual
Functional Block Diagram
Digital signal
connections to
PL1 & PL2
Global Resource Bus
Front Panel JTAG
DSP TIM Site
DSP Comm-Port PAU
0 1 3 4
RS422 TIM
Site
DSP & PSU
Watchdog
24 TTL I/O’s
Controller FPGA
Spartan XC2S100 FG256
Analogue
TIM Site
Analogue
connections
to PL1
Eprom
14 TTL I/O’s
4Mbyte
FLASH
RAM
Power
Supplys
Digital signal
connections to
PL2
Digital signal
connections to
PL1
PL2 DIN41612
Back-Panel
Connector
Front Panel Maintenance Port (RS232)
Quad
UART
Key Switch
Virtex to PL1
connections
PL1 DIN41612
Back-Panel
Connector
Loading...