Sundance SMT118 User Manual
SMT118
User Manual
Version 1.0 Page 2 of 20 SMT118v2 User Manual
Revision History
Date Comments Engineer Version
22/7/03 First release GP 1.0
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Table of Contents
Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Block Diagram ............................................................................................................ 4
Power Supply ............................................................................................................. 5
TIM sites..................................................................................................................... 6
JTAG....................................................................................................................... 6
Global Bus .............................................................................................................. 6
CPU ........................................................................................................................ 6
I/O ........................................................................................................................... 6
Comm-ports ............................................................................................................ 7
Reset .......................................................................................................................... 7
Flash...........................................................................................................................8
TTL .............................................................................................................................8
QUART....................................................................................................................... 9
Interrupts .................................................................................................................. 10
Memory Map............................................................................................................. 12
Board Size ................................................................................................................ 12
Connector Pin-Outs .................................................................................................. 13
CONN2 - DAC....................................................................................................... 13
CONN8 - RESET .................................................................................................. 13
CONN3 – TTL I/O ................................................................................................. 14
CONN4-7 – RS232 ............................................................................................... 14
CONN9 - JTAG ..................................................................................................... 15
Connector Position ................................................................................................... 16
How To ..................................................................................................................... 17
Write to flash ......................................................................................................... 17
Read / Write to RS232 .......................................................................................... 18
Safety ....................................................................................................................... 20
EMC ......................................................................................................................... 20
Physical Properties................................................................................................... 20
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Block Diagram
From the block diagram it can be seen that this is a three slot TIM carrier with a CPU
site, two I/O sites and various types of I/O.
Each of the sections will be described in detail below.
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Power Supply
Power is supplied to the SMT118 via the 4 pin connector HDR9 (referring to
connector position section, HDR9 is located at the top right of the drawing). A
minimum current of 200mA is required by the circuitry of the SMT118. The maximum
current will be dependant on other TIMs mounted on the SMT118.
The on-board supplies are generated by custom designed industry standard pincompatible 2” x 1” DC-DC converters. The 12V module is based around the
2186 device and includes an input voltage regulator to allow a maximum of an 18V
input. The 5 and 3.3V supplies are based around the
Micrel 2182
device and these
allow an input range from Vout+1.5 to 30V. The individual supplies are rated as
follows:
Micrel
Voltage rail
(Volts)
Minimum input
(Volts)
Max current delivery
(Amps)
3.3 4.5 5
5.0 6.5 5
12.0 7.0 1
These values imply a minimum board supply of 7.0V. The maximum input is 18.0V.
Note that a –12V supply is not provided as standard, but an option is available to use
a dual output 12 or 15 volt DC-DC converter which will be able to supply both positive
and negative supplies to the TIM sites. When this option is installed the board supply
voltage must be greater than 10V.
Individual LEDs are illuminated when each of the DC-DC converters becomes active.
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TIM sites
The SMT118 has three TIM sites. Only the primary or CPU site can be considered to
be 100% TIM standard compliant. The two I/O sites are compliant with the exception
of the optional global bus connector.
JTAG
The JTAG chain includes all three TIM sites with the proviso that there must always
be a CPU module in SITE 1.
A standard 14-pin XDS510 compatible header (CONN9) is provided to allow
debugging.
In addition to the TI standard 14-pin JTAG header, there is a 20 way 0.050” pitch
high-density connector which allows direct JTAG connection to the
PCI TIM motherboards with embedded test bus controller.
Global Bus
The global bus connectors are essentially all wired in a common bus. This includes
the control signals, address and data buses. With this connectivity on the control
signals, it is evident that only the CPU site is able to generate global bus ‘master’
cycles. The two I/O sites are termed ‘slaves’, and they can contain memory mapped
resources which respond to the CPU global bus cycles.
SMT310
series of
It is not possible to insert a CPU TIM into the I/O sites unless the CPU TIM does not
have the optional global bus connector or, that the SMT118 has been specifically
modified at build time to remove these global bus connectors from the I/O sites.
CPU
The CPU TIM site connects the global bus address, data and control signals directly
to the other I/O sites’ global bus connectors.
These signals are also connected to an FPGA on the carrier board which is used to
provide the main features of this board.
Interrupts are provided via the FPGA onto the TIM IIOF and NMI signals. These
signals are inputs only to the CPU site.
I/O
The I/O sites receive the global bus address bus and control signals. They cannot
initiate a global bus cycle independently.
The four interrupt sources from each of these modules are routed to the FPGA (a
total of 8 separate interrupts).
Each I/O site has separate connectors to allow serial communication between one
another, and also to allow communication to a latching connector on the carrier
board. This provision was specifically designed for the SMT366 module and allows
the sharing of sampling clocks and outputting of DAC analog signals. There is no
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