FC202 FPGA Core
User Guide
Note: This core was initially developed for satisfying a US Navy contract. Sundance would like
to acknowledge Navy’s help and support.
Copyright © Sundance
All rights reserved. No part of this document may be reproduced, translated,
stored in a retrieval system, or transmitted, in any form or by any means,
electronic, mechanical, photocopying, recording or otherwise, without prior
written permission of the owner.
Note:
If this copy is no longer in use, return to sender.
Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundance.com
www.sundance.com
AUTHORS
Name Signature Date
Stephen Malchi 30-Jan-07
Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundance.com
www.sundance.com
Document History
Date Initials Revision Description Of Change
30-Jan-07 SM 0.00 First Release rev1.0
Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundance.com
www.sundance.com
Table of Contents
Table of Figures...........................................................................................................................5
1. GENERAL DESCRIPTION ...................................................................................................6
2. FC202 QUADRATURE CONVERSION...............................................................................8
3. PRESENTATION.................................................................................................................13
4. USAGE..................................................................................................................................14
5. VERFICATION....................................................................................................................16
DSP Test Bench ....................................................................................................................16
FPGA Test Bench..................................................................................................................16
Integrity Test Bench..............................................................................................................18
6. RELEASE NOTES ...............................................................................................................20
7. DELIVERABLES .................................................................................................................20
8. LICENSING AND PROPERTY RIGHTS............................................................................20
Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundance.com
www.sundance.com
Table of Figures
Figure 1 – FC202 Component Diagram..........................................................................................6
Figure 2 - Typical System Integration Model.................................................................................11
Figure 3 - Hilbert Transform Magnitude and Phase Response........................................................12
Figure 4 - XY Plot of Hilbert Transform........................................................................................12
Figure 5 - In-Phase and Quadrature output generated by DSP model.............................................17
Figure 6 - In-Phase and Quadrature output generated by FPGA model ..........................................18
Figure 7 - Integrity Test Bench results ..........................................................................................19
Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundance.com
www.sundance.com
1. GENERAL DESCRIPTION
FC202 is an efficient implementation of a quadrature conversion algorithm as a 3L
Diamond FPGA task. In order for it to be used within a Diamond/FPGA system, the I/O
1
interfaces are ‘standardized’ to the model described by Diamond
.
Figure 1 – FC202 Component Diagram
1
See: http://www.3l.com/Diamond/Documentation/Diamond.pdf (Chapter 28, “FPGA Tasks”)
Sundance Digital Signal Processing Inc. Rev1.0
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundance.com
www.sundance.com