Sundance FC201 User Manual

FC201 - General Offset/Gain/Delay Correction

FPGA Core

User’s Guide

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Revision 0.4

AUTHORS

Name Signature Date

B. Vacaliuc 19-May-07

DOCUMENT HISTORY

Date Initials Revision Description of Change

1-May-07 BV 0.1 Initial Release

Table of Contents

1. GENERAL DESCRIPTION...................................................................................................2

2. FEATURES ............................................................................Error! Bookmark not defined.

3. THEORY OF OPERATION ..................................................Error! Bookmark not defined.

4. I/O DESCRIPTION, BASIC MODULE................................Error! Bookmark not defined.

5. I/O DESCRIPTION, DIAMOND MODULE.........................Error! Bookmark not defined.

6. PRESENTATION...................................................................Error! Bookmark not defined.

7. USAGE ...................................................................................Error! Bookmark not defined.

8. VERIFICATION ....................................................................Error! Bookmark not defined.

9. DELIVERABLES...................................................................Error! Bookmark not defined.

10. LICENSING AND PROPERTY RIGHTS.............................Error! Bookmark not defined.

11. ORDERING INFORMATION...............................................Error! Bookmark not defined.

Table of Figures

Figure 1 - Component Diagram.......................................................................................................3

Figure 2 - Typical System Integration Model..................................................................................9

Sundance Digital Signal Processing Inc.

4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.

Tel: [phone], Fax: [phone], email: [e-mail]

www.sundancedsp.com

Page 3 of 3

Revision 0.4

1. GENERAL DESCRIPTION

This document describes the specifications of a 3L Diamond/FPGA firmware module.

The FC201 is an efficient implementation of a general offset/gain/delay correction. In order for
it to be used within a Diamond/FPGA system, the I/O interfaces are ‘standardized’ to the model
described by Diamond1.

FC201

ADC_OUTADC_IN

COEFF_IN

Figure 1 - Component Diagram

The firmware module operates in a flow-through mode; for every ADC_IN sample written, one
ADC_OUT sample will be clocked out.

The FC201 firmware module is designed to correct a single digital data channel. Typically, each
channel requires its own correction coefficients. Coefficients are loaded asynchronously and are
applied prior to the next input cycle. Loading coefficients affects a reset of the module. The
module will not accept ADC_IN samples until the first set of coefficients are loaded.

The module is useful for correcting ADC input as well as DAC output data streams.

1

See: http://www.3l.com/Diamond/Documentation/Diamond.pdf (Chapter 28, “FPGA Tasks”)

Sundance Digital Signal Processing Inc.

4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.

Tel: [phone], Fax: [phone], email: [e-mail]

www.sundancedsp.com