Datasheet SMH4811A Datasheet (Summit)

查询SMH4811供应商

SUMMIT

MICROELECTRONICS, Inc.

Distributed Power Hot-Swap Controller

FEATURES

l Supply Range ±20VDC to >±500VDC
l Versatile Card Insertion Detection Supports:

w Multi-length Pin Systems
w Card Injector Switch Sensing

w Programmable Debounce Periods
l Control Powering-on of DC/DC Converters
l Highly Programmable Host Voltage Monitoring

w Programmable Under- and Over-voltage

Detection

w Programmable UV Filter
l Programmable Power Good Delay for enabling

the DC/DC Converter

SMH4811A

Preliminary

DESCRIPTION

The SMH4811A is designed to control hot swapping of
plug-in cards operating from a single supply ranging from
20V to 500V. It provides under-voltage and over-voltage
monitoring of the host power supply, drives an external
power MOSFET switch that connects the supply to the
load, and also protects against over-current conditions
that might disrupt the host supply. When the input and
output voltages to its controls are within specification, it
provides a Power Good logic output that may be used to
turn loads on (
or drive a LED status light). Additional features of the
SMH4811A include: temperature sense or master enable
input, 2.5V and 5V reference outputs for expanding moni­tor functions, two Pin-Detect enable inputs for fault protec­tion, and duty-cycle over-current protection.

e.g.

, an isolated-output DC-DC converter,

l Programmable Circuit Breaker Function

w Programmable Over-Current Filter

w Programmable Quick-Trip™ Circuit Breaker

Values

l 2.5V and 5.0V reference outputs

w Easy Expansion of External Monitor

Functions

SIMPLIFIED APPLICATION DRAWING

0V

Pin Detect

PD1#

UV

OV

VDD

Disable/Enable

ENPG

SMH4811A

FAULT#

PG#

DC/DC

Pin Detect

–48V

©SUMMIT MICROELECTRONICS, Inc., 2000 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone [phone] • FAX [phone] • www.summitmicro.com

Characteristics subject to change without notice

PD2#

VSS

CBSENSE

2044 6.1 2/8/01

VGATE

2.5VREF

5.0VREF

2044 SAD 5.1

1

RECOMMENDED OPERATING CONDITIONS

Temperature –40°C to 85°C.

FUNCTIONAL BLOCK DIAGRAM

VDD

16

12VREF

PIN CONFIGURATION

16-Pin SOIC

SS

1
2
3
4
5
6
7
8

DRAIN SENSE

VGATE

EN/TS

PD1#
PD2#

FAULT#

CBSENSE

V

ENPG

14

SMH4811A

Preliminary

V

16
15
14
13
12
11
10

PG#
ENPG
NC

2.5V
5V
OV
UV

9

2044 PCon 5.0

DD

REF

REF

DRAIN

SENSE

EN/TS

PD1#
PD2#

UV

OV

VSS

CBSENSE

12

2.5VREF

+

1

50kΩ

ABLE

50mV

2.5V

200kΩ

+

–

+

–

FILTER

+

–

+

–

+

–

50kΩ

3

4
5

9

10

12V

5V

8

PROGRAMM-

DELAY

7

Programmable

Quick Response

Ref. Voltage

–

DUTY

CYCLE

TIMER

50kΩ

PROGRAMM-

ABLE

DELAY

VGATE
SENSE

11

5.0VREF

15

PG#

2

VGATE

6

FAULT#

2044 BD 5.2

2

2044 6.1 2/8/01

SUMMIT MICROELECTRONICS, Inc.

PIN DESCRIPTIONS

SMH4811A

Preliminary

DRAIN SENSE (1)

The DRAIN SENSE input monitors the voltage at the drain
of the external power MOSFET switch with respect to VSS.
An internal 10µA source pulls the DRAIN SENSE signal
towards the 5V reference level. DRAIN SENSE must be
held below 2.5V to enable the PG outputs.

VGATE (2)

The VGATE output activates an external power MOSFET
switch. This signal supplies a constant current output
(100µA typical), which allows easy adjustment of the
MOSFET turn on slew rate.

EN/TS (3)

The Enable/Temperature Sense input is the master en­able input. If EN/TS is less than 2.5V, VGATE will be
disabled. This pin has an internal 200kΩ pull-up to 5V.

PD1# and PD2# (4 & 5)

These are logic level active low inputs that can optionally
be employed to enable VGATE and the PG outputs when
they are at V

. These pins each have an internal 50kΩ

SS

pull-up to 5V.

FAULT# (6)

This is an open-drain, active-low output that indicates the
fault status of the device.

CBSENSE (7)

The circuit breaker sense input is used to detect over­current conditions across an external, low value sense
resistor (RS) tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor for
longer than t

will trip the circuit breaker. A program-

CBD

mable Quick-Trip™ sense point is also available.

OV (10)

The OV pin is used as an over-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if OV is greater than 2.5V. A filter
delay is available on the OV input.

5.0VREF & 2.5VREF (11 & 12)

These are precision 5V and 2.5V output reference volt­ages that may be use to expand the logic input functions
on the SMH4803A. The reference outputs are with re­spect to V

SS

.

ENPG (14)

This is an active high input that controls the PG# output.
When ENPG is pulled low the PG# output is immediately
placed in a high impedance state. This pin has an internal
50kΩ pull-up to 5V.

PG# (15)

The PG# pin is an open-drain, active-low output with no
internal pull-up resistor. It can be used to switch a load or
enable a DC/DC converter. PG# is enabled immediately
after VGATE reaches V

– VGT and the DRAIN SENSE

DD

voltage is less than 2.5V. Voltage on these pins cannot
exceed 12V, as referenced to V

SS.

VDD (16)

VDD is the positive supply connection. An internal shunt
regulator limits the voltage on this pin to approximately
12V with respect to VSS. A resistor must be placed in
series with the VDD pin to limit the regulator current (RD in
the application illustrations).

VSS (8)

VSS is connected to the negative side of the supply.

UV (9)

The UV pin is used as an under-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if UV is less than 2.5V. Program­mable internal hysteresis is available on the UV input,
adjustable in increments of 62.5mV. Also available is a
filter delay on the UV input.

SUMMIT MICROELECTRONICS, Inc.

2044 6.1 2/8/01

3

ABSOLUTE MAXIMUM RATINGS*

SMH4811A

Preliminary

Temperature Under Bias ...................... –55°C to 125°C

Storage Temperature ........................... –65°C to 150°C

Lead Solder Temperature (10 secs) ................... 300 °C

Terminal Voltage with Respect to VSS:

V

................................. –0.5V to V

DD

DD

OV, UV, DRAIN SENSE,

CBSENSE...........–0.5V to VDD+0.5V

PD1#, PD2#, ENPG, EN/TS ......... 10V

FAULT#, PG# ........–0.5V to VDD+0.5V

VGATE ................................ VDD+0.5V

AC OPERATING CHARACTERISTICS

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DBC

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DGP

t

NDTHSTSF

t

CYC

t

FVUP

t

DDP

Note: * Indicates default value

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*COMMENT

Stresses listed under Absolute Maximum Ratings may cause perma­nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.

004sµ
051sµ

*05sµ

5sµ

05sµ

052sµ
005sµ

5.1sm

*5sm
02sm
08sm

061sm

ffoETAGVottluafmorfyalednwoDtuhStsaF 002sn

*ffO —

5sm

08sm

061sm

5.0sm

5sm

*08sm

061sm

2044 Prog Table

4

2044 6.1 2/8/01

SUMMIT MICROELECTRONICS, Inc.

DC OPERATING CHARACTERISTICS

(Over Recommended Operating Conditions; Voltages are relative to VSS)

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TSYHVU

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VO

V

TSYHVO

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ETAGV

I

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V

ESNES

I

ESNES

V

BC

V

BCQ

V

STNE

V

V
V

V

V

Note: (1) TA = 25ºC.

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DD

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Am3=524.2005.2575.2V

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Am3=2.0– 1Am

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ESNES

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Am2=0 4.0V

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Am2=0 4.0V

KNIS

SMH4811A

Preliminary

DD

002Vm
001Vm

06Vm

2044 Elect Table

V

SUMMIT MICROELECTRONICS, Inc.

2044 6.1 2/8/01

5

FUNCTIONAL DESCRIPTION

SMH4811A

Preliminary

GENERAL OPERATION

The SMH4811A is an integrated power controller for hot
swappable add-in cards. The device operates from a wide
supply range and generates the signals necessary to drive
an isolated output DC/DC converter. As a typical add-in
board is inserted into the powered backplane physical
connections must first be made with the chassis to dis­charge any electrostatic voltage potentials. The board
then contacts the long pins on the backplane that provide
power and ground. As soon as power is applied the device
starts up, but does not immediately apply power to the
output load. Under-voltage and over-voltage circuits
inside the controller check to see that the input voltage is
within a user-specified range, and pin detection signals
determine whether the card is seated properly.

These requirements must be met for a Pin Detect Delay
period of t

, after which time the hot-swap controller

PDD

enables VGATE to turn on the external power MOSFET
switch. The VGATE output is current limited to I

VGATE

allowing the slew rate to be easily modified using external
passive components. During the controlled turn-on period
the VDS of the MOSFET is monitored by the DRAIN
SENSE input. When the drain sense drops below 2.5V,
and VGATE gets above VDD – VGT, the power good output
can turn on the DC/DC controller. A Power Good Enable
input may be used to activate or deactivate an output load.

Steady state operation is maintained as long as all condi­tions are normal. Any of the following events may cause
the device to disable the DC/DC controller by shutting
down the power MOSFET: an under-voltage or over­voltage condition on the host power supply; an over­current event detected on the CBSENSE input; a failure of
the power MOSFET sensed via the DRAIN SENSE pin;
the pin detect signals becoming invalid; or the master
enable (EN/TS) falling below 2.5V. The SMH4811A may
be configured so that after any of these events occur the
VGATE output shuts off and either latches into an off state
or recycles power after a cooling down period, t

Powering V

DD

CYC

.

The SMH4811A contains a shunt regulator on the VDD pin
that prevents the voltage from exceeding 12V. It is
necessary to use a dropper resistor (RD) between the host
power supply and the VDD pin in order to limit current into
the device and prevent possible damage. The dropper
resistor allows the device to operate across a wide range
of system supply voltages, and also helps protect the
device against common-mode power surges. Refer to the
Applications Section for help on calculating the RD resis­tance value.

6

2044 6.1 2/8/01

System Enables

There are several enabling inputs, which allow a host
system to control the SMH4811A. The Pin Detect pins
(PD1# & PD2#) are two active low enables that are
generally used to indicate that the add-in circuit card is
properly seated. This is typically done by clamping the
inputs to V

through the implementation of an injector

SS

switch, or alternatively through the use of a staggered pins
at the card-cage interface. Two shorter pins arrayed at
opposite ends of the connector force the card to be fully
seated (not canted) before both pin detects are enabled.
Care must be taken not to exceed the maximum voltage
rating of these pins during the insertion process. Refer to
details in the Applications Section for proper circuit imple­mentation.

The EN/TS input provides an active high comparator input
that may be used as a master enable or temperature
sense input. These inputs must be held low for a period of
t

before a power-up sequence may be initiated.

PDD

,

Under-/Over-Voltage Sensing

The Under-Voltage (UV) and Over-Voltage (OV) inputs
provide a set of comparators that act in conjunction with an
external resistive divider ladder to sense when the host
supply voltage exceeds the user defined limits. If the input
to the UV pin rises above 2.5V, or the input to the OV pin
falls below 2.5V for a period of t
quence may be initiated. The t

, the power-up se-

PDD

filter helps prevent

PDD

spurious start-up sequences while the card is being in­serted. If UV falls below 2.5V or OV rises above 2.5V, the
PG and VGATE outputs will be shut down immediately.

2.5V

OV / UV

t

UOFLTR

FAULT#

2044 Fig01 5.0

Figure 1. Under-/Over-Voltage Filter Timing

SUMMIT MICROELECTRONICS, Inc.

SMH4811A

Preliminary

Under-/Over-Voltage Filtering

The SMH4811A may also be configured so that an out of
tolerance condition on UV/OV will not shut off the output
immediately. Instead, a filter delay may be inserted so that
only sustained under-voltage or over-voltage conditions
will shut off the output. When the UV/OV filter option is
enabled an out of tolerance condition on UV or OV for
longer than the filter delay time, t

UOFLTR

, activates the
FAULT# output, and the VGATE and PG outputs will be
latched in the off state. To initiate another power-up
sequence the FAULT# output must first be reset. Refer to
the appropriate section on resetting the FAULT# output.
The Under-/Over-Voltage Filtering feature is disabled in
the default configuration of the device.

V

DD

UV

11 ≤ VDD ≤ 13

2.5V

REF

Under-Voltage Hysteresis

The Under-Voltage comparator input may be configured
with a programmable level of hysteresis. The compare
level may be set in steps (up to 15) of 62.5mV below 2.5V.
The default under-voltage hysteresis level is set to

62.5mV.

Soft Start Slew Rate Control

Once all of the preconditions for powering up the DC/DC
controller have been met, the SMH4811A provides a
means to soft start the external power FET. It is important
to limit in-rush current to prevent damage to the add-in
card or disruptions to the host power supply. For example,

<t

PUVF

OV

PD1# +
PD2#

VGATE

DRAIN

SENSE

CBSENSE

PG#

ENPG

5V

50mV

REF

t

PDD

VDD – V

GT

2.5V

<t

CBD

REF

V

DD

2044 Fig02 5.0

SUMMIT MICROELECTRONICS, Inc.

Figure 2. Complete Power On Timing Sequence

2044 6.1 2/8/01

7

SMH4811A

Preliminary

charging the filter capacitance (normally required at the
input of the DC/DC controller) too quickly may generate
very high current. The VGATE output of the SMH4811A
is current limited to I

, allowing the slew rate to be

VGATE

easily modified using external passive components. The
slew rate may be found by dividing I

by the gate-to-

VGATE

drain capacitance placed on the external FET. A complete
design example is given in the Applications Section.

Load Control — Sequencing the Secondary Sup­plies

Once power has been ramped to the DC/DC controllers,
two conditions must be met before the PG# output can be
enabled: the Drain Sense voltage must be below 2.5V,
and the VGATE voltage must be greater than V

–VGT.

DD

The Drain Sense input helps ensure that the power MOS­FET is not absorbing too much steady state power from
operating at a high VDS. This sensor remains active at all
times (except during the current regulation period). The
VGATE sensor makes sure that the power MOSFET is
operating well into its saturation region before allowing the
load to be switched on. Once VGATE reaches VDD –V

GT

this sensor is latched.
Once the external MOSFET is properly switched on the

PG# output may be enabled (if ENPG is high). The PG#
output has a 12V withstand capability, so high voltages
must not be connected to this pin. A bipolar transistor or
opto-isolator can be used to boost the withstand voltage to
that of the host supply.

Current Regulation

The current regulation mode is an optional feature that
provides a means to regulate current through the MOS­FET for a programmable period of time. If enabled the
device will start the internal timer when the voltage at
CBSENSE exceeds 50mV. Also, it attempts to limit the
voltage at CBSENSE to 60mV by regulating the VGATE
output. The circuit breaker will trip if the over-current
condition remains after the time-out. However, if CB­SENSE drops below 50mV before the timer ends, the
timer is reset and VGATE resumes normal operation. If
the Quick-Trip level is exceeded then the device will
bypass the current regulation timer and shut down imme­diately. The Current Regulation feature is disabled in the
default configuration.

Non-Volatile Fault Latch

The SMH4811A also provides an optional nonvolatile fault
latch (NVFL) circuit breaker feature. The nonvolatile fault
latch essentially provides a programmable fuse on the
circuit breaker. When enabled the nonvolatile fault latch
will be set whenever the circuit breaker trips. Once set, it
cannot be reset by cycling power.

N

OTE

UNTIL

: THE

IT IS

DEVICE REMAINS PERMANENTLY DISABLED

REPROGRAMMED AT THE FACTORY

.

As long as the NVFL is set the FAULT# output will be
driven active. The Non-Volatile Fault Latch feature is
disabled in the default configuration.

Circuit Breaker Operation

The SMH4811A provides a number of circuit breaker
functions to protect against over current conditions. A
sustained over-current event could damage the host sup­ply and/or the load circuitry. The board’s load current
passes through a series resistor (RS) connected between
the MOSFET source (which is tied to CBSENSE) and VSS.
The breaker trips whenever the voltage drop across RS is
greater than 50mV for more than t

(a factory program-

CBD

mable filter delay ranging from 10µs to 500µs).

Quick-Trip

TM

Circuit Breaker

Additionally, the SMH4811A provides a Quick-Trip feature
that will cause the circuit breaker to trip immediately if the
voltage drop across RS exceeds V

. The Quick-Trip

QCB

level may be factory set to 60mV, 100mV (default),
200mV, or the feature may be disabled.

8

2044 6.1 2/8/01

Resetting FAULT#

When the circuit breaker trips the VGATE output is turned
off and FAULT# is driven low. In the default condition the
breaker resets automatically after a time of t

. In the

CYC

latched condition cycling power to the board or toggling the
EN/TS input will also reset the circuit breaker. If the over
current condition still exists after the MOSFET switches
back on, the circuit breaker will re-trip.

SUMMIT MICROELECTRONICS, Inc.

SMH4811A

PROGRAMMABLE FEATURES

Preliminary

<T

CBD

CBSENSE

VGATE

V

QCB

50mV

T

Figure 3. Circuit Breaker Timing — Quick Trip

13

12

FSTSHTDN

2044 Fig03 5.0

The SMH4811A has programmable time and voltage
functions that can be fine-tuned for a wide variety of
applications. Because of this a manufacturer can use a
common part type across a wide range of boards that are
used on a common host but have different electrical loads,
power-on timing requirements, host voltage monitoring
needs,

etc

. This ability shifts the focus of design away
from designing a new power interface for each board to
concentrating on the value added back-end logic. Be­cause the programming is done at final test all combina­tions (all 128 possibilities) are readily available as off the
shelf stock items.

Also see the AC Operating Characteristics Table.

Pin Detect

The Pin Detect function can be enabled or disabled.

Circuit Breaker Delay

The circuit breaker delay defines the period of time the
voltage drop across R
V

before the VGATE output will be shut down. This is

QCB

is greater than 50mV but less than

S

effectively a filter to prevent spurious shutdowns of
VGATE.

(V)

DD

V

11

10

9

2

0

4

IDD (mA)

Temp, ºC

–40

0
25
85

125

68

12

10

2044 Fig04

Figure 4. Effect of Temperature on Current Con-

sumption Over Voltage Range

Power Good Delay

The PG delay timer that controls the delay to PG# being
asserted.

Quick-Trip Circuit Breaker Threshold

This is the threshold voltage drop across RS that is placed
between VSS and CBSENSE.

SUMMIT MICROELECTRONICS, Inc.

2044 6.1 2/8/01

9

APPLICATIONS

SMH4811A

Preliminary

Operating at High Voltages

The breakdown voltage of the external active and passive
components limits the maximum operating voltage of the
SMH4811A hot-swap controller. Components that must
be able to withstand the full supply voltage are: the input
and output decoupling capacitors, the protection diode in
series with the DRAIN SENSE pin, the power MOSFET
switch and the capacitor connected between its drain and
gate, the high-voltage transistors connected to the power
good output, and the dropper resistor connected to the
controller’s VDD pin.

Over-Voltage and Under-Voltage Resistors

In the following examples the three resistors, R1, R2, and
R3, connected to the OV and UV inputs must be capable
of withstanding the maximum supply voltage of several
hundred volts. The trip voltage of the UV and OV inputs is

2.5V relative to V

. As the input impedance of UV and OV

SS

is very high, large value resistors can be used in the
resistive divider. The divider resistors should be high
stability, 1% metal-film resistors to keep the under-voltage
and over-voltage trip points accurate.

Telecom Design Example

A hot-swap telecom application may use a 48V power
supply with a –25% to +50% tolerance (

i.e.

, the 48V supply
can vary from 36V to 72V). The formulae for calculating
R1, R2, and R3 follow.

First a peak current, ID

, must be specified for the

MAX

resistive network. The value of the current is arbitrary, but
it can't be too high (self-heating in R3 will become a
problem), or too low (the value of R3 becomes very large,
and leakage currents can reduce the accuracy of the OV
and UV trip points). The value of ID

should be ≥200µA

MAX

for the best accuracy at the OV and UV trip points. A value
of 250µA for ID

will be used to illustrate the following

MAX

calculations.
With VOV (2.5V) being the over-voltage trip point, R1 is

calculated by the formula:

V

OV

=

R1

ID

MAX

.

Substituting:

MIN

VS

MAX

.

×

ID VS

MAX MIN

=

ID

Substituting:

µ

72V

−

MIN UV

ID

MIN

−

µ

×

µ

.

:

MIN

.

.

250 A 36V

==

ID 125 A

MIN

Now the value of R3 is calculated from ID

VS V

=

R3

V

is the under-voltage trip point, also 2.5V. Substituting:

UV

36V 2.5V

==Ω

R3 268k

125 A

The closest standard 1% resistor value is 267kΩ
Then R2 is calculated:

V

+=

R1 R2

()

ID

UV
MIN

,

or

V

UV

=−

R2 R1

ID

MIN

.

Substituting:

2.5V

=−Ω=Ω−Ω=Ω

R2 10k 20k 10k 10k

µ

125 A

.

An Excel spread sheet is available on Summit's website
(

www.summitmicro.com

) to simplify the resistor value

calculations and tolerance analysis for R1, R2, and R3.

Dropper Resistor Selection

The SMH4811A is powered from the high-voltage supply
via a dropper resistor, RD. The dropper resistor must
provide the SMH4811A (and its loads) with sufficient
operating current under minimum supply voltage condi­tions, but must not allow the maximum supply current to be
exceeded under maximum supply voltage conditions.

2.5V

==Ω

R1 10k

µ

250 A

.

Next the minimum current that flows through the resistive
divider, ID

, is calculated from the ratio of minimum and

MIN

maximum supply voltage levels:

10

2044 6.1 2/8/01

The dropper resistor value is calculated from:

−

VS V

MIN DD

=

R

D

II

DD LOAD

MAX

+

,

SUMMIT MICROELECTRONICS, Inc.

SMH4811A

Preliminary

where VS
V

DDMAX

is the lowest operating supply voltage,

MIN

is the upper limit of the SMH4811A supply voltage,
IDD is minimum current required for the SMH4811A to
operate, and I

is any additional load current from the

LOAD

2.5V and 5V outputs and between VDD and VSS.
The min/max current limits are easily met using the drop-

per resistor, except in circumstances where the input
voltage may swing over a very wide range (

e.g.

, input
varies between 20V and 100V). In these circumstances it
may be necessary to add an 11V zener diode between
VDD and VSS to handle the wide current range. The zener
voltage should be below the nominal regulation voltage of
the SMH4811A so that it becomes the primary regulator.

MOSFET V

(ON) Threshold

DS

The drain sense input on the SMH4811A monitors the
voltage at the drain of the external power MOSFET switch
with respect to VSS. When the MOSFET’s VDS is below the
user-defined threshold the MOSFET switch is considered
to be ON. The VDS(ON)

THRESHOLD

is adjusted using the
resistor, RT, in series with the drain sense protection
diode. This protection, or blocking, diode prevents high
voltage breakdown of the drain sense input when the
MOSFET switch is OFF. A low leakage MMBD1401 diode

offers protection up to 100V. For high voltage applications
(up to 500V) the Central Semiconductor CMR1F-10M
diode should be used. The V

DS

(ON)

THRESHOLD

is calcu-

lated from:

VON V I R V

() ( )

where V

DS SENSE SENSE T DIODE

DIODE

THRESHOLD

is the forward voltage drop of the protection
diode. The VDS(ON)
due to the temperature dependence of V
The calculation below gives the VDS(ON)

=−×−

THRESHOLD

varies over temperature

DIODE

THRESHOLD

and I

SENSE

under
the worst case condition of 85°C ambient. Using a 68kΩ
resistor for RT gives:

V ON 2.5V 15 A 68k 0.5V 1V

() ( )

DS

THRESHOLD

=− ×Ω−=

µ

The voltage drop across the MOSFET switch and sense
resistor, V

VIRR

, is calculated from:

DSS

=+

DSS D S ON

()

,

where ID is the MOSFET drain current, RS is the circuit
breaker sense resistor, and RON is the MOSFET on
resistance.

,

.

.

Note: Figures 5 through 8 — the *10Ω resistor must be located as close as possible to the MOSFET

SUMMIT MICROELECTRONICS, Inc.

2044 6.1 2/8/01

11

APPLICATIONS CIRCUITS

SMH4811A

Preliminary

–48V

0V

10nF
100V

10kΩ
10kΩ

100nF

50V

R1

R3

R2

UV

OV

PD1#

PD2#

FAULT#

SS

V

20mΩ

6.8kΩ

DD

V

R

S

R

D

2.5V

REF

ENPG

SMH4811A

GATE

100nF

*10Ω

V

1kΩ

10nF
100V

CBSENSE

EN/TS

PG#

5V

REF

DRAIN SENSE

R

T

68kΩ

MMBD1401

MMBTA06LT1

1N4148

47kΩ

100nF

50V

0V

100µF

100V

–48V

2044 Fig05

–48V

0V

NTC

50kΩ

@T

50kΩ

MAX

+

–

1MΩ

LMV331

Figure 5. Changing Polarity of Power Good Output

10nF
100V

10kΩ

10kΩ

100nF

50V

R3

1kΩ

EN/TS

UV

R2

OV

PD1#

PD2#

FAULT#

R1

SS

V

R

S

20mΩ

R

D

6.8kΩ

DD

REF

V

2.5V

SMH4811A

CBSENSE

100nF

*10Ω

ENPG

GATE

V

1kΩ

10nF

100V

PG#

5V

REF

DRAIN SENSE

100nF

R

T

68kΩ

MMBD1401

50V

MMBTA06LT1

100kΩ

100nF

50V

2044 Fig06

100µF

100V

0V

–48V

12

Figure 6. Overtemperature Shutdown

2044 6.1 2/8/01

SUMMIT MICROELECTRONICS, Inc.

SMH4811A

Preliminary

EN1

EN2

EN3

EN4

–48V

0V

0V

10kΩ

10nF
100V

1MΩ

+

–

+

–

LMV

339

+

–

+

–

100nF

10kΩ

10kΩ

50V

R3

1kΩ

EN/TS

UV

R2

OV

PD1#

PD2#

FAULT#

R1

SS

V

R

20mΩ

DD

V

S

R

D

6.8kΩ

REF

ENPG

2.5V

SMH4811A

CBSENSE

100nF

*10Ω

GATE

V

1kΩ

10nF

100V

PG#

5V

REF

DRAIN SENSE

100nF

50V

R

T

68kΩ

MMBD1401

MMBTA06LT1

100kΩ

100nF

50V

100µF

100V

–48V

2044 Fig07

–48V

0V

10nF
100V

10kΩ
10kΩ

100nF

50V

R3

R2

R1

Figure 7. Expanding Input Monitoring Capability

R

D

6.8kΩ

EN/TS

UV

OV

PD1#

PD2#

DD

V

ENPG

PG#

SMH4811A

5V

REF

100nF

*10Ω

GATE

V

1kΩ

10nF
100V

DRAIN SENSE

68kΩ

MMBD1401

SS

V

R

CBSENSE

S

MMBTA06LT1

100kΩ

100nF

50V

100µF

100V

DC / DC

Converters

+VIN
–VIN
ON/OFF

2044 Fig08

+VOUT
–VOUT

V

0V

SUMMIT MICROELECTRONICS, Inc.

Figure 8. Typical Application with DC/DC Converter

2044 6.1 2/8/01

13

PACKAGES

SSOP PACKAGE

1

D

JEDEC
MO-137

SMH4811A

Preliminary

H

E

S

A

hx45

C

noisnemiD

.niM.moN.xaM.niM.moN.xaM

0 to 8
typ

L

e

sehcnIsretemilliM

B

A160.0460.0860.055.136.137.1

1A400.0600.08900.021.051.052.0

2A550.0850.0160.04.174.155.1
B800.0010.0210.002.052.013.0
C5700.0800.08900.091.002.052.0
D733.0243.0443.065.896.847.8
E051.0551.0751.018.349.399.3

eCSB520.0CSB536.0

H032.0632.0442.048.599.502.6

h010.0310.0610.052.033.014.0
L610.0520.0530.014.046.098.0

S0050.05250.00550.072.133.104.1

A

2

1

A

2044 SSOP

2044 SSOP DIM Table

14

2044 6.1 2/8/01

SUMMIT MICROELECTRONICS, Inc.

16 PIN SOIC PACKAGE

SMH4811A

Preliminary

0.155±0.005

0.236 ± 0.008

.004

Pin 1 Index

0.05 BSC

7 ± 1

0.390 ± 0.005

SOIC 16

0.016 ± 0.003

7 ± 1

.0085 ± .0010
(After Plating)

916

0.151 ± 0.005

81

0 ± 8

155 ± 0.005

DETAIL A

.016 ±.002

45 ± 1

0.024 ± 0.002

0.054 ± 0.005

0.069 MAX

.007 ± .003

7 ± 1

0.390 ± 0.005

Note: 1. Reference: JEDEC publication MS-012 PTX 360-120

2. Unit: Inches

3. Mold flash, protrusion & gate burr shall not exceed 0.006 inch per side.

ORDERING INFORMATION

SMH4811A

Base Part Number

0.007 ± 0.003

0.023 ± 0.005

0.041

DETAIL A

2044 SOIC 1.0

G

Package

G = SSOP
S = SOIC

2044 T ree 5.0

SUMMIT MICROELECTRONICS, Inc.

2044 6.1 2/8/01

15

SMH4811A

Preliminary

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating
parameters, and may vary depending upon a user’s specific application. While the information in this publication has
been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any
error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications
where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to
significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless
SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is
adequately protected under the circumstances.

© Copyright 2000 SUMMIT Microelectronics, Inc.

16

2044 6.1 2/8/01

SUMMIT MICROELECTRONICS, Inc.