Strand DDM / System DDM (1971 - 1980) PDP11 Handbook

processor

..

handbook

digital equipment corporation

DEC

Typesetting

This Handbook was typed and edited with the aid of the DECsystem 10 time· sharing system and type was set via a

DEC

computer typesetting system.

Digital Equipment Corporation

PDP,DEC,UNIBUS are registerd trademarks of Digital Equipment Corpora· tion

material in this handbook is for information purposes only and is sub·

The ject to change without notice

ii

momoomD

The

PDP-II

is that these systems represent a significant departure camputer design.

'The notatian, and theory language pravides 0 cancise and pawerful generolized method for defining an arbitrary computer system ond its operation. Along with the development of program was written for simuloting the operation of any computer system

of its benchmork comparison tests were run on

In

their feotures ond advontages, without the time ond expense of physical prototypes.

initial design step was the development, of a totolly new language,

ISP

description. With

this monner it

a family of upward-compatible computer systems.

'

af

computers coiled

was

possible

.'

the

aid of

to

evaluate 0 voriety of design choices ond compare

the

ISP

0 large number of potentiol computer designs.

from

traditional methods of

Instruction Set Processor (ISP).

ond the mochine simulotion program,

We

ISP, a PDP-IO

on

act~lIy

constructing

believe

This

the bosis

Since the main design objective of the PDP-II performonce, the interaction of software and every step in the design pracess. System programmers continually evaluated the efficiency of the code which would coding a program, the speed be built into numeraus other potential software considerations.

,thot

power and flexibility. further PDP-ll product deve lopment.

a tested and tried system. The ultimate proof of this new design opproach from

0 system executive, the eose of system resource monagement, and

The current

its generol purpose register and

Thus

the large ond rapidly. increasing number

PDP-II Family

This

the PDP-II Family

be

of

design

produced by the system software, the ease,of

real-time response, the power ond speed thot could

is

the result of this design effort.

UNIBUS

is

the bosis for our COntinuing commitment

is

at

once a new concept in computer systems, and

was

hordware

organization provides unparalleled

of

PDP-II users

Kenneth H. President, Digital Equipment Corporation

to optimize totol system

was

carefully considered

We

believe-

all

around the world.

Olsen

hascorne

iii

at

ta

Introduction

This Handbook provides basic information about the

16-bit computer, the computer. Since these computers are the

PDP-ll the processor, its major components and how the Part II sharing, communications, and data acquisition and control systems.

The and Interfacing Handbook, which includes detailed descriptions ipherals, family computers).

Manuals covering the various ating System, also available.

120 apply also to the

is

a summary

PDP-1l120

options, and the UNIBUS (the single data bus common to all

PDP-ll/15

of

PDP·ll

Processor Handbook is supplemented by the

FORTRAN,

etc.) and detailed hardware maintenance manuals are

OEM

computer, and the

functionally identical, all statements about

PDP-ll

1 15 and the

software; and Part III describes

PDP-ll

software packages (Paper Tape, Disk Oper-

PDP-ll

120 general purpose

PDP-llR20

PDP-llR20. PDP-1l120

PDP-ll

Part I describes

is programmed.

PDP-ll

of

rugged

time-

Peripherals

PDP-ll

per-

PDP-ll

iv

TABLE

OF

CONTENTS

PART PDp·U!20 PDP·U/IS PDP·UR20

I

CHAPTER 1 INTRODUCTION

PDP·11

1.1

1.2

1.3

1.4S0FTWARE .................................................................. , ........................ 7

1.5

1.6

CHAPTER 2 SYSTEM

2.1 UNIBUS ................................................................................................ 9

2.2

2.3

2.4

2.5

CHAPTER 3 ADDRESSING

3.1

3.2

3.3

3.4

3.5

3.6

CHAPTER 4 INSTRUCTION

4.1

4.2

4.3

4.4

4.5

4.6

4.7

FAMILy .................................................... ~ ............. : ................. 1

GENERAL

PERIPHERALS/OPTIONS ..................................................................... 6

DATA

COMMUNiCATIONS

DATA

ACQUISITION

CENTRAL CORE

MEMORY SYSTEM AUTOMATIC

SINGLE

DOUBLE DIRECT DEFERRED USE USE

INTRODUCTION INSTRUCTION BYTE SINGLE DOUBLE PROGRAM MiSCELLANEOUS

INTERACTION

OPERAND

ADDRESSING

Of

PC

OF

STACK

INSTRUCTIONS

OPERAND

••••.••.•..•.••.•.......•.•••••••••••....•.•......•••••••••.••••.••••...•.....••

CHARACTERiSTICS

AND

ARCHITECTURE

PROCESSOR.

.............................................................................•.... 13

PRIORITY

MODES

ADDRESSING

ADDRESSiNG

(INDIRECT)

AS

GEN

ERAL

POI

NTER

SET

.........................................................................

.................................................................................

FORMATS

INSTRUCTIONS

CONTROL

INSTRUCTIONS

.............................................................................

.............................................................. 1

.................................................................... 8

CONTROL

•.•••••••••••••••••....••..•..••••••••••.••••.•••..•••••.•• _ •..••

......................................................................

INTERRUPTS

...................................................................... 19

........................................................................

ADDRESSING

REGISTER

AS

........................ : ..........................................

........................................................................ 40

INSTRUCTIONS

.................................................... 8

................................................ 15

....................................................... 20

.............. : ..............................•........ 20

................................................ 28

.................................................. :30

GENERAL

REGISTER

...................................................

.................................................. 58

............................................... 68

............... : ..... _ ...... 34

1

9

10 15

22

37 37

39

.41

101

v

CHAPTER 5 PROGRAMMING

5.1

STACK

5.2

..............................................................................................

SUBROUTINE

TECHNIQUES

LINKAGE

..................................................... 108

lOB

................................................................... 113

5.3INTERRUPTS .......................................................................... ~ .......... 117

REENTRANCY

5.4

5.5

POSITION

5.6

RECURSION

.

5.7CO·ROUTINES .................................................................................. 124

.............................................. , ...................................

INDEPENDENT

...... c

..............................................................................

CODE..

.................................................... 123

121 124

CHAPTER 6 SPECIFICATIONS ~ ......................................................................... 125

6.1 PDp·

6.2

6.3

6.4

6.5

6.6

CHAPTER 7 CONSOLE CHAPTER 8 EXTENDED

~.1

B.2

11

120

PDp·11R20

AND

RUGGEDIZED INSTALLATION SYSTEM POWER

TELETYPE

UNITS

SU

PPL REQUI

OPERATION

ARITHMETIC

DESCRIPTION

.................................................................................. 143

PROGRAMMING

PDp·ll/15

PROCEDURE

AND

COMPUTER

........................................ 127

................................ , ........... 132

........................................................... 133

CABLES

........................................................... 133

Y ............................................................................... 134

REMENTS

............................................................. 135

.............................. : ......................... , .........

ELEMENT

.................... · .......................... 143

............................................................................... 145

B.3INSTRUCTIONS ............ , ................................................................... 148

8.4

PROGRAMMING

EXAMPLES

............................................................. 150

..

137;

vi

PART

II

SOFTWARE

INTRODUCTION CHAPTER 1 PAPER

1.1

1.2

1.3

1.4

1.5

1.6

1.7.BASIC

CHAPTER

2.1

2.2

2.3

2.4

2.5

2.6

2.7

CHAPTER 3 FORTRAN CHAPTER 4 COMMUNICATIONS

4.1

4.2

4.3

4.4

............................................................................................•... 153

TAPE

SOFTWARE

PAL·ll

AS\EMBLER ...............................................

EDITING LOADERS FLOATING ON·LlNE INPUT IOUTPUT

2 DISK

DESCRIPTION ASSEMBLY TEXT ON·LlNE FILE LINKER LIBRARIAN

APPLICATIONS DESCRIPTION DISTRIBUTION CORE

SOURCE

DEBUGGING

LANGUAGE

OPERATING

EDITOR

DEBUGGING

UTILITY

............................................................................................. 167

REQUIREMENTS

PROGRAM

AND

DUMPS

POINT

P.ACKAGE

EXECUTIVE.

............................................................................ 160

........................... : ...................................................... 163

LANGUAGE

................................................................................... 166

PACKAGE

....................................................................................... 168

IV

.................................................................................. 169

..... ~ ...........................................................................

........................... ; ........... ; ..........................................

.............................................................. ; ................... 172

.............................................................. 155

,·

............................................................ 156

..................................................................... 156

............................................................ 157

....................................................................... 159

...... ~ ................................................... 159

SySTEM

........................................................... 163

.................................................................. ;.165

...................................................................... 166

.................................................................... 166.

SOFTWARE

.......................... ; ......................................... 173

(COMTEX·ll) .............................

......................... 155

I71 171

171

CHAPTER 5 REAL

5.1

5.2

5.3

5.4

5.5INPUT/OUTPUT ............................................................................... 176

5.6

5.7

TIME

LANGUAGES SCHEDULING MEMORY MUL

OPERATOR PROGRAM

EFFICIENCY

TI·PROGRAMMING

COMMUNICATION

DEVELOPMENT

EXECUTIVE

SUPPORTED

................................................................................... 176

(RSX·llC) ................................................ 175

............ : ................................. : ................ 175

......................................................................

.................................................................... 176

......................................................... 177

...................... · ........................................ 177

vii

176

PART

III

SYSTEMS

CHAPTER

CHAPTER 3 INDUSTRIAL

1

TIMESHARING.

1.1

PROGRAMMING PROGRAM

1.2

1.3

INPUT tOUTPUT ..................................................... , ........................ 184

INTERNAL

1.4

1.5

MONITOR SYSTEM

1.6

2

2.1

PDP·Il

2.2

HARDWARE SOFTWARE

2.3

2.4APPLICATIONS .................. " ............................................................. 189

3.1

PROCESS

3.2

REAL

3.3APPLICATIONS ................................................................................. 194

ACCESS

COMMUNICATIONS

ARCHITECTURE

T-:lME

SYSTEM

LANGUAGE

DEVELOPMENT SySTEM

FUNCTIONS

.................................................... : ......................... 185

...................................................................................... 188

........................... , ............................................................ 189

DATA

INTERFACES

OPERATING

(RSTS-ll)

................................... +

.......................................................................... 185

..................................................................... 185

...................................................................... 187

.................................................................. 187

ACQUISITION

....................................................................

SYSTEM

............................................... 181

............................................................ 181

..................... : ..

AND

CONTROL

..................................................... 193

........................

APPENDIXES

APPENDIX A INSTRUCTION APPENDIX

B

MEMO~Y

REPERTOIRE

MAP ............................................................................. 199

........................................................ 195

183

193

I93

APPENDIX

INDEX

C INSTIWCTlON

.•.....•..••.•.••••••.•••.•.•.•....• · .•.••••.•.•..•...............•.•...•...•........••••...••.•.•••.•..•.••...• 221

SET

PROCESSOR

........... : ..................................... 207

viii

PDP-II/20 PDP-II/IS PDP-IIR20

ix

1

x

PART

CHAPTER 1

INTRODUCTION

I

The PDP-1I120 PDP-ll computer with a wide range of features, mally

found in

1_1

THE

The

PDP-ll vices and options, and extensive software_ similar and hardware and software upwards compatible, although each machine has some of its own characteristics. existing his

application, but

ware_

The major characteristics

is

Family of computers_

PDP-ll

family

a powerful

on

which the whole family

I6-bit

FAMILY

Family includes several processors, a large number of peripheral

members_

as

I6-bit

computer in the medium-sized branch of the

As

the first member of the

is

based_

peripherals, software and growth potential not nor-

computers_

The

needs change or grow,

New

user can chose the system which

of

PDP-II

It is a balanced, modular system

PDP-ll

systems will be compatible with

he

family computers are listed in Table

PDP-ll

machines are architecturally

is

can easily add or change hard-

family it is the

most suitable to

de-

I-

I.

1.2 GENERAL CHARACTERISTICS

1.2_1

The UNIBUS

All computer system components and peripherals connect to and communicate with each other on a

PDP-Irs sor, communicate with cessor has the same

many strengths_ Since all system elements, including the central proces-

single high-speed bus known

each

other in identical fashion

easy

access

to

peripherals

PDP-ll

System Simplified Block Diagram

as

the UNIBUS --the

via

as

the UNIBUS, the pro-

it

has to memory.

key

to the

With

bidirectional and asynchronous communications on the UNIBUS, devices

can

send; receive, and exchange data independently without processor intervention_ disk is asynchronous, the UNIBUS is compatible with devices operating over a wide range of speeds.

Device communications on the sued pleting the dent of physical bus length and the response times of master and slave devices.

For

example, a cathode ray tube (CRT) display can refresh itself from a

file while the central processor

by a "master"

data transfer. Device-to-device communication

device, a response signal

unit

(CPU) attends

UNIBUS are interlocked. For

1

to

other tasks. Because

is

received from a "slave" com-

is

each

completely indepen-

command

is-

it

TABLE

1-1

PDP-ll

Family Computers

PDP-ll/05

CENTRAL

General Purpose Registers

Instructions

Segmentation

Hardware Stacks

Stack Overflow

Detection

Automatic Priority

. Overlapped

Floating Point

Hardware

Extended Arithmetic Power Fail and standard

Maximum

Addressable

Memory Lor.ations

PROCESSOR

interrupt

instruction

Auto-Restart

Option

KDll-B 8 Basic Set Basic Set

No. Yes Yes,

single-line Single line mUlti-level multi-level

No

No option option

32K 32K

fixed

PDP-ll/IS

KCIL

8

No Yes Yes,

fixed . Yes,fixed

(four

line

optional)

No

option

(128K optional)

PDP-llI20 PDP-ll/R20

KAll 8 Basic Set

No Yes

four-line four-line

multi-level

No

No'

'option standard

standard standard

32K

PDP-1l/45

KBll 16 Basic Set

and

MUL,DIV

XOR,ASH,ASHC, MARK,SXT,SOB, SPL,RTI,MFPI, MTPD,MFPD,MTPI

.

Yes Yes Yes

programmable

multi-level PLUS 8 software

Yes

Internal

CPU(optional)

128K

levels

to

2

Interfaces to the UNIBUS are not time-dependent; there are no pulse-width or rise-time restrictions to worry about. The maximum transfer rate is one

1€?-bit

word every 400 nanoseconds, or 2,500,000 words, per

Input/output priority and may request bus mastership and steal bus and memory cycles during instruction operations, The processor resumes operation immediately after the memory transfer. Multiple devices can operate simultaneously at maximum direct memory access (DMA) rates by plained in Paragraph 2.2, Chapter

of the

II

l.2.2

The central processor, connected time

allocation

operations and instruction decoding.

po~~

registers which can be used auto'indexing pointers in autoincrement can perform data transfers directly between turbing the registers; does both single·and double-operand addressing; handles both 16-bit word and 8-bit byte data; and, by using its dynamic stacking nique, allows nested interrupts and automatic reentrant subroutine calling.

Instruction

The instruction complement uses the flexibility of the general-purpose registers provide over powerful instruction repertoire ventional 16·bit computers, which usually have three classes (memory reference instructions, operate

structions) ali operations

tions. Since peripheral device registers can be manipulated

memory by the central processor, instructions

core memory may be used equally well

example, data in an external device register can be tested

the

CPU,

can add data directly to a peripheral device register,

metically contents with a mask and branch. Thus all used to create a new dimension in the treatment for

a special class

described in Chapter The following example contrasts the rotate operation in the PDP-11 with a similar

operation in a conventional minicomputer:

devices transferring directly to

PDP-ll

Peripherals and Intertacing Handbook.

Central

Processor

of

the UNIBUS

Set

400

powerful hard-wired instructions .. the most comprehensive and

in

without bringing

it

of

I/O

instructions is eliminated.

4.

or

from memory are given highest

"stealing"

2;

for

as

of

any computer in the 16-bit class. Unlike con-

the PDP-11 are accomplished with one set of instruc-

into

memory

bus cycles. The UNIBUS is further

and is covered in considerable detail in Part

to

the UNIBUS

peripherals and performs arithmetic and logic

It

contains multiple high-speed general·pur-

accumulators, pointers, index registers,

or

for

data in peripheral device registers. For

or

as

a subsystem, controls the

autodecrement modes. The processor

I/O

devices and memory without dis·

AC

control instructions and

that

are used to manipulate data in

disturbing the general registers.

or

compare logically

PDP·ll

otcomputer

PDP-llI20

on

the UNIBUS

second_

of

instructions

as

flexibly as core

or

modified directly by

instructions can

I/O

or

and the need

instructions are

I/O

arith-

ex-

or

tech-

in-

One

as

to

be

.

RORA

LOA

A

PDp·ll

Approach

; rotate contents of memory location A

right one place

Conventional

; load contents

AC

Approach

of

memory location A

into

3

ROR

STAA

PDp·l}

The basic order code of the

instruc~ions

for words or bytes; The

one step, such operations

as

uses

PDp·}l

adding or subtracting two operands,

operand from one location to another:

.;rotate contents of

;store contents of

AC

right one place

AC

~n

location A

both single and double operand address

therefore performs very efficiently in

or

moving

PDP-ll

Approach

an

ADDA,B

LDAA ADDB STAB

Priority Interrupts

A

multi· line automatic priority interrupt system permits the processor to respond

automatically

be

can (any number of devices). A tional

Each

peripheral device in the

to

attached to

on the

PDp·1l1l5

conditions outside the system, Any number of separate devices

.each

line.

The

multi· line system, like that of the PDp·

(KFll·A).

PDp·ll pair of memory words (one points contains the new status processor information). This unique identification nates the

servicing hardware

after having

need

for polling of devices to identify

selects and begins executing the appropriate service routine

automatically

saved

; add contents of location A to location B

Conventional

Approach

;Ioad contents of memory location into ;add cntents of memory location B to ;store results

PDP·

11

115 has only a single line

at

location B

11

of

120,

interrupt

is

op·

system has a hardware pointer to its own

to

the devices's service routine, and the other

elimi·

an

interrupt, since the interrupt

the status of the interrupted program segment.

AC

The devices' interrupt priority and service routine priority are independent. This

allows adjustment of system behavior in response to real·time conditions,

by

dy·

namicallY changing the priority level of the service routine.

The interrupt system grammable ledge ing device. pletion

priority with the priority of any interrupting devices and to acknow·

the device with the highest level above the processors

an

interrupt for a device can Service to the lower priority device is resumed automatically upon com·

of the higher

ing, can be carried out to any level without requiring the software to

allows the processor

be

level

servicing.

Such

to

continually compare its own pro·

priori~y

level. Servic·

interrupted for servicing a higher priority

a process, called nested interrupt servic·

save

and

reo

store processor status at each level.

The

interrupt scheme is explained in paragraph 2.7, Chapter

2.

Reentrant Code

Both the interrupt handling hardware writing reentrant code for given .subroutine

or

the

program

PDP·11.This type of code allows a single copy of a

to

be shared

and

the subroutine call hardware facilitate

by

more than one process

or

4

task. This

reduces the amount of core needed for mUlti-task applications such current servicing

Addressing

Much of the power pabilities. dress indexing, full dressing_ Variable length instruction formatting allows a minimum number of bits to

be

storage space. Addressing modes are described in Chapter

Stacks

In the

PDP-ll,

to

make efficient use of frequently accessed data. The stack

by

program interrupts, subroutine calls, and trap instructions_ sor is interrupted, the central processor status word and the program counter are saved

(pushed) onto the stack area, while the processor services the interrupting device. A memory which the interrupt instruction restores the

interrupted program without software intervention.

ter

5.

Direct Memory Access

All PDP-l1's provide for direct access to memory. Any number of

may

be

attached

allowing memory data storage or retrieval at memory cycle speeds. Latency

minimized

and priorities in

Power Fail and Restart

The

PDP-ll's

fails, but also allows the user to

power

(including all dynamic registers), thus preventing harm to devices, and

status eliminating the need for reloading programs_ Automatic restart when power returns to safe operating levels, enabling remote

ations of

in the systemized power-fail protect/restart feature. This feature is optio-

cluded

nal

on

the

of

many peripheral devices.

of

the

PDP-ll

addressing modes include list sequential addressing, full

l6-bit

used for

new

PDP-ll

each

addressing mode. This results in efficient use of program

a stack is a temporary data storage area which allows a program

status word

is

reserved for interrupt instructions (vector area). A return from

to

the UNIBUS. Maximum priority is given

by

the organization and logic of the UNIBUS, which samples requests

parallel with data transfers_

power fail and restart system not only protects memory when

systems_

PDP-llll5

(KPll-A).

is derived from its wide range of addressing

word addressing, 8-bit byte addressing, and stack

3.

is

then automatically acquired from

original processor status and returns to the

save

All standard peripherals in the

Power Fail

Stacks are explained in Chap-

to

the existing program location and

or

PDP-ll

is

discussed in Chapter

as

the con-

ca-

ad-

used automatically

When

the proces-

an

area in core

DMA

is

unattended oper-

devices

devices thus

accpmplished family are in-

2,

paragraph

2_

1.2.3· Memories

Memories with different ranges freely mixed and interchanged in a single expand and growing pains and Chapter

1.2.4

The

tems, easy expansion, and

ing-blocks, called

connected wiring between

memory

as.

memory technology grows, a

2,

paragraph 2.5

Packaging

PDP-ll

only

module.

obsolescence associated with conventional computers.

has adopted a modular approach to allow custom configuring of

System Units, which are completely independent subsystems

by

pluggable UNIBUS and power connections. There

them_

An

of

speeds and various characteristics can

PDP-ll

system_

Thus

as

PDP-ll

can evolve with none of the

easy

servicing_ Systems are composed of basic build-

example

of

this type of subsystem is a 4,096-word

memory needs

is

no fixed

be

See

sys-

is

5

System Units can 'be mounted in many combinations within the ware, since there are no fixed positions for memory or ditional units can case maintenance and operation resumed within a few minutes.

PERIPHERALS/OPTIONS

1.3 Digital Equipment Corporation (DEC) designs and manufactures many of the per· ipheral devices offered with PDP·l1's. ipherals, small computer environment, lower prices, more choices and quantity discounts.

Many processor, tions are available. These devices are explained in detail in the Peripherals and in· terfacing Handbook. Options llR20

1.3.1 All

their

punches, line printers, card readers DECwriter, a totally DEC·designed and built teleprinter, can serve tive to the Teletype. typewriter terminals, including higher speed, fewer mechanical parts and very quiet operation.

PDP·II

DEC

are discussed in Chapter

I/O

PDP·

I I systems are available with Teletypes

I/O

I/O DECterminal alphanumeric display DECwriter teleprinter High High Teletypes Card Readers Synchronous and Asynchronous Communications Interfaces

be

mounted easily and connected

is

required, defective System Units can be replaced with spares

As

can offer extremely reliable equipment specifically designed

input/output,

memory, bus, storage, and communications op·

used

a designer and manufacturer of per·

only

by

thePDP·1l!l5,

8.

Devices

capabilities can be increased with high speed paper tape reader·

It

has several advantages over standard electromechanical

devices include:

Speed

Line Printers

Speed

Paper Tape Reader and Punch

or

alphanumeric display terminals.

I/O

device controllers. Ad·

to

the system in the field. In

PDP·1l120, and PDp·

as

standard equipment. However,

PDp·ll

as

an

for

The

alterna·

hard·

the

LA30

1.3.2 Storage Devices

Storage devices range from convenient, small·reel magnetic tape (DECtape) units

to mass storage magnetic tapes and disk memories. With the number system. TU56 DECtapes, highly reliable tape and Each

quire handling of large volumes of data,

Magtape. Disk storage devices include

cartridge and disk pack units.

memory, to the

of

storage devices, in any combination, may

built

by

DEC,

DECtape provides storage for

are ideal for applications with modest storage requirements.

RP02 Disk Pack system which can store up to 93.6 million words.

I47K

fixed· head disk units and moving·head removable

These

devices range from the 65K RS64 DECdisk

units

I6·bit

DEC

offers the industry compatible

be

with small tape reels, designed

words. For applications which

UNIBUS, a large

connected to a

PDp·l1

reo

TUIO

6

PDP·ll

storage devices include: DECtape Magtape RS64

~5K·256K

RS11

256K·2M word fixed·head disk

word fixed· head disk

RK03 1·2M word moving·head disk RP02

10M

word moving

head

disk

1.3.3 Bus Options

Several

options (bus switches, bus extenders) are available for extending the UNI·

BUS

or for configuring multi·processor or shared·peripheral systems.

1.4

SOFTWARE

Extensive software, consisting PDp·ll

Family systems. The larger the

of

disk

.and

paper tape systems, is available for

PDp·ll

configuration, the larger and

more comprehensive the software package that comes with it.

1.4.1 Paper Tape Software

The

Paper

Tape

Software system includes:

Editor

(EDll)

Assembler

(PALll)

Loaders

On·Line Debugging Technique

Input·Output .Executive

Math Package

(FPPll)

(DOnI)

(lOX)

1.4.2 Disk Operating System Software

The

Disk Operating System software includes:

.~

Text Editor (£011) Relocatable Assembler (PAL1IR)

Linker

(UNKll) File Utilities Packages (PIP) On

Line Debugging Technique (ODT1I)

Librarian

1.4.3 Higher

PDP·ll which can memory. A cess a PDP·ll

(UBRll)

Levt!1

users needing

be

Languages .

an

run

on

the paper tape software system with only 4.096 words of core

multi·user extension of

with o"!ly 8K of core.

interactive conversational language can

BASIC

is available

so

up to eight

use

users

BASIC

can

ac·

7

RSTS-ll

The

PDP-ll

riched version

Resource Timesharing System

of

BASIC,

is available

for

up

(RSTS-ll)

to

with BASIC-PLUS, an

16 terminal users.

en-

FORTRAN

PDP-ll

FORTRAN

provide

easy

1.5

DATA

The advanced architecture of in multiplexer, and multiple single-line interfaces tiplexing hardware; byte handling, the complished easily and efficiently ity-in the communications area bardware and communications-oriented software.

COMTEX-11 ware is explained in the Peripherals and Interfacing .Handbook; and communications applications are discussed in Part III, Chapter

1.6

The (RSX-11C Real-Time Executive) combine systetyls 11 hardware is described is described in Part II, Chapter

applications is discussed in Part III, Chapter

COMMUNICATIONS

data communications applications. For example, the UNIBUS performs like a

DATA

ACQUISITION

PDP-II.

for

is an ANSI-standard

compatability with

software,

is

described in Part II, Chapter

PDP-11

FORTRAN

IBM

1130

Family machines makes them ideal

key

by

the PDP-11.

DEC

has developed a full line of communications

IV

FORTRAN.

to

communications applications, is

compiler with elements that

can

be

added without special mul·

To

provide total systems capabil-

4;

communications hard-

2.

for

CONTROL

modular process interfaces and special state-of-the art software

industrial'data acquisition and control (IDACS) applications.

in

the Peripherals and Interfacing Handbook.

6;

and the

to

provide efficient, low-cost and reliable

PDP-11

in data acquisition and contrDl

3.

IDACS-

RSX-llC

use

ac-

8

PART I

CHAPTER 2

SYSTEM ARCHITECTURE

SYSTEM

Digital Equipment Corporation's computer using two's complement arithmetic. The length processor which directly addresses bytes. All communication between system components is done on a single high· speed eral·purpose registers which dress pointers, and an automatic priority interrupt system.

2.1

The UNIBUS memory, and along the

The form cessor uses the same set ipheral devices. Peripheral devices also nicating including memory locations, processor registers, and peripheral device registers, is assigned an address on the memory location, while location Thus, peripheral device registers may by memory can an structions to process data in any memory location

tor.

2.1.1

Most UNIBUS lines are bidirectional,

input can either read or loaded by the central processor the same register can

2.1.2

Communication between two devices on the bus relationship. At any point is time, there is one device that has control of the bus. This the bus A typical example of this relationship struction from memory (which is always a slave). Another example is the disk, master, transferring data dynamic. The processor, master, could then' communicate with a slave memory bank.

DEFINITION

PD~·l1

is

a 16·bit, general·purpose, parallel16gic

PDp·ll

is

a variable word

32,768 16·bit words or 65,536 8-bit

bus called a UNIBUS. Standard features of the system include eight gen·

can

be

used

as

accumulators, index registers, or ad·

UNIBUS

is

a single, common path

all peripherals. Addresses, data, and control information are sent

that

connects the central processor,

56 lines of the bus.

of

communication

with

the processor, memory or other peripheral devices.

is

the same

of

signals to communicate with memory

for

every device on the UNIBUS. The pro·

use

this set of signals when commu·

UNIBUS. For example, location 10008 is a core

Each

as

177562 is the Teletype keyboard data buffer.

be

the central processor. All the instructions

especially powerful feature, considering the special capability of

be

applied equally well

Bidirectional

be

Master-Slave

controlling device is termed the

when

Lines

driven

as

output. This means

be

used

for

Relation

communicating with another device on the bus, termed the "slave".

to

memory, as slave. Master-slave relationships -are

for

example, may pass bus control to a disk.

manipulated

to

so

both input and output functions.

that

data in peripheral device registers. This is

that the same signals

that

"bus

master". The master device controls

is

the processor,

as

flexibly

as

itwere

an accumula·

that

are received

of

a master·slave

core memory

PDP·ll

The.c:Jisk,

can

be

applied to data in core

as

though

a peripheral device register can

or

other peripheral devices; thus,

is

in the form

as

master, fetching an in·

with per·

device,

in·

as

'be

as as

9

Since

the UNIBUS structure to determine which device gets control of the UNIBUS which is capable two

devices, simultaneously, the device with the higher priority will receive control. structure

2.1.llnterlocked Communication

Communication sued complete the transfer. Therefore, communication is independent bus length (as far and nizing with, and waiting for, clock pulses. Thus, at its maximum possible

2.2

The central processor purpose registers, arithmetic unit, and UNIBUS and priority control. Data paths

conncecting these units are in a figure eight.

lowing data transfers:

is

by

the master device, there must

slave

devices_

CENTRAL

register to register memory to memory register to memory memory to register

is

used

by

the processor

of

which are capable of becoming a bus master, request

further explained in paragraph 2 .5 of this Chapter.

on

the UNIBUS is 'interlocked

as This asynchronous operation precludes the

PROCESSOR

becoming

timing is concerned) and the response time

speed_

is

organized around three functional blocks: the general

PRIORITY' I T

7

and

bus

master

be a reSponse

The

STATUS

WORD

I·NI

5

all

I/O

devices, there

bus.

is

so

that for

each

processor may perform the fol-

z I

vI

Every

assigned a priority.

each

from the slave in order, to

device is allowed to operate

control signal

need

c I

o

is

a priority

device on the

use

of

When

of

the

The

priority

the physical

the master

for synchro-

bus

is-

2.2.1

General The PDP-11/15, PDP-1l/20, and eight-general purpose registers. These registers (referred to may

be

Registers pointer, and functions greatly enhances the power and flexibility discussed in Chapter 3 and Chapter

2.2.2

The Central Processor Status Register(PS) contains information on the current. priority of

Registers

used

as

accumulators,

R6

and

R7

Central Processor Status Register ,

the processor, the result

have

is the program counter. Using general registers to perform these

PDP-llR20

as

auto index registers,

unique capabilities.

5_

of

the previous operations, and

processors

R6

serves

of

each

contain one set

as

RO,

RI,

or

as

pOinters. General

as

the

the PDP-ll_ Their

R2,.

hardwar~

an

indicator

__

R7)

stack

use

of

is

10

for detecting the execution of an instruction to bugging. anyone

Four bits structions. These

The T control. trap will occur on

The processor status word ated on

Register organization

GENERAL

The

priority of the central processor can

of five levels. This information

of

the

PS

are assigned

bit'>

are set

as

Z ..

if

the result

N ..

if

the result

C·:

if

the operation resulted in a carry from the most significant bit

V

..

if

the operation resulted in

bit

is

used in program debugging and

If

this

bit

by

any instruction.

REGISTERS

R0

RI

R2

R3

R4

R5

R6

(SPI

R7JPCl

was

is set,

when

completion

for

15

zero

negative

an instruction

of

is

location 177776 on the UNIBUS and can

PDP·UI20,

UNUSED

is

held in bits

to

monitoring different results of previous in·

follows:

an

arithmetic overflow

can is

the instruction's execution.

PDp·1l115

CENTRAL

PROCESSOR

be

trapped during program

be

set under program control

5,

6,

and 7 of the

be

set or cleared under program

de·

to

PS.

fetched from memory, a processor

be

oper,

and

PDP·llR20:

STATUS REGISTER

8 7 6 5

4

o

2.2.3 Processor States

This description reader a basic description of the processor's operation. More including theory Manual, DEC·ll·HR2A·D.

The

PDP·ll and service. vice is

used

Fetch: processor enters another major state, depending on the type decoded. to

Source: decodes the source field of a double·operand instruction and transfers state is entered only

Destination: decodes the destination Destination

of

the

KAll

(and

KCll)

processor is intended only

detailed discussion,

of

operation and logic design, is provided

in

the

KAII

processor has five major states: fetch, source, destination, execute

The

first

during special operations, such

four states are used during normal processor operation; ser·

as

traps and interrupts.

locates and decodes

It

is possible

an

to

go from fetch

instruction.

to

When

fetch is completed, the

any other state, including back

fetch. Every instruction starts by first entering the fetch state.

the

source operand to the appropriate location. The source

if

the instruction is a double·operand type.

field

of

the appropriate instruction.

fields are present in both single and double·operand instruc·

11

to

give the

Processor

of

instruction

major

tions. Destination operand tion.

Execute: the specified operation. During this state arithmetic operations, tions, and tests are performed, and the Destination location

required. Service:

Although major states follow the sequence of fetch, source, destination, execute, and service, not enters

only the states necessary to execute the current instruction. The minimum

sequence is from fetch of one instruction Maximum sequence is fetch, source, destination, execute, service, and back to fetch.

2.2.4 Processor Traps

There

area

Central Processor to trap to a set of fixed locations. These include Power Failure, Odd

Addressing Errors, Stack Errors, Timeout Errors, Memory Parity Errors,

of

Reser:ved

of the

lOT,

The T bit Trap TRAP

instructions are described

Power Failure

Whenever 235 v nominal) or outside a power fail sequence

cation 24 and the power fail program

(data in registers), condition

location 24 to a pointer

of When

power up routine auto·restart

Odd

Addressing Errors

This error occurs whenever a program attempts an

odd address (in the middle of a word boundary).

and the

Time-Out Errors

These errors occur and there is no slave pulse within 10 I'sec. This error usually occurs in attempts address non·existant memory or peripherals.

The offending instruction

Reserved Instructions

There

is

trap through location

2.2.5 Trap Handling

Appendix B includes a list of the reserved Trap Vector Locations. curs, the processor follows the same procedure

uses

the data obtained during previous major states

used

to execute special operations, such

all major states are required for every instruction. The processor

series of errors and programming conditions which

Instructions,

EMT,

and

TRAP

has

already

AC

power drops below

is

initiated. The Central Processor automatically traps to

is

restored the processor traps to location 24 and executes the power

to

restore the machine

is

an

option

CPU

traps through location

when

a Master Synchronization pulse

a set of illegal and reserved instructions which

4.

is

accessed and transferred

directly to fetch of the next instruction.

Use

of the T bit in the Processor Status Word, and

instructions.

been

discussed in this chapter.

in

Chapter

95

limit

of

peripherals

to

the power-up routine.

to

on

is

its state prior

the

PDP-ll

aborted and the processor traps through location

4.

volts for 117v nominal power (190 volts

47

to

63Hz,

as

measured by

has

2 msec. to

for

power fail, and change the contents

to

115.

4.

power failure. Power fail and

to

execute a word instruction on

for

traps

to

appropriate loca·

is

as

interrupts, traps, etc.

\l\(ill

The

lOT,

DC

save

all volatile information

The

instruction is aborted

is

placed

on

the UNIBUS

'cause

the processor

When

as

it

does for interrupts

to

perform logic func· updated

cause the

Use

use

EMT,

and

for

power, the

to

4.

to

a trap

oc-

if

10·

12

(saving the Program Counter (PC) and Processor Status Word (PS) on the new Processor Stack etc ... )

2.3

CORE

2.3.1

A memory signed to

MEMORY

Memory

can

each

Organization

be

viewed

as

a series

of

location. Thus a 4096-word

__

locations, with a number (address)

PDP-II

memory could be shown

as-

as

follows:

000000 000001

000002

000003 000004

OCTAL

ADDRESSES

017774

017775

017776

017777

Because

PDP-ll

memories are designed to accommodate both 16-bit words and 8-bit bytes, the total number of addresses words. A 4096-word memory

can

contain 8,192 bytes and consists

LOCATIONS

'-'

does

not correspond to the number of

tal locations. Words always start at even-numbered locations. A

PDP-ll

word is divided into a high byte

HIGH

BYTE

15

I

B 7

and

a low byte

LOW

BYTE

as

of

follows:

o

017777

oc-

Low bytes

are

stored at even-numbered memory Im;ations and high bytes at oddnumbered memory locations. Thus the

PDP-ll

memory

as

follows:

it

is convenient for the programmer to view

13

000001 000003 000005

,

.......--

BYTE HIGH

HIGH HIGH

16-BYTE

~

WORD

BYT

LOW LOW

LOW

,

000000 000002 000004

OR

WORD

(

{

(-,

~

B-BYTE

WORD

LOW

BYTE

HIGH BYTE

LOW

BYTE

HIGH BYTE

LOW

BYTE

000000

000001

000002

000003

000004

017773

017775

01777 ~ I--H-IG-H

PDP·ll

HIGH

r----------r--------~

HIGH

________

--+--L-O-W--;

WORD

ORGANIZATION

~

-L

________

LOW LOW

017772

017774

017776

~

memories are normally provided in 4096·word read and write modules.

( (

BYTE

HIGH

LOW

HIGH

ORGAN

017775

017776

017777

IZATION

However, there are also 8192·word interleaved memory modules. The various PDp·ll

memories, their characteristics and speeds are listed below.

Specifications

Memory

MMlH

MMll·F

MMll·FP with parity

and

Size

4K

Memory

X 16 bit

X 18

bit

Types

Type

0::::.,

"'?

E 0

:3:0

(r)

N

>.

. - E

.... c .,

00

E:;:;

.,

ro

E·~

C

.-

QJroal

oOD

c..>o

.....

u

Q.

E

::J

E

Access

500ns

400ns

Time

Cycle

l200ns

950ns

Time

Interieaved

Access

*

Cycle

500ns 900ns

400ns

490ns**

400ns 490ns**

(1 bit per

byte)·**

M792

words

bit

Read

only; al90

available

as

lOOns

NO

3216

bootstrap loader

AI.I

memories are

Temperature:

*MMll·F

suffix

"X"

**For a 16·bit

800

ns.

··"Available

PDP·ll

OOto

and

MMll·FP

to part number

DMA

Unibus·compatible

50°C

automatically..interleavEld

when

ordering

transfer into memory. A

from Computer Special Systems

MMll·E

l6·bit

if

8K

or more

interleaved (Le.,

transfer

out

of memory takes

is

ordered.

MMll·EX).

Add

14

The areas and trap vectors, isters. Most of the addresses between 00000o and 00370 rupt: vectors, anc( the tpp 4,096 addresses are generally reserved for peripheral device registers. A detailed address map is contained in Appendix

The concept programmer can directly address-32K word locations. A memory extension unit

available for the sable locations to 128K.

2.3.2Interleavirig

When are performed with a 4K memory bank and cannot technique called "interleaving", causes successive memory

formed within alternate 4K memory banks. This allows cycles to that is the second memory bank has completed its cycle, provided the bus is free. This effect is called memory in· terleaving and results in faster memory operation.

Memory interleave is completely transparent to the it memory

ing the 950 nanosecond

Interleavlng.affects first terleaved and the second delivered from

2.4

Full 16·bit words tween a master and a data. This type structions, operands, and data from memory, and storing the results into memory after execution peripheral device control and memory.

2.5

When ter and requests

Direct memory ipherals without processor supervision. called (memory display).

of

addresses

of

pr.ocessor

particular interest

stack and general storage, and peripheral device

to

the programmer are the interrupt

are

reserved

8.

of

word "pages" has

PDp·ll/20

an

address register is incremented on successive memory cycles, the cycles

were

one continuous 8K block. Interleaved memory allows 16·bit transfers into

every

490 nanoseconds, and out of memory every 800 nanoseconds (us·

8K

is interleaved. If the system has

DEC

SYSTEM

INTERACTION

of

AUTOMATIC

a device (other than the central processor) is capable of becoming bus mas·

L to make a non· processor transfer

2.

to interrupt a program execution and force the, processor to

cific address where

or

NPR

level

to/from

MMll·F).

8K

blocks.

is

automatically interleaved.

or

8·bit bytes of information can

slave.

operation occurs when the processor,

of

PRIORITY

use

of

the bus,

direct data transfers

data transfers. are usually made for Direct Memory mass storage) or direct device transfers (disk refreshing a

been

completely eliminated in the

and PDP·l1R20 to extend the number of addres·

be

overlapped. However, a

can

start its cycle before the first memory bank

user,

who addresses core

For

example,

8K

would also

The information can

instructions. Direct data transfers occur between a

if

a system has a

16K

of

memory, the first 8K would

be

interleaved. Any 8K block

be

transferred

be

instructions, addresses, or

as

master, is fetching in·

PDp·n.

cycles

be

12K

memory, the

on

to

overlapped;

of

the bus

INTERRUPTS

it

is generally for one of two purposes:

of

data directly to or from memory

an

interrupt service routine is located.

can

be

accomplished between any two per·

These

non· processor request transfers.

go

reg·

for

inter·

The

be

per·

as

be

memory

to a

spe·

Access

CRT

in·

be·

is

if

The

PDp·ll

has

a multi·line, multi·level priority interrupt structure.

15

DEVICE

CP

. PRIORITy LINE

REQUEST

......-NPR----,-------,,------,------

8

-~

..

~

_BR7---[;5-0'6---.-·

4--BR6----.-----,----------------

[;5

-[±J--'0'-7

--.

---------

[;5

--

--,.

~

----!

~

--BR'--[f]-'-01

_BR4-[fJ-r-

See

Table

I-I,

II's.

Bus

Highest priority is assigned memory cycles

of

Bus

request 7 (BR7) is the next highest priority, and BR4 low BR4 are not implemented in the in larger machines (PDP-1l/45). Thus, a processo'r priority have the same effect,

BR7

through

tions.

The

programmable. For example, Teletypes are normally assigned to Bus Request line

4. Bus request lines assigned Appendix

The processor's priority can using bits level that inhibits granting of bus requests on lower levels When

the processor's priority

on

BR6

When

more than one device is connected to the same bus request (BR) line; a vice nearer the central processor has a higher priority than a device farther away. Any number of devices can

Thus the priority system

unique priority. the processor priority varies. Also, abled

or disabled under program control.

page 2

requests from external devices

access

type transfers, and are honored

an instruction execution.

BR4

priority

B.

7,

6,

and 5

and below are ignored.

Although its priority. level is fixed, its actual priority changes

--[±]---'02--.-[±]-'-03

-[f]-'--HSP

HSR

,for

a summary of the

to

i.e.

all interrupt requests will

priority requests are honored

is

hardwired into

to

be

in.

the processor status register.

is

be

is

two·dimensional and provides

-dJ---r--

INCREASING PRIORITY

can

non-processor request (NPR). These are direct

"-

PDP-UI20,

each

device except for the processor, which

each

peripheral device and option are

set under program control

set

to

a level,

connected to a given

each

device may

---

-.

KB

API

structures of the various

be

made on one of five request lines.

by

11/15, or

be

by-

the processor ,between instruc-

for

example

BR

be

---

--~

[fJ---r-

- - -

TP

the procesor between bus

is

the lowest. Levels

llR20,

of

3,

granted.

to

one of eight levels

These

bits set a priority

or

on the same level.

PS6,

aU

or

NPR

line,

each

dynamically, selectively en·

--

PDP-

are

1,

or 0 will

showr1

be·

used

de·

as

They 2,

bus requests

device with a

is

in

16

Once a device other than the processor has control of the bus, two types

NPR ipheral

. are between a mass storage device, such

ture signed peripheral controllers

An NPR device has very fast access once the processor can relinquish control while an instruction is in progress. This can occur at the end of any bus cycles except in between a quence. An or

memory

Interrupt Operations· Devices the bus request lines (BR7, BR6, BR5, BR4) can take advantage flexibility

..

data and status registers. currently under way in the central processor is interrupted and the device service.

routine is initiated. turns done automatically by the processor.

Example· A peripheral devices requires service and requests use of

of

operations: data transfers

Data

Transfers·

devic.es

of

the bus also permits device-to·device transfers, allowing customer·de·

it

has control. The processor state is riot affected by the transfer; therefore

less.

the

,

.

NPR

An

N'PR

at

memory speed.

of

the processor. The entire instruction set

to

the interrupted task. This is all accomplished through

BR

levels.

1.

The processor determines which device is requesting use of the bus, and

compares the priority of the device with the existing processor priority.

2.

If

device priority sending a signal along a bus grant line, and the device takes control bus.

3.

When the device has control of the'bus, rupt command with the address of the words in memory containing the ad· dress and status of the appropriate device service routine. '

4.

The processor then saves the current central processor status (PS) and the current program counter (PC).

5.

The new fied by the device and the next location, and the device service routine is begun. Note vice·polling is required to determine which service routine (Appendix B contains a

6.

7.2 microseconds ceiving the interrupt command and the fetching This assumes there were no

7.

The device service routine can resume the interrupted process byexecu-

ting

the seconds PC

and

NPR

without the supervision

device in control of the bus may transfer

Once the device request has been satisfied, the processor

PC

that

RTI

(Return from Interrupt) ,instruction. This requires 4.5 micro-

if

there are no intervening NPR's.

PS.

data transfers can· be made between any two per·

to

device can gain control

that

When

is

higher, the processor grants priority

and

PS

are'take from the location (interrupt vector) speci·

these operations all occur automatically and

list of interrupt vectors.)

is

the time interval between the central processor's

or

interrupt

of

the processor. Normally, NPR transfers as

access other devices, such

to

the bus and can transfer

request interrupts after getting bus control on '

a device servicing program must be run, the task

NPR

transfers during this time.

operations.

a disk, and core memory. The struc·

of

the bus in 3.5 microseconds

is

available

it

sends the processor an inter· ,

It

is done

it

may do one of

as

disks, directly. at

high data rates

read·modify·write

i6·bit

words from

of

the power and

for

manipulating

h~rdware,

of

the bus at one

to

the device

that

to

execute.

of

the first instrucU(:tn.

by

restoring the old

and

of

no

se·

reo

is

by

the

de-

re-

8.

A device service routine

priority bus request any time after

9.

If

such

an

tine

are

had

been

priority interrupts can go on to any level, limited only

for temporarily storing the

interrupt occurs, the

also automatically

saved) and

can

be

interrupted in turn

completion of its first instruction.

PC

and the

PS

saved

the

(without loss

new device routine is initiated. This nesting

PS

and the

PC.

of the device service rou·

of

the other

by

a sufficiently high

PC

and

by

the core available

PS

that

of

.

18

PART

CHAPTER

I

3

ADDRESSING

Data stored in memory must specified

Since a large portion of the data handled character strings, in arrays, in lists etc.), the structured data efficiently and flexibly. The general registers may instruction in any of the following

PDP·U's temporary frequently accessed. This is known

In the trol, ruptservice automatically reason

An addressing modes, is the register arrangement:

by

a PDp·11 instruction the function (operation code) a general purpose register

and/or

a general purpose register to

operand. an

addressing mode (to specify how the selected register(s) is/are

used)

as

accumulators.

as

pointers. The contents of the register are the address of the operand,

rather than the operand itself.

as

pointers which automatically step through core locations. Automatically stepping forward through consecutive core locations is known toincrement addressing; automatically stepping backwards

autodecrement addressing. These modes are particularly useful for pro·

cessing tabular data.

as

index registers. In this instance the contents

word

following the instruction are summed

operand. This allows

also have instruction addressing mode combinations which facilitate

data

storage structures

PDP-11

however,

important

any register can be

certain instructions associated with subroutine linkage and inter-

R6

is frequently referred

PDP-ll

be

accessed, and manipulated.

(MOV,

to

be

used

ways:

The

data to

be

manipulated resides within the register.

easy

access

for

convenient handling

as

the

used

as

use

Register 6

to

as

the

feature, which must

ADD

etc.) which usually indicates:

when

be

by

to variable entries in a list.

"stack."

a "stack pointer"under program con·

as

"SP". be

locating the source operand

used

when locating the destination

a computer

PDp·

11

has

to

produce the address of the

(See

a "hardware stack pointer". For this

considered in conjunction with the

Data

is

usually structured (in

been

designed

be

of

the register, and the

of

data which must

Chapter 5)

MODES

handling is

to

be

to

handle

used with an

as

known

au·

as

be

is

19

RO

Rl

R2

R3

R4

R5

R6

(Hardware Stack Pointer)

R7

(Program Counter)

SINGLE

.3.1

The instruction format crement, test)

Bits to

be

Bits 5 through sists

a) Bits 0 through 2 specify which

OPERAND

ADDRESSING

for

all single operand instructions (such as clear, in·

is:

MODE

,15

" 6 I

OPCOOE------~i~----------~

DESTINATION

***

15

through 6 specify the operation code

ADDRESS

*-SPECIFIES

**'SPECIFIES

-SPECIFIES

----------------------'-

DIRECT

OR

HOW

REGISTER

ONE

OF 8 GENERAL

INDIRECT.

WILL

ADDRES.:;:_

BE

PURPOSE

USED

,,5

REGISTERS

that

executed.

0 form a six·bit field called the destination address field. This con·

of

two subfields:

of

the eight general purpose registers is to be

** *

4 3

***

j

Rn

<!II

I

2.

f~----~

defines the type

0 I

of

instruction

referenced by this instruction word.

b)

. Bits 4 and 5 specifY how the selected register will

be

used

(address mode). Bit

3 indicates direct or deferred (indirect) addressing.

3.2

DOUBLE

Operations which imply two operands (such are

handled by instructions

OPERAND

ADDRESSING

that

specify two addresses.

as

add, subtract, move and compare)

The

first

operand is called the source operand, the second the destination operand. Bit assignments source and destination address registers. The

Instruction format

fields may specify different

for

the double operand instruction

mOdes

and different

is:-

in

the

20

OP

CODE

15 12

SOURCE

ADDRESS

DESTINATION

***"SPECIFIES A

ADDRESS

*-DIRECT/DEFERRED

**-SPECIFIES

\11

HOW

GENERAL

**

MOllE

1·1

10

BIT

SELECTED

*

9 B

t

FOR

SOURCE

REGISTERS

REGISTER

**-

Rn

AND

**

MODE

6,

,5

DESTINATION

ARE

TO

BE

*

i@1

4 3 2

f

ADDRESS

USED

***

Rn

0,

The source address -field is The destination is used similarly, and locates the second operand and For example, the instruction tion A to contain

the contents (destination operand) of location

the result

of

I

used

to

select

the

source operand, the first operand.

ADD

A,B adds the contents (source operand)

the addition and the contents

B.

After execution B will

of

A will

be

unchanged.

the

result.

of

loca·

Instruction mnemonics and address mode symbols are sufficient for wntmg machine language programs. version to binary digits; this

The

programmer

is

accomplished,automatically by the

need

not

be

concerned about con-

PDP-ll

as-

sembler.

in

Examples in this section and further PDp·ll

instructions:

Mnemonic Description

CLR

CLRB

clear (zero the specified destination) 0050nn

clear byte (zero the byte in

this chapter use the following sample

Octal Code

the

specified

1050nn

destination) INC increment (add 1 INCB

increment byte (add 1

to

contents

to

the

of

destination)

contents

of

0052nn

1052nn

destination byte) COM

,complement (replace the contents

by

destination

each

0

their logical complement;

bit

is set and each 1

bit

is cleared)

of

the

0051nn

COMB

AOD

complement byte (replace

the

contents

of

the 1051nn

destination byte by their logical complement;

each

Obit

is set and each 1

add (add source'operand

operand and store the result

bit

is cleared)

to

destination

at

destination

..

address)

21

06mmnn

3.3

DIRECT

The following table summarizes the four basic modes used with direct

ADDRESSING

a~dressing.

DIRECT

Binary Name

000 010

100

110

3.3.1 Register Mode

With register mode any tors ware registers, within the processor, the general registers operate

and provide speed advantages when used variables. The PDP-l1 assembler interprets and assembles instructions form or

sembler syntax requires

Register Autoincrement

Autodecrement

Index

of

and the operand is contained in the selected register. Since they are haJd-

OPR

Rn

number and

as register mode operations.

OPR

RO=%Q

the general registers

is used

to

that

a general register be defined as follows:

(%

sign indicates register definition)

MODES

Assembler

Syntax Rn (Rn)+

-(Rn)

X(Rn)

OPR

represent a general instruction mnemonic.

Register contains operand Register is used as a pointer

sequential cremented

Register is decremented and then used

Value X is added duce address ther X

Rn

l!1ay

be used as simple accumula·

for

operating

Rn

represents a general register name

Function_

data

as

a pointer.

to

of

nor

on

operand. Nei·

(Rn) are modified.

at

frequently-accessed

then

(Rn) to pro·

high speeds

Rl=%l

. R2 = %2, etc.

Registers are However R6 and

Register Mode Examples (all numbers in octal)

typically referred

R7

are also referred

Symbolic

to

by name

Octal Code . Instruction Name

as

RO,

RI,

to

as

SP and PC, respectively.

R2, R3,

R4,

R5,

R6 and

of

to

in·

the As-

R7.

1.

Operation: Add one

INCR3

005203

Increment

to

the contents

22

of

general register 3

Re

Rt

10

0 0 0 t

~,~'~5~::~:~::~:~::~'_-_~_-_-_~_-_~_~~6~,~,5~

OP

COOE

IINC(

D£STlNATtON

0052U

FIELD-------------'

*

-DIRECT

**

-REGISTER

.0

--I

ADDRESS

MODE

tOO

** *

I 0 0 I 0

lOt

~4~3~~2----~0~,

t =

j

R2 R3

;"

R4

. R5

R6(SP)

R7(PC)

2.

ADDR2,R4 060204

Operation:

BEFORE

R2

I

000002

R4

LI

_....:0;,:,000:;.:..04---,

3. COMBR4

Operation:

105104

One's complement bits general registers are used, byte instructions only operate on bits

BEFORE

R41

022222

3.3.2

Autoincrement

This mode provides

ments

of

ister

for

quential·location~

ing address

this

a table

to

be

the address

bytes, by

two

and stacks.

the

next operand

mode~is

Mode

for

automatic stepping

of

operands.

for

words, always by two

The autoincr.ement mode is especially useful.

It

will access an element

completely general and may be used

It

of

the-

operand. Contents

in

the

Adr.l

Add the contents

. I

of

AFTER

RZI

000002

R4

Lf

_....:000.:.:.;:,00:,:6---1

R2

to

Complement Byte

(}.7 (byte)

()'7; i.e. byte 0

AFTER

R41

022155

OPR

(Rn) +

of

assumes the contents

a pointer through sequential ele-

of

the selected general

of

forR6

of

registers are stepped (by one

and R7)

a table and then step the pointer

table. Although most useful

for

a variety

the

contents

in

R4.

of

the register)

to

address the next

for

array process-

for

table handling,

of

purpo~.

of

R4.

(When

reg-

sa-

to

23

Autoincrement

Symbolic Octal Code Instruction Name

Mode Examples

1.

OPeration:

BEFORE ADDRESS

20000

I.-.....;.00;.:502.=;5_...J

30000

...

(_..;.",-,,1..;."..;.6_-,

2.

Operation:

BEFORE

AOORESS

20000

(

111

30000

1

30002

CLR

CLRB

105025

(R5) +

SPACE

(R5) +

SPACE

"116

005025

Use contents

Clear

of

R5 as the address

of

Clear selected operand and then increment the

of

R5

1

20000

30000

Clear Byte

of

by two.

AFTER ADDRESS

SPACE

I

005025

I.----:OO.::.:O:.:OOO.:.=..---,

R5

as

the

address

R5

... ( __

of

contents

REGISTER

030000

105025

Use contents

Clear selected byte operand and then increment

R5(

the contents

REGISTER

030000

(20000

of

R5

AFTER

ADDRESS

by one.

105025

111

t

SPACE

115 ( 030001

:000

:=1

the operand.

REGISTER

:.~3?O~02_

......

the'operand.

REGISTER

3.

Operation:

BEFORE

AllDRESS

10000

1000021

ADD

062204

010000

(R2)+,R4

SPACE

062204

The contents

operand which is then incremented

REGISTERS

100002

~2

1

010000

1141

24

Add

of

10000

100002

R2

is

AFTER

1

(

are

added

by

A00RE5S

062204

010000

used

as

to

the contents

two.

SPACES

the address

of

REGISTERS

100004

1121

020000

R41

of

R4.

the

R2

1-

3.3.3

Autodecrement

Mode

OPR-(Rn)

mode is useful

This of

the selected general register are decremented (by two

one

for

~hoice

byte instructions). and then used as

of

postincrement. predecrement features

decisions. but were intended

(See Chapter 5

Autoclecrement

for

processing data in a list

to

for

complete discussions

Mode

Examples

in

the

for

facilitate hardwa re I softwa re stack operations

of

stacks).

Symbolic Octal Code Instruction Name

1.

Operation:

INC-(RO)

005240

The contents

Increment

of

RO

used as the address

by

1000

In74

as

the address

one.

AFTER

I I

of

AOORESS

RO

BEFO~E

AOORESS

1000

I

In74(

2~

Operation:

SPACE

005240

000000

INCB-(RO)

increased

REGISTERS

017776

Rill

105240 Increment Byte

The contents used byte is increased by one.

reverse direction. The contents

for adc;lress· the

are decremented by

of

005240

000001

word instructions. by of

the

PDP·1

operand. The

i were npt arbitrary

two

and

the operand. The operand is

SPACE

Rei

REGISTER

017n4

are decremented by one then

of

the operand. The

operand'

BEFORE

AOORESS

1000

I

000

17n41

17776

3.'

Operation:

'05240

!

ADD

SPACE

.

000

I

-(R3).RO

REGISTER

o,n76

Rill

064300

The contents used as a pointer added

'000

,n74 I

l7n6

Add

of

to

the contents

25

AFTER

AIlORESS

SPACE'

'05240

I

00'

~

000

R3

are decremented by 2 then

to

an operand (source) which

of

RIll

RO

(destination operand).

REGISTER

0'7775

is.

10020

BEFORE

AODRESS

I

064300

SPACE

RfJ

R31

I

REGISTER

000020

077776

10020

AFTER

AOORESS

I

064300

SPACE

R01

R31

REGISTER 0000070

077774

777741

71776

3.3.4 Index

The contents of

000050

Mode

the' selected general register, and struction word, are summed the selected register may

allowing random access

thus can then be modified

be

by

program to access data in the table. Index addressing in-

structions are of the form

in

the

memory location following

eral

register.

Index

Mode

Examples

Symbolic

1.

<i

CLR

200(R4)

Operation:

~EFORE

AOORESS

SPACE

'~o~

'022

'024

000200

R41

777741

11776

OPR

X(Rn)

to

form the address

used as a base for calculating a series

to

elements

OPR

X(Rn) where X is the indexed word and is located

Octal

of

the-

instruction word and

Code"

005064

000050

an

index word following the in-

of

the operand. The contents

of

data structures. The selected register _

Rn

is the selected gen-

Instruction Name Clear

000200 The address

ding

of

200

to the contents

the operand is determined by ad-

of

R4.

The location is

then cleared.

REGISTER

00'000

AFTER"

AOORESSSPACE

.~o~

'022 '024

000200

R41

of

addresses,

REGISTER

00.000

'200~

'202

2.

COMB

200(R1)

Operation:

'2OO~

105161 000200

The contents of a location which adding plemented_

Complement Byte

200

to

the contents of

(i.e_

logically complemented)

26

is

determined-by

R1

are one's com- "

BEFORE

AODAESS

SPACE

1020~

1022~

, Rl (

RalISTER

017777

AfTER

AOORESSSl'lACE

"

REGISTER

Rl

11.-_,-01,-7,;-;77,-7_....1

"

20176\

20200

3.

011

000

t::~:~~::j

ADD

3O(R2),20(R5) 066265

Operation:

BEFORE

AOORESS

SPACE

R2(

1022 ()()()OOO

-~

1024

20201

1130

I

000020

000001

1151

.

:~t-I_l:..;;66.;;..:.;Ooo~-i1

000030

000020

The contents of a location which is determined

adding 30 to the contents of contents of a ding 20 at the destination address,

REGISTER

001100

002000

Add

R2

location which

to

the contents.ofR5.

AfTER

AIlORESS

SPACE

are added

is

determined by ad·,

The

ie.

20

R21

1022

000030

1020~

1024

000020

00000I

1130 I

20201

000002

1151

result is stored

(R5~

REGISTER

001100

(00)00

to

by

the

27

3.4

DEFERRED

The four basic modes may also be register mode the operand is the contents deferred mode the contents

In the three other deferred modes, the contents of

the operand rather than the--operand itself. These modes are therefore used

when

a table consists indicating deferred addressing is following table summarizes the deferred versions

(INDIRECT)

of·

addresses rather than operands. Assembler syntax

ADDRESSING

used

with deferred addressing.

of

the selected register is the address

"@"

the selected register, in the register

of

the register selects the address

(or

"(

)"

when

this not ambiguous). The

of

the basic modes:

Whereas

of

the operand.

Binary Name Assembler Function Code

Syntax

in the

for

001

Register Deferred

@Rnor

(Rn) Register contains the address

the operand

01

1 Autoincrement Deferred

@(Rn)+

Register is first used pointer

to

address

a word containing the

of

the operand, then in-

cremented (always by

2;

as

even

for byte instructions).

101

Autodecrement Deferred

@-(Rn)

Register is decremented (always by two; tions)

pointer

address

even

for

and

to

a word containing the

of

byte instruc·

then

used as a

the operand

1 1 1 Index Deferred @X(Rn) Value X (stored in a word follow·

ing the instruction) and (Rn) are added and the sum is used

. pointer

address

to

a word containing the

of

the operand. Neither

as

X nor (Rn) are modified.

Since

each

scriptions

deferred mode is similar to its basic mode counterpart, separate

of

each deferred mode are not necessary. However, the following exam·

de-

pies illustrate the deferred modes. '

Register

Deferred

Mode

Example

Symbolic Octal ClR@R5

005015 Clear

Code

Instruction Name

of

a

Operation:

BEFORE

AOORESS

SPACE

::

...

1-000..,..-100-----1

R5

L-I

_00_'700_---'

The contents

cleared;

A£GISTER

?R

of

location specified in

AFTER

ADORES8

SPACE

::

1-1-000000----1

R5

L-I

R5

REGISTER

_00_1700_--,

are

Autoincrement

Symbolic Octal

Deferred

Mode

Example

Code

Instruction Name

INC@(R2)+

Operation:

B£FCRE

ADDRESS

SPACE

'01O~

'0'2~

'0300

... 1_.;..00:....'.;..010-,--;

Autodecrement

Operation:

IlEFORE

'0'001

10102

10774 '0776

1

Deferred

COM

@-(RO) 005150

AOORESSS"",CE

012345

0,0'00

005232 The contents

used

Operand crementedby

REGISTER

R2 I 0'0300

Increment

of

as

the address

the location specified in

of

is

increased by one. Contents

the address

2.

AFTER

ADDRESS

SPACE

R2 I 010302

'01O~

'0I2~

'0300

1-1

__

0°_'_°'_°_--1

Mode

Example

The contents then

used erand. Operand is one's complemented. (i.e. logically

complemented)

REGISTER

010776

RIll

Complement

of

RO

as

the address

AFTER

·ADORESSs...oE

are decremented by two and

of

the address

'65432

R01

=1

10774

10776

0'0'00

1

of

the operand.

of

R2

REGISTER

of

the

REG'STER

0'0774

R2

are

is in·

op-

Index

Deferred

Operation:

Mode

Example

ADD

@1000(R2),Rl 067201

,~dd

001000

1000 and contents

the address the contents

of

the address

of

which are added

the result is stored in

29

R2

are summed to produce

of

the source operand

to

contents of

Rl.

Rl;

BEFORE

ADORE55

SPACE

Rl

.t020~7201

1022

1024

lO5(i

001000

...

1-OOOOO--2--i

1

R2 1 000100

REGISTER

001234

AFTER

AOORESS

SPACE

102O~67201

1022 001000

1024

.,

.050

1..-_0_0000_2_--1

RI 1 001236

021.

REGISTER

000100

1100 ... 1_00-----C10_5O_-i

3.5

USE

OF

THE

PC

AS A GENERAL

Although Register 7 is a general purpose register, Program Counter

-counter

to

acquire a word from memory, the program counter is automatically in· cremented by executed gram

The are four

- -poSition

or

uses the

PC

responds

of

independent

garding the

for

the

PDP·ll.

two

to

contain the address

the address

PC

of

to

the next. instruction

locate byte data, the

all the standard

these modes with which the

code

(PIC·

PC

these modes are termed immediate, absolute (or immediate

see

1100

If--_OO;..;.;.;;IOS.;;.;O'----I

REGISTER

it

doubles

Whenever the processor uses the program

of

the next word

t9

PC

is still incremented by two.)

PDp·ll

addressing modes. However, there

PC

can provide advantages

be

exeC!Jted.

of

the instruction being

Chapter 5) and unstructured data. When

ferred), relative and relative deferred, and are summarized below:

Binary Code

010 011

Name Immediate Absolute

Assembler Function

Syntax

#n

@#A

Operand follows instruction

Absolute

Address folows

struction

of

110

Relative A

Address

A, struction, follows the instruc· tion.

111

Relative Deferred

@A

Address

address

of

A, struction follows tion.

in

function as the

(When the pro·

for

handling

reo

de-

in·

relative

to

the in-

location containing

relative

to

the in·

the

instruc·

The reader should remember described in

3.3

and 3.4,

but

that

the

general register selected is

counter. When a standard program is available

able

to

load

it

into

ish the relocation

different areas

of

a program very efficiently through the use

of

core and run

special effect modes are the same

R7~

the program

for

different users,

it

there.

it

often is helpful

POP·II's

can accompl·

of

position inde-

30

as

modes

to

be

pendent code (PIC) which is written struction and

its

objects are moved in such a way between them is not altered, the same offset relative to the positions in memory. Thus, location:

The ularly

PIC

is discussed

PC

also greatly facilitates the handling

true of the immediate and relative modes which are discussed more fully in

PIC

in

by

using the PC addressing modes.

that

the relative distance

PC

can

usually references locations relative to the current

more detail in Chapter

of

5.

unstructured data. This is partic-

Paragraphs ,3.5.1 and 3.5.2.

3;5.1 Immediate Mode

OPR

#n,DD

If

be

used in all

an in-

Immediate mode is equivalent to using the autoincrement mode with the

PC.

. provides time improvements for accessing constant operands by including the

constant in the memory location immediately following the instruction word. Immediate Mode Example

Symbolic

ADD

#10,RO

Octal

Code

062700

Instruction Name Add

000010

Operation:

BEfORE

ADDRESS

1020

~'"

1022

1024

SPACE

0000,10

The value 10 is located in the second word instruction and is added

to Just before this instruction is fetched and cuted, the struction. increments the mode is is used

ond word cremented by two

REGISTER

000020

Rei

PC

I

001020

PC

points

to

The

processor fetches the first word and

PC

27

(autoincrement the PC). Thus, the

as

a pointer

of

the instruction) before being in-

AFTER

1020 1022 1024

the first word

by two. The source operand

to

fetch the operand (the

to

point

to

the next instruction.

ADDRESS

SPACE

062700

000010

........--PC I

the contents

of

REGISTER

000030

Rei

1024

of

the

of

RO.

exe-

the in-

PC

sec-

3.5.2 Absolute Addressing'

OPR

@#A

It

This mode is the equivalent ing the

PC.

The contents

of

address (i.e.,

the operand. Immediate data is interpreted

an

address that remains constant

of

immediate deferred

of

the location following

sembled instruction is executed).

or

autoincrement deferred

the

instruction are taken

as

no

matter where in memory the

31

an

absolute address

as

usthe

as,

Absolute Mode Examples

Symbolic

Octal Code Instruction Name

1.

CLR@#l100

005037

Clear

001100

Operation:

BEFORE

ADDRESS

20 22

1100 ,

1102

2.

SPACE

"'-

PC

t77777

,-

ADD

@ # 2000,R3 063703

Clear

the contents

1100 , 1102

20 221 241

AFTER

AOORESS

1

Add

of

005037

001100

000000

lo~ation

SPACE

/PC

002000

,Operation: Add contents of location 2000

2000

20 22 24

BEFORE

AOORESS

I

063703 002000

000300

SPACE

"

,

R31

PC

REGISTER

000500

2000

AFTER

AOOR

ESS

SPACE

20

063703

22

002000

24

000300

I

/PC

1100.

to

R3.

R31

REGISTER

001000

3.5.3 Relative Addressing OPR

A

OPR

X(PC), where X

is

the ,location

This mode is assembled as index mode using

which is stored

lation, dress

of

the operand, but the the address code (see PC.

Chapter

When

of

instructions are

in

the second

the operand. This mode

5)

since the location referenced is always fixed relative

or

third word

number

to

be relocated, the operand ismOlled

which, when added

is

useful

amount.

32

or

of

A relative

R7. The base

for

to

the instruction.

of

the instruction, is

the address calcu·,

to

the (PC), becomes

writing position independent

not

by

the same

the ad·

to

the

Relative

Addntssing Example

Symbolic

octal

Code . Instruction Name

Operation:

8ERlRE

AIXlAESS

1024

=1

1026

10U)O t

INCA

SMCE

:::

000000

I'

I.

005267 000054

To increment location tion

immediately following instruction

ded

to

are increased

PC

Increment

(PC)

to

produce address

by

one.

AFTER·

ADOAESS

102O~.

1022 t024

1026

1\

00 I 000001

3.5.4 Relative DefeTed Addressing

OPR@A

..

OPR@X(pc), where x is location containing address

.

This

mode

struction, and, rather tJ:Iatthe

.

Relative

DefeTed

__

is

similar

to

the

when

added

Mode

Symbolic Octal

relative mode, except

to

the

PC,

address.

Example

contatns the address

of

the

struction.

operand .

Code

or

Instruction Name

A,

contents

SPACE

000054

of

that

the second-word

of

the

A.

.

_PC

A,

relative

address

of

memory loca·

word·

Contents

to

of

the

are

the

oper·

of

ad-

A

in·

.in-

CLR@A

Operation:

--

BUORE

ADORESS

SPACE

1022

000020

~~'

_

.024

OlCMl!O

1044

1

IQIOOJ

.oooiif

005077

000020

Add second word addtess

PC

&-1044

Clear

of. address

AFTER

10~1

.'022

1024

W>441

-t

33

of

instruction

of

operand. Clear operand,

ADDRESS

SlW:E

005057

000020

0.0100

00000o

to

~PC

l

PC

to produce

3.6

USE

OF

STACK

The processor stack pointer

POINTER

used

for the stack operations related

Register 6

"pops" items has a special attribute: autoincrements and autodecrements are always done in

steps of two. Byte operations

unmodified .

The

modes

"pushes"data on to the .stack and autoincrement with Register 6

data

off

on

following table is a concise summary of the various POP·l1 addressing

the stack. Index mode with the

the stack. Since the

.use

of

stacks is explained

AS

GENERAL

(SP,

Register

SP

is

used

using the

Addressing Modes Summary

REGISTER

6)

is

in

to

by the processor for interrupt handling,

SP

in

most

program nesting. Autodecrernent with

SP

in this

way

detail in Chapter

cases

the general register

permits random

simply

leave

odd addresses

5.

access

of

it

Binary Code

000

Name

Register

010 Autoinerement

100 Autodecrement

110 Index

DIRECT

Assembler

Rn (Rn)+

-eRn)

X(Rnl

MODES

Syntax

Function

Register.contains operand·

Register'contains address of op· erand. Register contents cremented after reference.

Register contents decremented .

before reference register con· tains address

Value X (stored in a word follow··

ing the instruction) is

(Rn) to produce address'of

and. Neither X nor (Rn)

modified.

of

operand

added

opec·

in·

to

are·

.

34

DEFERRED

MODES

Binary

Code

001

011

101

111

Name

Register Deferred

Autoincrement Deferred

Autodecrement

I

ndex

Deferred

Assembler

Syntax

@Rn

or (Rn)

@(Rn)+

@-(Rn)

@X(Rn)

Function

Register contains the address

the operand

Register pointer address of the operand, then cremented (always for byte instructions)

Register is decremented by two; tions) pointer address of the operand

Value X (stored in a word following the instruction) and (Rn) are added and the sum is pointer address

X nor (Rn) are modified

is

first

used

by

2;

(always

used

as

even

as

to

A word containing the

even

for byte instruc-

and then used as a

to

a word containing the

to

a word containing the

of the operand. Neither

of

a

in-

a

010 011

110

111

Immediate Absolute

Relative

Deferred

PC

ADDRESSING

#n

@#A

A

@A

35

Operand follows instruction Absolute address follows in-

struction Address of

struction, follows the instruction.

Address of address struction follows the instruction.

A,

relative to the in-

location containing

of

A,

relative to the in-

36

PART

CHAPTER

I

4

4.1 INTRODUCTION' This chapter describes the

Single Operand

General Shifts

~~::i:

Double Operand

Arithmetic Instructions

Logical Instructions

Precision

(4.4)

I(tructions

(4.5)

PDp·ll

Program Control Instructions (4.6)

Branches Subroutines Traps

~

Miscelleneous

Conditien

Code

(4.7)

Operators

(4.8)

INSTRUCTION

instructions in the following· order:

SET'

The specification code, a diagram showing the format scribing its execution and the effect on the condition codes, description, special comments, and examples.

MNEMONIC: This is shown at the top left hand side instruction has a byte equivalent, the byte mnemonic is also shown.

INSTRUCTION

tal

op

cOde,

tions the most significant

for

each instruction includes the mnemonic, octal code, binary

FORMAT:

the binary op code, and

A diagram accompanying each instruction shows the oc·

bit

(bit

of

the instruction, a symbolic notation de·

bit

assignments. (Note

15) is always a

1.)

of

the page.

timing

information, a

When

that

in byte instruc·

37

the word

OPERATION: The operation tion. The following symbols are used:

()

= contents

src = source address

dst

= destination address

loc = location

.=

becomes

• =

"is

popped

'f = "is

A = boolean AND v

..,.

~=

Reg

B =

pushed onto

= boolean

= exclusive

boolean

or

R = register

Byte

OR

not

of

from

of

each instruction is described with a single nota·

stack"

Instruction Timing

The

PDp·l1 processor operations are sum and/or quired times stated are subject

is an asynchronous processor in which, in

of

a basic instruction

destination operands. The following table shows

for

the

various modes

overlapped. The execution

time

and the time

of

addressing source

to

±20%

variation.

to

determine

time

and

Addressing Format Timing

many

cases, memory and

for

an instruction is

and

fetch

the

addressing times

destination operands. All

the

source.

re-

(src

or

dst)

R

(R)ot@R

(R)+

-(R)

@(R)+

@-(R)

BASE(R) @BASE(R)

*

dst

time

is

CoMPare,

Bit

TeST,

none

: referencing bytes

0.5

CoMPare Byte

Test,

Bit

Test Byte

or

TeST

of

which ever modify

or

@(R)

JIS.

less than listed

Byte

the

at

odd addresses adds

time

if

instruction was a

destination word.

0.61'5

38

src(ps)**

o

L5

1.5

2.7

3.9

tosrc

and

dst

dst(ps)

o

1.4*

2.6*

3.8*

times.

*It

4.2

INSTRUCTION-FORMATS

The major instruction formats are:

Single Operand Group

OF'

15

Double Operand Group

OF'

Code

12 II

Operators

15

Condition

o

Register-Source

Subroutine Return

or

Destination

,Code

,0

dst

,

6 5

dst

6 5

2

I

Src/dst

,

o

Branch

15

o

,

o

OP

Code

I

o

8 7

o

offset

-,

o

39

4.3

BYTE

The

byte operands. addressing ment

INSTRUCTIONS

POP-ll

processor includes a full complement of instructions

Since all

is

straightforward. Byte instructions with autoincrement

POP-ll

addressing is byte-oriented, byte manipulation

direct addressing cause the specified register

that

or

to

be

modified by one to point

manipulate

autodecre-

to the next byte of data. Byte operations in register mode access the low·order byte

of

the specified_register. These provisions enable the either a word dresses in core memory

or

byte processor. The numbering scheme

is:

BYTE

1

BYTE

3

BYTE

0

2

POP-ll

for

word and byte

2000 2002

to

perform

as

ad-

The most significant bit

(Bit

15)

of

the instruction word is set to indicate a byte

instruction. Example:

Symbolic

CLR ClRB

Octal 005000

105000

NOTE·ISP

ISP

. The Instruction Set Processor (ISP) notation has been used with each instruction. is described in detail in Appendix users who wish to gain an in depth understanding understanding

It

is a precise notation for defining the action

ISP

is

not

essential to understanding

C.

It

was

inclLided

of

any instruction set and

for

the benefit

of

each instruction. However, POP-ll

instructions.

40

of

POP-ll

4.4

SINGLE OPERAND INSTRUCTIONS

General:

Shifts:

Multiple

Precision:

Rotates:

4.4.1 Single Operand General Instructions

CLR CLRB

ASR ASRB ADC

ADCB ROL

ROLB

DEC DECB

ASL ASLB SBC

SBCB ROR

RORB

41

INC INCB

SWAB

NEG NEGB

TST TSTB

COM COMB

CLR CLRB

2.3

p.s

Clear dst

(dst).O

N:

cleared

Z:

set

cleared

o

o o

15

Operation:

Condition Codes:

V:

C:

Description: Word: Contents

roes. Byte: Same

Example:

(Rl)

Before

= 177777

NZVC

11

ISP:

CLR:

DI

~

0;

N·

...

0;

Z +-

1;

v

...

0;

C~O

CLRB:

Db'

....

0;

N ~

0;

z

.....

1;

V

....

0;

C ~ 0

o

d d

6

5

of

specified destination are replaced with

CLR

d d

Rl

d d

After

(Rl) = 000000

set

Bet

NZVC

0100

Z

11

clear

cZeaP

D~

D,

N~

V.,

N, V, C;

C,

n050DD

o

ze·

42

2.3 ps

DEC DECB

Decrement

dst

o o

15

Operation: Condition

Codes:

Description:

Example:

ISP:

DEC:

r

....

D'

-:-1;

T<15>;

(r<15:0> -0) ~ (Z ~ 1

(r<15:0'>.

D

..

r

DECI:

r

..

Db'

-1;

N

..

1<1>;

(r<7:D> -0)

(r<7:

0>

..

Db

... r tzransmit

(dst).(dst)-l

N:

set

if

Z:

set

if

V:

·set

if

C:

not affected

Word: Subtract 1 from the contents Byte:

Same

= 000001

(R5)

else

)

77777

-=

(V'"

8

nut

• (Z

1778) ~ IV'" 1

1

.. 1 else Z ...

else V ..

0"

o d d

6 5

result is

<0;

cleared otherwise

result is 0; cleared otherwise

(dst)

was

100000; cleared otherwise

DEC

R5

Before

(R5) = 00000o

NZVC

1000

NBult

is

difference

negative?

Z ~ 0);

else

0);

aero?

V

....

0);

overflorJ

if

Nsu.lt

is

diffel'ence

if

result

largest

to

largest

to

D

0);

tnmsmit

result nsgative?

aero?

OIJel'fiOlJ

d

of

the destination

After

NZVC

0100

of

D-l

positive

number

of

D-l

positive

number

n053DD

d

o

43

INC INCB

2.3

p.s

Increment dst

+ 1

one

0 0

0;

to

1°/1

1

°

15 6 5

Operation:

Condition Codes:

Description.:

0 0

°

(dst~(dst)

N:

set

if

Z:

set

if

V:

set

if

C:

not affected

Word:

Add

result is

(dst) held 077777; cleared otherwise

Byte: Same

Example:

Before

'"

000333

(R2)

NZVC

0000

ISP:

INC.

r ...

D'+l;

...

'1'<15>;

INCB:

r ...

(r<15:0:> ~ 0)

(r<U:

D ... r

D1t+lj

N'"

(r<7:U> • 0) (r<7:

Db'"

(t>

r<7>i

0>

r

...

:)

1000008)

=t

200

S

(Z

...

·1

else

z ...

Z ...

else

V ...

0);

O)j

V ...

0);

0)

..

(V ... 1

(Z

...

1

else.

)

~

(V

... 1 -else

d d

<0;

cleared otherwise

contents

of

destination

INC

R2

(R2)

result

i6

8W1l

is

if

largest

:N8Ult

sum

if

largeat

""8utt

of

negative?

zero?

j

overflow

transmit

"MBult

nsgative?

ove:r>f'lOLJ

transmit

D+l

to

Drl

to

'"

000334

negative

D

negative

D

d d

d

After

NZVC

0000

numbep

numb~_l'

n052DD

d

0

44

2.3

J1S

NEG NEGB

Negate dst

10/1

I °

15

-Operation:

Condition Codes:

° °

°

(dst).

Z:

V:

C:

N:

set set set cleared

-(dst) if

the result

if

result is 0; cleared otherwise

if

the result is 100000; cleared otherwise

if

Description: Word: Replaces

two's complement. Note two's complement notation the most negative number has no

positive counterpart).

Byte: Same

Example:

(RO)

= 000010

NZVC

0000

ISP:

NEG:

r

...

-D';

+-

r<lS:>;

(r<15:0> -0) ~ (Z

(1."<15:0> =

(r<15:

0>

;,I"

D ... r -tPansmit

NEGB:

r·t-

-

Db';

N

...

r<7>;

(r<7:0>

""

(r<7:

0>

...

(r<1:.1l>"

Db'"

r

+-1

else

)

100000

~

(v'" 1 else v ...

a

0) ~ (C'" 0 else

)

200

=10

(V'"

~

(C'"

else

0

else

S

0)

=10

c'"

z

C ...

...

0);

1);

0);

V'"

1);

:0

is

d d d d

°

6

5

<0;

cleared otherwise

the result is 0; set otherwise

the

contents

of

the destination address by its

that

100000 is replaced

NEG

RO

Before

(RO) = 177770

result

is

negative

of

to D

to

D

of

D

O);overfZOb)?

0);

negative?

zem?

carry?

t:6suZt

negative?

aero?

O71e'1'f/.ow?

=-ry?

transmit

result

is

l'esuJt

negative

After

NZVC

1001

n0054DD

d d

°

Q;'

itself -(in .'

45

TST 1ST8

1.8

2.3

p.s p.s

if

Mode

0

lest

dst

1°/1

0

1

15

Operation:

Condition Codes:

,~

Description:

Example:

ISP:

TST:

r ...

DI

...

0;..

N ~ r<15>;

(r<lS:O>

- 0) ~ (Z'-1 else

v'"

0;

c ~ 0

TSTB:

r

....

Db'

..

0;

N'"

r<7>;

(r<7:

0>

:II

V'"

0;

C~O

0 0 0

(dst).

(dst)

N:

set

if

Z:

V:

C:

the result set if result is 0; cleared otherwise cleared cleared

Word: Sets the condition codes tents of the destination address

Byte: Same

Before

(Rl)

= 012340

NZVC

0011

0);

....

1

else

Z

....

0);

, : '

is

d d

6 5

<0;

clearedotherwi~

Nand

TST

(Rl)

d

I

Z according to the con·

Rl

= 012340

NZVC

0000

NBult

is

nega1;iTJe?

zero?

otear

2'esuZt

nsgative?

3em?

otear

diffBl'e7ICe

Vande

is

,diffeNnos

Vande

d

After

of

n057DD

d d

0

DandO

.46

2.3

ps

COM

COMB

Complement dst

o 0

15 6

Operation: Condition

Codes:

N:

Z:

V:

C:

0 0

(dst).~(dst)

set

if

most significant

set

if

result is

0;

cleared

set

Description: Replaces the contents

ical complement (each

1 is cleared)

to Byte: Same

Example:

Before

(RO)

= 013333

NZVC

0110

ISP:

CI»I:

r ...

-.

D';

Dext

N"

r<15>;

(.-<15:0> -0)

V'"

0;

c

....

1.

D~r

..

(Z ~ 1

eloe

Z ~ 0);

M.ult

negative?

"'PO?

a'tea,. V

set

t,.."..",nt

com:

r'P-,Db

N

....

(r<7:0>

V'"

c

~

Db ~ r

'

r<1>;

•

0) ~ (Z'" 1 else

0;

1;

z ...

0);

result

nsgative?

aero?

atea.. V

set

~t

d d

: 0 1 I

d

5

bit

of result is set; cleared otherwise

d

d'

I

cleared otherwise

of

the destination address by their log·

bit

equal

to

0 is set and each

COM

RO

After

(RO)

= 164444

NZVC

1001

i.

C

""",,1.ement

result

i.

""",,1.ement

""Bult

to D

to

of

D

of

D

nOSlDD

d

0

bit

equal

450 ns

47

4.4.2 Shifts

Scaling data

The sign der

bit

the following examples, are lost.

by

factors of two is accomplished

ASR

- Arithmetic shift right

ASL

- Arithmetic

bit

(bit

is

filled with 0 in shifts to the left. Bits shifted out of the C-bit,

shift

left

15)of

the operand is replicated in shifts to the right.

by

the shift instructions:

The

as

shown in

low-or-

48

2.3p.S

3.5

p.S

if

odd

byte

ASR ASRB

Arithmetic Shift Right

lOll,

t5

Operation:

COndition

Description:

ISP:

ASR,

r

....

D'/2;

c

...

Dr::.G'>-;

N'"

1'<15>;

(r<lS:Ct> •

(R • C) ~ (V"

D~r

ASII:

;"Db'/2;

c

~

Dl><Il>J

.....

1<1>;

(1<7:11> -

(11

Db

0 0 0 I

(dst).(dst)

Codes:

N: cleared otherwise Z: V:

by

C: Word:

is

ASR Word:

ne:.:t

0)

:=I

(Z ... 1

IMJlt

0)

_ (Z ~ 1

at

C) 1:$

(V'" 1 .1

..

r,

dst

o 0

Odddddd 6 5 0

shifted

one

place to the "right

set

if

the high-order

set

if

the result =

loaded

from the

bit

of

0;

clearecLotherwise

Exclusive

OR

the result is set (result < 0);

of

the N-bit and C-bit (as

the completion of the shift operation)

loaded from low-order

bit

of

the destination

Shifts all bits of the destination right one

replicated.

performs

The

C-bit is loaded from

signed

division of the destination

Byte:

....

utt

i8

Darl7J

...

-'-

el

..

1 e1a. V ...

ela.

••

V'"

Z ...

0);

z ~ II);

0).

0);

J'l6gtJti,11fJ?

8"ro?

....

8utt

DtU'I'/J

......

...

gaU",,?

INPO?

-fit>.>

i8

is

bit 0 of

D/2

.....

tease

D/2

i....

wast

"Eo:aluei"" OR"

n062DD

set

place.

Bit

15

the destination.

by

two.

.igm.fi.oant

significant

bit

of

If

aM

C

49

ASL

ASLB

2.3

3.5

ps ps

if

odd byte

Arithmetic Shift

lOll,

15

Operation: Condition

left

0 0 0

Codes:

dst

1 0 0

(dst~(dst)

N:

set

shifted one place to ,the left

if

high·order

6 5

bit

of

the result is set (result < 0); cleared

n063DD

otherwise

Z:

set

if

V:

the result ,= 0; cleared otherwise

loaded with the exclusive

OR

of the N-bit and

Cbit

by the completion of the shift 0peration)

C:

loaded

with

the high-order bit

of

the-

destination

Description: Word: Shifts all bits of the destination left one place.

loaded with an the most significant signed multiplication

O.

The

C-bit

of

bit

of

the status word is loaded from

of

the destination.

the

destination.by 2 with overflow in·

ASL

performs a

dicati'on. Byte: Same

Word:

Byte:

0':'L-I

=-,'---'-~'

15

=:b"

=!!,........--'-."......r-{~..:..I

ODD

ADDRESS

e

L-::7....L.--!EVE=N~ADIlRESS==L-....L..---'--::-'0

I I I I

ISP:

ASL, ,

r - D'<lS>t:D'<1:3:O>clt;

C'" D <14>;

N'"

r<15>;

(r<15:0> -0)

(N

e C) =

D

~

ASLB:

r'"

C

l

Db'<1>CDb

...

Db<6>i

N - r<.7>;

(r<1:0> = 0)"

eN

e C) =

Db

~

= (Z

(V

....

r

<S:O>ci);next

nes.t

(Z"'1

(V"

r

.... 1 elae Z ..

1

else

V"

elae

Z,'"

1

elae

v

...

0);

N8Ult

bit

.queesed

negative?

ael'O?

overfl,ow

tl'a7umri t

:Nsu.l.t

bit

Bquseaed out

negati1Hl?

aero?

O1Hl!'{to6>

tl'a7umrit

is

DX2

ou.t

is

nEzcZu.sive.

""

...

tt

is

'DX2

iB

"k<>u,.sive OR"

""Butt

to

c

ORn of

to

D

to

c

to

pf

D

o

Bit

N

and

N

and

(as set

0 is

0

1-

C

50

4.4.3

Multiple Precision

It

is

sometimes necessary to do arithmetic on operands considered words or bytes. The PDP·l1 makes special provision for instructions

ADC

(Add Carry) and

SBC

(Subtract Carry) and their byte equiva·

such

as

multiple

operations with the

lents.

For example two 16·bit words may be combined into a 32·bit double precision

word and added or subtracted as shown

OPERAND

RESULT

I

31

I

31

A1

81

below:

32

BIT

WORD

~

16

16 15

,

15

A0

80

15

I

0

,

I

O.

I

0

Example:

The addition of

-1

(Rl)

ADD

Rl,R2

ADC

R3

ADD

R4,R3 ;Add high order parts

-1

and

-1

could be performed

as

follows:

= 37777777777

= 177777 (R2) = 177777 (R3) = 177777 (R4) = 177777

;Add low order parts ;Add carry to high order part

1. After

2.

3.

~ .

4. Result is 37777777776 or

(Rl)

and (R2) are added, 1

ADC

instruction adds C bit to (R3); (R3) = 0

(R3) and (R4) are added

-2

is

loaded into the C bit

51

ADC ADCB

2.3

p.s

Add

Ca

rry dst

1°/'

1

° °

°

15

Operation: Condition

Codes:

Description:

Example:

ISP:

ADC:

r

....

D' + C;

(r<15:0> = 0) (r<15: (r<15:

D ~ r

ADell:

r ...

Db'

N

....

(r<7:0> -0) ~ (Z'" 1 e18e Z .. (<<:7: 0> •

.

(r<7:0>.

Db

~

0> =

1000008)

0> =

0)

+ C; nex.t

1"<7>;

200

0)

r

8

1\

..

1\

)

(Z ~ 1

(0-1)

1\

(0-1)

n05500

d-

d

(dst).(dst) N:

set

if

Z:

set

if

V:

C:

Adds

result =

set

if

(dst)

set

if

(dst)

the contents

0 0

+ (C)

result

<0;

cleared otherwise

0;

cleared otherwise

was

077777 and fC)

was

177777 and (C)

of

d d d

5

6

was

1;

was

cleared otherwise

1;

cleared otherwise

theC-bit into the destination. This

d

0

mits the carry from the addition of the low-order words to

carried into the high-order result.

Same

Byte:

Double precision addition may struction ADD ADC ADD

1\

(0=1)

sequence: AO,BO Bl Al,Bl

else

Z

~

(0=1) ~ (V ~ 1

..

(C ~ 1

..

(V ~ 1

..

(C ~ 1

.ls.

0);

eloe

0); e1.e

c ~ 0);

e1

••

C ~ 0);

V ~ 0);

V "

be

done with the following in-

; add low-order parts ; add carry into high-order ;

add

high order parts

negative?

1!6l"O?

0);

overfiOlJ

if

largest

troanmIrit

,"""uZt

to

negative?

aero?

overj'tOlJ

if

"largest negative

troanmIrit ""Butt

to

negative

D

number

~r

per-

be

52

2.3

pS

SBC SBCB

Subtract Carry

1011

15

Operation: Condition Codes:

I °

ctst

° °

(dst~(dst)-(C)

N: Z:

V:

C:

°

set

if

result set if result 0; cleared otherwise set

if

cleared

<0;

result is 100000; cleared otherwise

if

result is 0 and C =

°

6 5

cleared otherwise

Description: Word: Subtracts the contents

tion. This permits the carry order words to

be

subtracted from the high order result. Byte: Same

Example: Double

precision subtraction is done

SUB

AO,BO

SBC

B1

SUB

AI,SI

I5P:

SBCB:

r

~

Db' - C;

T<7>j

nexc

= (Z

)

8

=

4-

(V

1

else Z .(-

of- 1

else

Nt-

(r<7:0> = 0) (1<7:0> = 200 (r<7,0> ~ 0) A (0=1) ~ (C ~ 0

Db - r

V+-

else

0);

0); C ~ 1);

result

negative? aero?

ovel'[lOlJ?

t:t'ansmi t

d d

1;

set otherwise

of

the

from

the subtraction

i8

differencB

result

n056DD

d d

d

d I

°

C·bit from the destina-

by:

to

D

of D and

of

two low-

part

C

of the

53

4.4.4

Rotates

The rotate instructions operate on the destination word and the C

bit

as

thoug-h they formed a 17·bit "circular buffer'. These instructions facilitate sequential bit testing and

detailed bit manipulation.

54

'2.3

3.5

fJS

ps

Rotate

if

odd byte

Left

15

dst

ROL ROLB

n061DD

o

I

0 0 0 d d d d d

I

6 5 0

I

d

OperatIon:

Condition Codes:

Description:

Example:·

I

15

1

ISP:

•

BOL:

r<:16:D>"

III·

r<1S>;

(...:15:11> -

c~

...

(N

n'<ls:o>a:;

0)

r;

next.

$ C) =-(V

(dst).(dst)

N:

set

rotated left

if

the high·order bit of the result word is

one

place

(result < 0): cleared otherwise Z:

set if all bits

V:

loaded with the Exclusive

by

the completion of the rotate operation)

C:

loaded with the high-order bit of the destination

Word:

Rotate all bits of the destination left one is loaded into the contents Byte:

Same

of

the result word =

C-bitof

of

the C-bitare loaded into Bit 0 of the destination.

OR

ofthe

the status word and the previous

Word:

Bytes:

ODD

I

~0

l'BsuU

i8

..

(Z ~ 1

....

nu.t

1

else

Z ~

V ...

0);

0)

V

negative?

881'O?

~t

i.s

based

D and C J"(Jtat.d

result

011

set

0;

cleared otherwise

N-bit and C·bit (as set

place.

Bit

to

C

and

Nault"

D

of

N

and

C

n.6J.J1

15

I\OLB:

1"<8:

0>

...

111·1'<7>;

~r<7:

0> •

CJ:I)b

...

(III

Db

r;

Ole)

'<7:

0)

O>;CCi

• (Z

(v

..

1.eloe

v

resuZt

is

D

and

C

,..,Butt

on ......

rotated

to

NSUlt

C

and

D

of R and

C

nsgatiVB?

0);

..

0)

ae1'lO?

tmnsnrit

V

is

based

55

ROR RORB

2.3 ps

3.5 ps

if

odd

byte

Rotate Right

dst

o 0 0 0 d d d d d

15

Operation: Condition

Codes:

(dst)~(dst)

N:

set

rotated right

if

the

high~order

cleared otherwise

"Z:

set if all bits

V:

loaded with the Exclusive

by

the completion of the rotate operation)

C:

loaded with the low-order

" Description: Rotates all bits

loaded into the

are

loaded into bit

Byte:

Same

Example:

Word:"

~-1

t

15

Byte:

I

Il

[~}

ISP:

ROR:

r<16:0>

....

ROBlI:

r<8:0>'"

Dto>ccc:nt~lS:

)I

.....

r<:tS>;

(r<lS:ct> -0)

CaK15:

0>

...

(N

e C) ~

Db'<0>a:aJb'<7:1>;

N""

r<:7>;

(r<7:0> • 0)

CCOb

+-

r;

(N e C) ~ (V

r;

(V

• (Z

(Z

.... 1 else

... 1

1>;

else

z ...

O)j

0)

z

...

0);

0)

650

one

place

bit

of the result

of

result =

0;

cleared otherwise

OR

of the N·bit and C-bit

bit

of

the

of

the destination right one

C-bit

"and

the previous contents of the C-bit

"15

of the destination.

I

I I

7t

8

1

:result

negative?

aero?

tl'fIn8m'it

V

"".uZ t

nsgatiVB? aero?

tN1'l8JJtit

V

is

based

[~}

is

D and C

result

on

i.

D and C

1'6BuZt

on

is

set (result < 0);

destination

place.

rotated

to

C and D

"'..m.l

pesul t of

rotated

to

C

and

result

D

of

n.miI

n060DD

dl

(as

Bit 0 is

I

0

1

I

1°

N and C

set

56

2.3

p.s

SWAB

Swap Bytes

dst

II" d d d d d

15

Operation: Byte Condition

Codes:

l/ByteO-.Byte

N:

set

if

high·order bit

cleared otherwise

Z:

set

if V:

C:

low·order byte cleared cleared

Description: Exchanges high-order byte and

tion word (destination must

Example:

Before

=077777

NZVC

11

Z ~ 0);

11

ISP:

SWAB:

r

...

D'<7:

N

--

(r<7:0> -0)

V -

C f-0;

0>00'<15:8>;

r<7>;

OJ

D ~ r

,.

(Rl)

(Z ~ 1

ne·xt

else

6 5 a

O/Byte 1 of

low·order byte (bit 7)

of

result = 0; cleared otherwise

SWAB

reBult

nega~ive?

aero? ctea2'

trcmsnri t ""BU t t

low-order byte

be

a word address). Rl

(Rl)

= 177577

iB

byt;e

swapped

v"

C

UJ

of

After

NZVC

0000

of

D

0003DD

result

is

set;

the destina·

D

57

4.5 Double Operand Instrudions Double operand instructions provide since they eliminate the need for used in accumulator·oriented machines.

MOV

General:

ADD

SUB

MOVB

Logical:

4.5.1 Double Operand Generallnstrudions

BIS BISB

BIT BITB

BIC BICB

an

"load"

CMP CMPB

instruction (and time) saving facility and "save" sequences

such

as

thoSe

58

2.3

ps

MOV MOVB

Movsre. dst

10"

I °

,0

1 I s

15 12

Operation: (dst).(src)

Condition

Description:

Example:

Codes:

N: Z: V: C:

Word: The tents of the source address

Byte:

byte instructions) extends

order byte (sign extension). Otherwise

bytes exactly

MOV

tents

fined mnemonic

MOV

Register

MOV

tained

MOV

and

buffer)

s s d d d

II

set

if

(src)

set

if

(src) cleared not affected

Moves

previous contents

Same

XXX,Rl ; loads Register 1 with the con·

of

memory location;

#20,RO ; loads the number

0;

2O,-{R6) ; pushes the operand con·

in

(R6) + , @ # 177566 ; pops the operand

moves

I

<0;

cleared otherwise

=0;

cleared otherwise

the

source

operand

of

as

MOV.

The

as

MOV

operates on words.

used

to

•• # "i

ndicates that the value 20 is the operand

location 20 onto the stack

it

into memory location

to

the destination are

MOVB

the

XXX

represent a memory location

the destination location.

are

not affected.

to a register (unique among

most significant bit

represents a programmer·de·

MOVB

1775t;;~

nlSSDD

d

lost

The

con·

of

the low

operates

(terminal print

20

off

on

into

a stack

MOV

Rl,R3

transfer

. MOve 177562,

minal keyboard

@#177566

buffer

to

terminal buffer

59

; performs an interregister

; moves a character from ter·

ISP:

HOVE:

HOVB:

r

r'"

...

SI~

N'"

(r<lS:

V'"

~

..

Sb

N'"

(r<7:

V"

Db'·

r<lS..>;

0> -

OJ

r

l

;

r<7>;

Cl> 0;

...

r

0)

moue

source

to

intemediate

NBwlt

regiBter~

,.

nsgativ.1

else

Z ...

O)~

.ero

-

if

16

bi.ts

of

r

4!'e

all

ae:ro

then Z

is

to

1

ovopfl,ow

~t

.

MOVe

etse

80Ul'Ce,

Z

is

.... s ..

ill

",!.BaNd

lt

to

se-t

to

0

to

destination

intermediate

result

Bet

""gativ.?

..

(Z

..

1

else

Z

..

0);

aero?

clear

V

t>"ll7lSlllit

Nsult

to

Db

60

2.31JS

ADD

Add src. dst

10

15

Operation: Condition

Codes:

0

I s

12

"

(dst).(src) N:

set.if result

Z:

set

if

V:

set

if

s s

I I

>

d

s

I

6 5 0

+ (dst)

<0;

result =

there

cleared otherwise

0;

cleared otherwise

was

arithmetic overflow as a result

cI

d

06SSDD

d d d

of

the oper-

ation; that is both operands were of the same sign and the

was

of

result C:

set if there

the opposite sign; cleared otherwise was

a carry from the most significant

bit

of the

result; cleared otherwise

Description: Adds the source operand to the destination operand and

at

the destination address. The original con-

destination are'lost. The contents

cOlllplement additiOn

ADD

20,RO

ADD

Rl,XXX

to

register:

to

memory:

ADD·

Rl,R2

ADD

@ # 17750,XXX

for

of

the

source

is

performed.

a memory loca-

Examples:

stores the result tents of

the

are not affected. Two's Add

to register: Add to memory: Add register Add memory

XXX

is

a programmer-defined mnemonic

tion.

ISP:

ADD:

r::::16:0> - s· +

N ... 1'<15>;

(r<15:0> -0) ~ (2

(5<15> " 1K15» "

v

C'"

D

~

.... 1 else

r<16>;

r

0';

else

(5<15> e r<15» ~ (

V'"

0);

deteJ'mine

Z -

negative?

0);

overflow

canoy

tJtctnsnrit

aeNJ?

Q7J.

opemnd

then

8et V to 1 else

th8

intermediate

..

.?

.~if

and

17th

result

sig7l$

"the

bit

to

D

of

sign

result

operands

of

set V to

the

sum

0

of

agree l"esul.t

17

bits

and

disagNle

sign -of

61

SUB

2.3

p.S

Subtract src. dst

11

15

0 s s

12

11

s s

s

I

d d d

6

5 0

Operation: (dst).(dst)-(src) [in detail, (dst) +

Condition.Codes:

N:

set

if

set

if

result

there

Z:

V:

ation, that is

of the source

<0;

cleared otherwise

=0;

cleared otherwise

was

arithmetic overflow

if

operands

was

the

were

same

of opposite signs and the sign

as

the sign of the result; cleared

otherwise

.

C:

.cleared

if

there

was

a carry from the most significant bit

the result; set otherwise

Description: Subtracts the

and

leaves

source

operandJrom the destination operand

the result at the destination address. contents of the destination are lost. source

are

Example:

bit,

when

not affected.

set,

indicates a "borrow".

In

double-precision arithmetic the

SUB

Rl,R2

Before

(Rl)

=011111

(R2) = 012345

(Rl) =011111

(R2)

NZVC

11

I d

~(src)

as

a result

The

After

=001234

NZVC

0001

16SSDD

d

+ 1 (dst)]

of

the oper·

The

contents

d

of

orignial

of

the

C·

ISP:

SUB:

r'"

0'

N'"

(r<15:.0;>·. (1X1S>

c'"

D~r

- 8

r<lS>;

V ... 1

r<16>;

1

;

"*

(Z - 1

else

..

-.

8<15»

1\

else

V ...

(1X1S>

0);

Ell

z ....

r<15»

0); '"

(

17

bit

:result

negative?

.8ero?

overof1,O>1?

bol'l'O>1

from

move

'l'68utt

is

(Bee add)

1

?th

to

D

D minus

bit

S;

actually

P

+-

..,

S+D+l-;

62

1.8

2.3

pS pS

if

Mode

0

CMP CMPB

Compare src. ds!

0/110

1

15

0

12

I s

11

s s s

S 8 d d d

6 5

Operation: (src)-(dst) [in detail, (src) + - (dst) + Condition

Codes:

N:

set.if

result

n2SSDD

d d d

0

11

<O;chfared otherwise

Z:

set if result

V:

set if there

of opposite signs

same

as

C:

cleared

was

the sign

if

there

=0;

cleared otherwise

arithmetic overflow; that is, operands

and

the sign

of

the result; cleared otherwise

was

a carry from the most significant

of

the destination

was

were

the

bit

the result; set otherwise

Description: Compares the source and destination operands and sets the

condition

which may then be used for arithmetic

and

codes,

logical conditional branches. Both operands are unaffected.

The

only action is

customarily followed

Note that unlike the subtract instruction the order of

to

set the condition

by

a conditional branch instruction.

codes.

The

compare is

oper·

ation is (src)-(dst), not (dst)-(src).

ISP:

DlPB:

. r<8:. 0>

...

Sb'

..

Db

I;

. DIP:

N ... r<7>;

(r<7:0>

(Sb<7>

c'"

r

..

5'

N ...

(1"<15: 0> -

(5<15> " ..,

·-0)

" ..,

Db<7»'

v

...

1

else

1"<8>

- 0'";

r<::1.5>;

0<15»

V'" 1 elae

c'"

1<16>

..

"(Z ... 1

V ...

;::t

V ~ 0);

(Z ... 1

10.

nex.t

elae z ...

10.

(Sb<7> e r<7» ~ (

0);

el&a

Z ...

(5<15>

E9

r<15»

0);

c::ompare

negative?

38ro?

overfi"",?

8th

~

negative?

ael'O?

..

( OVOl'fto.J?

17th

bit

affects

(s

is

""""!I

affects

(8

i8

••

""""!I

CC

add)

CC

add)

only

onty

of

63

· 4.5.2

Logical

These instructions have the same.format

They permit operations

Instructions

on

data at the

as

the double·operand.arithmetic group:

bit

level.

64

2.3

J.IS

Bit

Set src.

\0/1,

15

dst

°

BIS

BISB

n5SSDD

s

12

11

s [ d

6 5

d d

d

I

d

°

Operation: Condition

Codes:

Description:

Example:

ISP:

BIS:

r

...

D I V S I j

N

"'T<15>;

(1'<15:0> •

V ~ 0;

D

~

r

BISB:

r'"

Db' V Sb';

N

t-

r<7>;

(r<7:<t>.

V -

0;

Db

- r

(dst)~(src)

N:

set

Z:

set

V:

cleared

C:

not affected

v (dst)

if

high·order

if

result = 0; cleared otherwise

bit

of

result set, cleared otherwise

Performs "Inclusive OR"operation between the source and destination operands and address; that

is,

in the destination. The contents

Before

(RO)

=001234

(Rl)

= 001111

NZVC

0000

1

,.lIe

z

z ...

0);

..

0);

corresponding bits

leaves

SIS

RO,R1

1"e8Ult

is

S

negative?

.:a:e:ro?

clear transmit

result

negative?

"6l'O?

olear

tztanlJtttit roeeult

"OR"

V

NBUlt

is S "OR"

V

the result at the destination

set

in the source are set

of

the destination

After

(RO)

=001234

(R1)

=001335

NZVC

0000

D

to

D

to

D

are

lost.

65

BIT

BitS

2.4p.s

2.9

p.s

if

Mode 0

Bit Test src,

Operation:

Condition Codes:.

15

dst

s s

12

11

(dst)~(src)A(dst)

N:

set

if

Z:

V:

C:

high-order

set

if

result = cleared not affected

6 5

bit

of

0;

result

cleared otherwise

set;

Description: Performs logical "and"comparison

nation operands and modifies condition

Example:

Neither The corresponding bits in the source or whether tination

BIT #30.R3

BEQ

the

source

nor

BIT instruction may

that

are

clear in the source.

HELP

destination operands are affected.

be

used

are

set in the destination are also set

all corresponding bits set

; test bits 3 and 4 ;

if

;

BEQ

; both are

ISP:

,BIT:

BITB:

r ...

r

(r<15r

....

(><7:

Dr

1\

N"

r<15'>;

V ~ 0

Db' A Sb';

N"

r<.7>,

0>

V~O

S'.

==

0)

:::;

(Z

..... 1 else

Z +-

0)

'"

(Z ~ 1

else

Z ~ 0);

0);

test

result

negatitxn

lSero?

elear

V

test

result

neganve?

zero?

is

nAND"

"AND"

n3SSDD

d

d d

I

o

cleared otherwise

of

the source and desti-.

codes

accordingly.

to test whether any of the

in

the

des-

of

R3

both are

off

to see

to HELP will occur

off

of

D and S

of

D

and

S

if

66

2.9 pS

BIC

BICB

,Bit Clear src

[0/1

Operation:

Condition Codes:

15

dst

0 0

1

12

I s

11

(dst).-(src)A(dst)

N:

set

Z:

set

V:

cleared

C:

not affected

Description: Clears

bit in the source. The original contents lost. The contents

Example:

(R3)

(R4) ==001111

ISP:

BIC:

r"'D'I\-,S';next:

~

r<15>;

N

(r<l5:0> -0) 0 (Z

V

....

0;

D~r

BleB:

r'"

Db' A .....

N'"

1"<7>;

(1"<7:0> -

V'"

0;

Db'"

T

Sb

'

0)

~

(Z

.... 1 else Z ....

.... 1 else

I>

S

: s

S

if

high order

if

result

each

bit

=0;

cleared otherwise

bit in the destination that corresponds to a set

of

the source

Before

-001234

d d d d d d

I

s

6 5 0

of

result set; cleared otherwise

of

the destination

are

unaffected.

BIC

R3,R4

After

(R3)

~

(R4) ==000101

Z ...

NZVC

1111

0);

N8uZt

negative?

a82'01

cZea:t'V

tM>!Blllit

resuZt

negative?

,

aeY'O?

cleaP

tM>!Blllit

V

is

D

"AND"

l'esuZt

D

HAND"

""8UZt

to

'Wor"

D

"NO.!"

D

NZVC

0001

8

S

n4SSDD

are

001234

67

4.6

PROGRAM

4.6.1

Branches

The

instruction

(multiplied

a) the branch instruction is unconditional b)

codes (status word).

The

offset is the number of words from the current contents

the current contents. of the

Although the offset is automatically multiplied by two to express bytes before

PC.

Bit 7 is the sign

is

done in the backward direction. Similarly

and the branch

The8~bit

bytes) from the current bytes) from the current

The

PDp·ll

assembles the proper offset field for branch instructions in the form:

Where

"Bxx"

branch is to be made. the permissable branch range is condition

CONTROL

causes

by 2)·and the current contents

it

is -conditional and the conditions

PC

expresses a byte address, the offset

is

offset allows branching in the backward direction

assembler handles address arithmetic

is the branch instruction and

codes.

INSTRUCTIONS

a branch

of

the offset. 'If

done in the forward direction.

PC,

PC.

The

to

a location defined by the sum

of

the Program Counter if:

are

met after testing the condition

PC

point to the word following the branch instruction.

is

expressed in words.

it

is

set, the offset is negative and the branch

if

it

is not set, the offset

and in the forward direction

for

the user and computes and

Bxxloc

"Ioc"

is

assembler giv.esan error indication in the instruction

exceeded.

Branch instructions have

the address to which the

of

oUhe

PC.

it

is added to the

by

200. words (400.

by

177. words (376.

the offset

Note that '

is

positive

no

effect

The

if

on

68

2.6

J1S

BR

Branch (unconditiona!)

000

15

Operation:

Description:

Example:

PC • PC

Provides a way range

001000 001002 001004

xxx: 001006

001010

ISP:

BR:

PC +-PC + sign-extend(instrtlction<7:0>

I

000

of

OFFSET

8 7

+ (2 x offset)

of

-128

transferring program control within a

to + 127 words with a one word instruction.

BR

xxx

x

2)4

ooo410c

o

69

Simple.

Conditional

BEQ

BNE

BMI

BPL

BCS

BCC

BVS

BVC

Branches

70

1.5

2_6

pS pS

--

no branch branch

BEQ

Branch

on

Equal (zero)

~I_°-LI_°-LI_O_·L-°-LI_O~_0-L

15

Operation: Condition Codes: Unaffected .

Description: Tests the state

.

Example:

PC •

an

example. ation. in the source following a BIToperation. and.generally. that

CMP

BEQ

will branch

and

ADD

BEQ

will branch

PC

to

the

A.B

C

the

A.B

C

test that

result

sequence

__

L--L

__

L--L

__

O~F_~_~L-~I_·~

8 7 o

+ (2 x offset)

of

the Z-bit and causes a branch

it

is used to test equality following a CMP oper-

no

bits set in

of the previous operation

to

Cif

A

=.

B

to C if

A + B = 0;

Z = 1

if

the

destination were also.set

; compare A and B ; branch

;

addAto

; branch

0014 offset

__

if

was

zero.

if

they are equal

(A-

B =

0)

B

if

the

result = 0

~~I.

Z is set.

As

to

test

ISP:

BEQ:

(Z=1)

:=,b

(PC''''

PC + sign-extend(instruction<7:0>

X 2»

71

Branch

I 0 J 0

15

Not

Equal (Zero)

o 0 0 0

1.5 ps .. no branch

2.6 ps .. branch

0010

offset

1

I

10

8 7

OFFSET

Operation:

Conditio.n Codes: Unaffected

Description:

PC

...

PC

Tests the state of the Z·bit and causes a branch

clear. BNE

to test inequality following a

in the destination. were also in the source, followi

and generally,

. ation

was

Example:

CMP A,B

BNE

C

will branch

ADD

A,S

BNE

C

,will

branch

15ft;

BNE:

'(Z:::"(J)

-=

(PC -

PC + sign-extend(instruction<7:0>

+ (2 X offSet)

is

the

cOl11plementary

to

test

not

zero.

to C if

A

'"

to C if

A + B = 0

if

Z = 0

CMP,

that

the result

; compare A and B ; branch

and the sequence

B

; add ';

Branch

;to

x

2)}

operation

to

test

of

if

they are not equal

A

to

B

if

0

if

the Z·b1t is

to

BEQ.

that

It

some bits set

ng

the previous

the

resultnot

is

used

a BIT,

opel"·

equal

72

1.5

2.6

pS

--

pS

-- branch

no

branch

8MI

Branch

15

Operation: Condition Description:

Example:

ISP:

BMI:

(N=1)

:::10

(PC +-

on

Minus

PC

..

PC

Codes:

Unaffected Tests

the state of the N·bit and

is

used

the previous operation).

PC + sign·extend(instruction<7:0>

1004 same offset

OFFSET

8 7

+ (2 x offset) if N = 1

causes

to test the sign (most significant bit)

)(

2»

a branch

o

if

N is

of

the result of

set.

It

73

BPl

l.5

pS •• no branch pS .• branch

2.6

Branch on Plus

1

,

I

15

Operation:

Description:

ISP:

B"PL:

(NooO) ~ (PC -

.0

0 0

PC.

Tests the state

'BPL is the complementary operation

PC + sign-extend(insrructioo<7:0

.0

0 0

PC

+ (2 x offset)

8 7

of

the N·bit and

x 2»

if N =0

causes

.oFFSET

a branch

of

BMI.

1000

offset

if

N is clear.

.0

74

1.5

2.6

/.IS

••

/.IS

••

Branch

II 1

15

no

branch

on

Carry Set

0

o 0 0

I

8 7

OFFSET

1034

BCS

offset

I

o

Operation: Description:

ISP:

BCS;

(C=l)

= (PC

PC • PC

Tests

the state

is

used

to

test

ation.

....

PC + sign-extend(instructiono::::1:

+ (2 x offset)

of

the C·bit and

for

a carry

0>

)(

if

C = 1

causes

if

a branch

C=1

then

bl'aJ'lCh

in

the result of a previous oper.

2»

~f

Cis

set. rt

75

Bee

1.5

2.6

J.IS

--

J.IS

'- branch

no

branch

Branch on Carry Clear

o o

15

Operation: Description:

ISP:

Bee:

(C=O) ~ (PC +-PC + sign-extend(instruction<7:0>

o J 0

PC.,

PC

Tests

the state

BCC

is

the complementary operation to

o

B 7

+ (2 x offset)

of

the C·bit and

x

2))

if

C=O

causes

OFFSET

a branch

BCS

1030 offset

o

if

C is clear.

76

1.5

pS

2.6·,us

Branch

..

no branch

..

branch

on

Overflow Set

o 0 0 0

15

BVS

1024

offset

o

8 7

OFFSET

o

Operation: Description:

ISP:

BVS:

(V<=;l)

=:I

(pc

PC

..

PC

+.

(2 x offset)

Tests the state of

bit is

set

BVS

V

is

previous operation.

.....

PC

.. +

sign~~xtend(instruction<7;();>

if

V = 1

V

bit

(overflow) and causes a branch

used

to detect arithmetic overtlow

x

2»

in

if.

the the

77

ave

Branch

15

on

Overflo

o

.v

Clear

1.5

JlS

.. no branch

2.6

JlS

.. branch

1020

offset

o

8 7

OFFSET

o

Operation:

Description:

ISP:

Bve:

(V==O) ~ (PC'"

PC ~ PC

Tests the state clear.

PC

+

sign-extend(instruction<7;

+ (2 x offset)

of

BVC

the V

is complementary operation to

if V =0

bit

and causes a branch

0> x

2)

BVS.

if

the V

bit

is

78

'Signed Conditional Branches

Particular combinations of the condition'code bits are tested with the signed con· ditional branches. These instructions are used which the operands were considered

that

the

Note parisons in values is

largest

sense of signed comparisons differs from

that

in signed 16·bit, two's complement arithmetic the sequence of

as

follows:

077777

as

to

test the results

a signed (two's complement) values.

of

instructions in

that

of unsigned com·

077776

positive

000001 000000

177777 177776

negative

smallest

whereas in unsigned 16·bit arithmetic the sequence highest

100000

177777

000002

000001

100001

lowest The signed conditional branch instructions are:

BLT BLE

000000

BGE BGT

79

is

considered to

be

BLT

Branch on

Less

Than (Zero)

1.5

p.s

..

no

.branch

2.6 fIS" branch

0024

offset

~o~l_o~_o~

ffi

Operation: Description:

ISP:

BLT:

.

(N

E&

V)

do

__

O~I~o~

. added two negative numbers,

PC t-PC + sign-exr:end(lnstruct.ion<7:0> x 2»

__

~o~

PC

.-PC + (2x

Causes a branch

1. Thus

BL

T will always branch.following

In

particular, BLT will always cause a branch ·if

CMP

instruction operating on a negative source and a positive destination (even never cause a branch when

ating on a positive source and negative destination.

not

cause a branch

zero

(without overflow).

__

~I_'~

__

~~O~F_FS_ET~-L

8 7

offset)

if

N

"'v

= 1

if

the "Exclusive

if

overflow occurred). Further, BL

if

the

result

Or"of

even

if

it

follows a CMP instruction oper-

of

the previous operation

__

~~

__

~1

o

the N and V bits are

an

operation

overflow occurred;

it

follows a

BL

.

that

Twill Twill.

was

80

1.5 pS

pS

2.6

Branch

.. ..

o I 0

15

no

branch

on

Greater than

BGE

or

Equal (zero)

o

o I 0

OFFSET

8 7

0020

offset

o

Operation: Description:

ISP:

BGE:

(N =-V)

=-

(pc

PC ~ PC

+ (2 x offset)

Causes a branch

BGE

is the complementary operation to BLT. Thus

cause

always

caused addition

a branch

to

a branch on a zero result.

......

PC

+

sign~extend(instruction<):O>

if

N

\f

V = 0

if

N and V are either both clear or both set.

BGE

when

it

two positiv.e numbers.

)(

follows an operation that

BGE

2»

will also cause

will

sn

BlE

1.5 }IS

..

no branch

2.6 }IS •. branch

Branch on Less

o I 0

15

Operation: Description:

ISP:

BLE;

(Z V (N $

than

or

Equal (zero)

o

o 0

OFFSET

8 7

PC ~ PC

Operation is similar branch

V)

~

(pc

.....

PC + sign-ext.end(instruction<:7:0>

+ (2 x offset)

if

the result

if

Z v(N v-V)

to

BLT

but

of

the previous operation was zero.

in addition will cause a

x 2»

= 1

0034

offset

o

82

1.5

!JS --no branch

2_6!JS --branch

Branch

on

Greater Than (zero)

15

o

B 7

BGT

0030 offset

OFFSET

o

Operation: Description:

ISP:

BGT:

-.(Z

V (N e

v»

:$

(PC

PC.

PC

-t

(2 x offset)

Operation of.BGT a branch

....

PC + sign-extend.{instruction<7:0>

on

is

a zero

similar to

result

if

Z v(N

BGE.

X 2»

y.

0)

except

BGT

will

not

cause

83

Unsigned

The Unsigned Conditional Branches provide a means comparison operations

Conditional

BHI

Branches

in

which the operands are considered

BlOS

BHIS

BlO

84

for

testing the result of

as

unsigned values.

1.5

2.6

pS pS

.. ..

no branch branch

BHI

Branch on Higher

1

,0

15

Operation:

. Description:

ISP:

Btl!:

-,(C v Z)

o 0 o

PC ~ PC

Causes.a branch carry nor a zero result. This operations than the destination.

::::J

(PC

......

Pc + sign-extend(instruction<7:1l'-->

o o

B 7

+ (2 x offset)

if

as

long as the source

1010 offset

OFFSET

if

C = 0 and Z = 0

the

previous operation caused neither a

wi"

happen in comparison (CMP)

hasa

higher unsigned value

x 2»

o

85

BlOS

1.5

!lS

2-6!lS

--

no

--

branch

Branch on Lower

11100000

15

Operation: Description:

ISP:

BLOS,

(C v Z) ~ (PC +-

or

Same

OFFSET

8 7

PC...,

PC

+ (2 x offset)

Causes a branch carry

or

a zero to BHL The branch long

as

result_

the source is equal to,

if

C v Z = 1

the previous operation caused either a

BLOS

is

the complementary operation

will occur in comparison operations as

or

has a lower unsigned value than the destination_ _ Comparison of unsigned values with the CMP instruction be

tested

for

"higher

or

same" and "higher"by a simple test

of the C-bit.

PC

+-sign-extend(instruction<7:0>

X

2»)

1014 offset

o

can

86

1.5

2.6

ps

.. no branch

ps

.-

branch

BlO

Branch on Lower

15

Operation: Description:

ISP:

BCS/BUJ:

(C.=l) =

(PC'"

o 0 0 0

I

PC..

8 7

PC

+ (2 x offset) if C = 1

BlO is same instruction

only

for

,convenience.

PC + sign-excerui(instructlon<7:0> x 2»

as

OFFSET

BCS.

This mnemonic

1034 offset

o

is

included

I

87

BHIS

Brallch

1

15

on

,0000

Higher

or

Same

°

8 7

OFFSET

1.5 2_6

iJS iJS

--

1030

no

branch

offset

°

Operation: Description:

'SP:

Bee/BUIS:

(C=O) ~ (PC'"

PC • PC + (2

BHIS is the same instruction as cluded only

PC + sign-extend(ill8truction<1:0>

x offset)

for

convenience_

if

C = 0

BCC_

This mnemonic is in-

x

2»

88

Strand DDM / System DDM (1971 - 1980) PDP11 Handbook

Specifications and Main Features

Frequently Asked Questions

User Manual