STMicroelectronics RVIPer100-SP, VIPer100A-ASP Technical data

VIPer100/SP

VIPer100A/ASP

SMPS PRIMARY I.C.

Table 1. General Features

Type

V

DSS

I

n

VIPer100/SP 620V 3 A

VIPer100A/ASP 700V 3 A

■ ADJUSTABLE SWITCHING FREQUENCY UP

R

DS(on)

2.5

2.8

Ω

TO 200 kHz

■ CURRENT MODE CONTROL

■ SOFT START AND SHUTDOWN CONTROL

■ AUTOMATIC BURST MODE OPERATION IN

STAND-BY CONDI T ION ABLE TO MEET “BLUE ANGEL” NORM (<1w TOTAL POWER CONSUMPTION)

■ INTERNALLY TRIMMED ZENER

REFERENCE

■ UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■ INTEGRATED START-UP SUPPLY

■ OVER-TEMPERATURE PROTECTION

■ LOW STAND-BY CURRENT

■ ADJUSTABLE CURRENT LIMITATION

Figure 1. Block Diagram

Figure 2. Package

PENTAWATT HV

PENTAWATT HV (022Y)

DESCRIPTION

VIPer100™/100A, made using VIPower M0 Technology, combines on the same silicon chip a state-of-the-art PWM circuit together with an optimized, high voltage, Vertical Power MOSFET (620V or 700V / 3A).

Typical applications cover offline power supplies with a secondary power capability of 50 W in wide range condition and 100W in single range or with doubler configuration. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode without extra components.

_

1 V/A

CURRENT

AMPLIFIER

DRAIN

SOURCE

1

3

2 0

0 C F

OSC

ON/OFF

SECURITY

LATCH

ERROR

AMPLIFIER_

UVLO

LOGIC

0.5 V +

V

DD

13 V

+

_

4.5 V

R/S

OVERTEMP.

DETECTOR

1.7

DELAY

FF

QSR1

S

s

μ

OSCILLATOR

PWM

LATCH

FF

R2 R3

COMP

Q

250 ns

BLANKING

0.5V +

+ _

Rev 2

June 2005 1/24

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24

VIPer 100/SP - VIPe r100A/A SP

I

Table 2. Absolute Maximum Rating

Symbol Parameter Value Unit

Continuous Drain-Source Vol tage (TJ = 25 to 125°C)

V

OSC

V

COMP

I

COMP

V

ESD

I

DS

D

DD

for VIPer100/SP for VIPer100A/ASP

–0.3 to 620

–0.3 to 700 Maximum Current Internally lim ited A Supply Voltage 0 to 15 V Voltage Range Input

0 to V

DD

Voltage Range Inpu 0 to 5 V Maximum Continuous Curre nt ±2 mA Electrostati c Discharge (R =1.5kΩ; C=100pF) 4000 V Avalanche Drain-Source Current, Repetitive or Not Repetitive

I

D(AR)

P

tot

T

stg

(Tc=100°C; Pulse width limit ed by TJ m ax; δ < 1%) for VIPer100/SP for VIPer100A/ASP

Power Dissipation at Tc=25ºC Junction Operating Temperature Internally lim ited °C

j

2

1.4 82 W

Storage Temperature -65 to 150 °C

Table 3. Thermal data

Symbol Parameter PENTAWATT HV Unit

V V

V

A A

R

thj-case

R

thj-amb

Thermal Resistance Junction-case Max 1.4 °C/W Thermal Resistance Ambient-case Max 60 °C/W

Figure 3. Connection Diagrams (Top View)

PENTAWATT HV

PENTAWATT HV (022Y)

Table 4. Current and Voltage Convention

DD

I

OSC

V

DD

V

OSC

13V

+

I

COMP

V

COMP

DRAINVDD

COMP SOURCE

D

V

DS

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VIPer100/SP - VIPer100A/ASP

Table 5. Ordering Numbers

PENT AWATT HV PENTAWATT HV (022Y)

VIPer100

VIPer100A

VIPer100 (022Y)

VIPer100A (022Y)

Pins Functional Description Drain Pin (Integrated Power MOSFET Drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring sel f protection aga inst voltage s urges, PCB stray inductance, and allowing a snubberless operation for low output power.

Suorce Pin:

Power MOSFET source pin. Primary side circuit common ground connection.

VDD Pin (Power Supply):

This pin provides two functions :

■ It corresponds to the low voltage supply of the control part of the circuit. If V

up current source is activated and the output power MOSFET is switched off until the V reaches 11V. During this phase, the internal current consumption is reduced, the V a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut

down, and the device tries to start up by switching again.

■ This pin is also connected to the error amplifier, in order to allow primary as well as secondary

regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain V

on V

pin by transformer design, in order to stuck the output of the transconductance amplifier to the

DD

at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put

DD

high state. The COMP pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the V

voltage, which cannot overpass 13V. The output voltage will be

DD

somewhat higher than the nominal one, but still under control.

goes below 8V, the start-

DD

voltage

DD

pin is sourcing

DD

Compensation Pin

This pin provides two functions :

■ It is the output of the error transconductance amplifier, and allows for the connection of a compensation

network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, second ary regulation configurations are also implemented through the COMP pin.

■ When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle

for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (no matter what the configuration is) to provide a burst mode operation in case of negligible output power or open load condition.

OSC Pin (Oscillator Frequency):

An Rt-Ct network must be connected on that to define the switching frequency. Note that despite the connection of R provides also a synchronisation capabilit y, when connected to an external frequency source.

to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It

t

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VIPer 100/SP - VIPe r100A/A SP

Table 6. Avalance Characteristics

Symbol Parameter Max Value Unit

Avalanche Curre nt, Re petitive or Not Repetitive

I

D(AR)

E

(AR)

(pulse width limited by TJ max; δ < 1%) for VIPer100/SP (see Figu re 15) for VIPer100A/ASP (*) (see Figure 15)

Single Pulse Avalanche Energy

= I

(starting TJ = 25ºC, I

D

D(ar)

) (*)

2

1.4

60 mJ

A A

Electrical Chracteristics (TJ = 25°C; VDD = 13V, unless otherwise spec if ied)

Table 7. Power Section

Symbol Parameter Test Conditions Min Typ Max Unit

I

BV

I

DSS

R

DS(on)

C

t

f

t

r

oss

Drain-Source Voltage

DS

Off-State Drain Current

St atic Drain-Source On Resistance

Fall Ti me Rise Time Output Capacitance

= 1mA; V

D

for VIPer100/SP for VIPer100A/ASP (see Figure 8)

V

= 0V; Tj = 125°C

COMP

= 620V for VIPer100/SP

V

DS

= 700V for VIPer100A/ASP

V

DS

= 2A

I

D

for VIPer100/SP for VIPer100A/ASP

= 2A; Tj = 100°C

I

D

for VIPer100/SP for VIPer100A/ASP

= 0.2A; V

I

D

= 0.4A; V

I

D

V

= 25V

DS

= 0V

COMP

=300V (1)Figure 6

IN

= 300V (1)Figure 6

IN

620 700

2.0

1 1

2.5

2.8

mA mA

Ω Ω

2.3

4.5

5.0

Ω Ω

100 ns

50 ns

150 pF

V V

(1) On Inductive Load, Clamped.

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VIPer100/SP - VIPer100A/ASP

Table 8. Supply Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

= 5V; VDS = 35V

V

I

DDch

Start-Up Charging Current

DD

(see Figure 5)(see Fig ure 18)

-2 mA

I

DD0

I

DD1

V

DDoff

V

DDon

V

DDhyst

= 12V; F

V

Operating Supply Current

DD

(see Figure 5)

= 12V; F

V

DD

V

= 12V; F

DD

Undervoltage Shutdown (see Figure 5) 7.5 8 9 V Undervoltage Reset (see Figure 5) 11 12 V Hysteresis Start-up (see Figure 5) 2.4 3 V

= 0kHz

SW

= 100kHz

sw

= 200kHz

sw

12 16 mA

15.5 mA 19 mA

Table 9. Oscillator Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

R

=8.2KΩ; CT=2.4nF

T

V

F

SW

Oscillator Frequency Total Variation

=9 to 15V;

DD

with R

± 1%; CT± 5%

T

90 100 110 KHz

(see Figure 9)(see Fig ure 12)

V

OSCIH

V

OSCIL

Oscillator Peak Vol tage 7.1 V Oscillator Valley Voltage 3.7 V

Table 10. Error Amplifier Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

V

DDREG

ΔV

DDreg

G

BW

VDD Regulation Point I Total Variation

Unity Gain Bandwidth

=0mA (see Figure 4)

COMP

T

=0 to 100°C

j

From Input =V Output = V

DD

COMP

COMP pin is open

12.6 13 13.4 V 2%

to

150 KHz

(see Figure 13)

A

VOL

G

m

V

COMPLO

V

COMPHI

I

COMPLO

I

COMPHI

Open Loop Voltage Gain

DC Transconductance Output Low Level Output High Level Output Low Curre nt Capability Output High Current

Capability

COMP pin is open (see Figure 13)

V

=2.5V(see Figure 4)

COMP

=-400µA; VDD=14V

I

COMP

I

=400µA; VDD=12V

COMP

V

=2.5V; VDD=14V

COMP

V

=2.5V; VDD=12V

COMP

45 52 dB

1.1 1.5 1.9 mA/V

0.2 V

4.5 V

-600 µA

600 µA

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VIPer 100/SP - VIPe r100A/A SP

Table 11. PWM Comparator Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

H

V

COMPoffVCOMP

I

Dpeak

t

on(min)

ΔV

ID

Peak Current Limitat ion Current Sense Delay to Turn-

d

Off Blanking Ti m e 250 360 ns

b

/ ΔI

COMP

DPEAK

Offset I

V

= 1 to 3 V

COMP

= 10mA

DPEAK

V

= 12V; COMP pin open

DD

I

= 1A

D

0.7 1 1.3 V/A

0.5 V

345.3A

250 ns

Minimum On Time 350 1200 ns

Table 12. Shutdown and Overtemperature Section

Symbol Parameter Test Conditions‘ Min Typ Max Unit

V

COMPth

t

DISsu

T

hyst

Restart Threshold (see Figure 7) 0.5 V Disable Set Up Time (see Figure 7) 1.7 5 µs Thermal Shutdown

tsd

Temperature

(see Figure 7) 140 170 °C

Thermal Shutdown Hyst eresis (see Figure 7) 40 °C

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VIPer100/SP - VIPer100A/ASP

I

DD

I

D

V

0

(

140

(

Figure 4. VDD Regulation P oint Figure 5. Undervoltage Loc kout

I

COM P

I

COMPHI

0

COMPLO

Figure 6. Trans i t ion Time Figure 7. Shutdown Action

Slope =

G m in mA/V

V

DDreg

FC00150

V

I

DD

DD0

I

DDch

VOSC

DDhyst

V

DDoff

VDS= 35 V

Fsw = 0

DDon

V

FC00170

V

D

ID

10% Ipeak

DS

90% V D

D

10% V

tf

t

tr

FC00160

VCOMP

COMPth

ID

tDISsu

ENABLE

DISABLE

t

ENABLE

FC0006

Figure 8. Breakdown Voltage vs. Temperature Figure 9. Typ ica l Freque ncy Variation

1.15

BVDSS

Normalized)

1.05

0.95

1.1

1

0 20406080100120

Temperature (°C)

FC00180

1

%)

0

-1

-2

-3

-4

-5 0 20 40 60 80 100 120

Temper at ure (°C)

FC00190

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VIPer 100/SP - VIPe r100A/A SP

T

t

Figure 10. Start-Up Waveforms

Figure 11. Over-temperature Protection

J

T

ts c

tsd-Thyst

V

dd

V

ddon

V

ddoff

I

d

V

comp

SC101 91

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