ST MICROELECTRONICS USBLC6-2SC6 Datasheet

Features

■ 2 data-line protection

■ Protects V

■

Very low capacitance: 3.5 pF max.

■ Very low leakage current: 150 nA max.

■ SOT-666 and SOT23-6L packages

■ RoHS compliant

BUS

USBLC6-2

Very low capacitance ESD protection

SOT23-6L

USBLC6-2SC6

Figure 1. Functional diagram (top view)

SOT-666

USBLC6-2P6

Benefits

■ Very low capacitance between lines to GND for

optimized data integrity and speed

■ Low PCB space consumption: 2.9 mm

2

max for

SOT-666 and 9 mm² max for SOT23-6L

■ Enhanced ESD protection: IEC 61000-4-2

level 4 compliance guaranteed at device level,
hence greater immunity at system level

■ ESD protection of V

■

High reliability offered by monolithic integration

■ Low leakage current for longer operation of

BUS

battery powered devices

■ Fast response time

■ Consistent D+ / D- signal balance:

– Very low capacitance matching tolerance

I/O to GND = 0.015 pF

– Compliant with USB 2.0 requirements

Complies with the following standards:

■ IEC 61000-4-2 level 4:

– 15 kV (air discharge)
– 8 kV (contact discharge)

11

I/O1 I/O1

2

GND V

3

I/O2 I/O2

6

5

BUS

4

Applications

■ USB 2.0 ports up to 480 Mb/s (high speed)

■ Compatible with USB 1.1 low and full speed

■ Ethernet port: 10/100 Mb/s

■ SIM card protection

■ Video line protection

■ Portable electronics

Description

The USBLC6-2SC6 and USBLC6-2P6 are
monolithic application specific devices dedicated
to ESD protection of high speed interfaces, such
as USB 2.0, Ethernet links and video lines.

The very low line capacitance secures a high level
of signal integrity without compromising in
protecting sensitive chips against the most
stringently characterized ESD strikes.

October 2011 Doc ID 11265 Rev 5 1/14

www.st.com

14

Characteristics USBLC6-2

1 Characteristics

Table 1. Absolute ratings

Symbol Parameter Value Unit

IEC 61000-4-2 air discharge

V

Peak pulse voltage

PP

IEC 61000-4-2 contact discharge
MIL STD883G-Method 3015-7

T

Table 2. Electrical characteristics (T

Storage temperature range -55 to +150 °C

stg

Operating junction temperature range -40 to +125 °C

T

j

T

Lead solder temperature (10 seconds duration) 260 °C

L

= 25 °C)

amb

Symbol Parameter Test conditions

I

V

RM

BR

V

Leakage current VRM = 5.25 V 10 150 nA

Breakdown voltage between
V

and GND

BUS

Forward voltage IF = 10 mA 1.1 V

F

= 1 mA 6 V

I

R

I

= 1 A, 8/20 µs

PP

Any I/O pin to GND

V

CL

Clamping voltage

I

= 5 A, 8/20 µs

PP

Any I/O pin to GND

C

i/o-GND

ΔC

C

ΔC

i/o-GND

i/o-i/o

i/o-i/o

Capacitance between I/O
and GND

= 1.65 V 2.5 3.5

V

R

Capacitance between I/O VR = 1.65 V 1.2 1.7

15
15
25

Val ue

Min. Typ. Max.

12 V

17 V

0.015

0.04

kV

Unit

pF

pF

2/14 Doc ID 11265 Rev 5

USBLC6-2 Characteristics

Figure 2. Capacitance versus voltage

(typical values)

C(pF)

3.0

C =I/O-GND

2.5

2.0

1.5

1.0

0.5

O

C=I/O-I/O

j

F=1MHz

V =30mV

OSC RMS

T=25°C

Data line voltage (V)

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 4. Relative variation of leakage

current versus junction
temperature (typical values)

I[T

] / I [T

100

RM j

10

RM j

=25°C]

V =5V

BUS

Figure 3. Line capacitance versus frequency

(typical values)

C(pF)

2.8

2.6

2.4

2.2

2.0

j

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1 10 100 1000

F(MHz)

V =30mV

OSC RMS

T=25°C

j

V =0V to 3.3V

LINE

Figure 5. Frequency response

0.00

S21(dB)

-5.00

-10.00

T (°C)

1

25 50 75 100 125

j

-15.00

F(Hz)

-20.00

100.0k 1.0M 10.0M 100.0M 1.0G

Doc ID 11265 Rev 5 3/14

Technical information USBLC6-2

2 Technical information

2.1 Surge protection

The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail
topology.

The clamping voltage V

V

+ = V

V

with: V

CL

CL

F

TRANSIL

- = - VF for negative surges

= VT + Rd.I

can be calculated as follow:

CL

+ VF for positive surges

p

(VF forward drop voltage) / (VT forward drop threshold voltage)

and V

TRANSIL

= VBR + R

d_TRANSIL.IP

Calculation example

We assume that the value of the dynamic resistance of the clamping diode is typically:

R

= 0.5 Ω and VT = 1.1 V

d

We assume that the value of the dynamic resistance of the transil diode is typically:

R

d_TRANSIL

For an IEC 61000-4-2 surge Level 4 (Contact Discharge: V
V

= +5 V, and if in first approximation, we assume that:

BUS

I

= Vg / Rg = 24 A.

p

= 0.5 Ω and VBR = 6.1 V

= 8 kV, Rg = 330 Ω),

g

So, we find:

V

+ = +31.2 V

CL

V

- = -13 V

CL

Note: The calculations do not take into account phenomena due to parasitic inductances.

2.2 Surge protection application example

If we consider that the connections from the pin V
GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume
that the parasitic inductances L

VBUS

, L

I/O

and L
an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (t
voltage V

has an extra value equal to L

CL

.dl/dt + L

I/O

The dI/dt is calculated as:

dI/dt = I

= 24 A/ns

p/tr

The overvoltage due to the parasitic inductances is:

L

.dl/dt = L

I/O

.dI/dt = 6 nH x 24 A/ns = 144 V

GND

By taking into account the effect of these parasitic inductances due to unsuitable layout, the
clamping voltage will be:

+ = +31.2 + 144 + 144 = 319.2 V

V

CL

V

- = -13.1 - 144 - 144 = -301.1 V

CL

4/14 Doc ID 11265 Rev 5

to VCC, from I/O to data line and from

BUS

of these tracks are about 6 nH. So when

GND

GND

.dI/dt.

=1ns), the

r

USBLC6-2 Technical information

We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see 2.3: How to ensure good ESD

protection).

Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout

ESD surge on data line

di

L

L

I/O

I/O pin

V+=V +V + L + L

CL TRANSIL F I/O GND

V = -V - L - L

CL- F I/O GND

TRANSIL

BR

L

I/O

VBUS

dt

V

F

L

GND

di
dt

di
dt

di

dt

Rd.IpVV

+=

V pin

CC

V

TRANSIL

GND pin

L

V

BUS

Data line

didtdi

L

+ L

I/O

GND

V+V

-L

I/O

TRANSIL F

didtdi

- L

GND

V

CL

di

GND

dt

di

surge > 0

dt

surge > 0

V

CL+

dt

t = 1 ns

r

t = 1 ns

r

-V

F

dt

Positive

Surge

t

t

Negative

Surge

V

CL-

2.3 How to ensure good ESD protection

While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on
the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for
layout consideration)

Figure 7. ESD behavior: layout optimization Figure 8. ESD behavior: measurement

1

1

2

3

Unsuitable layout

1

1

2

CC

to V

pin and from GND plane to GND pin must be as short as

BUS

conditions

6

5

4

6

5

ESD SURGE

TEST BOARD

IN OUT

USBLC6-2SC6

+5 V

3

Optimized layout

4

Doc ID 11265 Rev 5 5/14

Technical information USBLC6-2

Figure 9. ESD response to IEC 61000-4-2

(+15 kV air discharge)

Vin

Vout

Important:

A good precaution to take is to put the protection device as close as possible to the
disturbance source (generally the connector).

2.4 Crosstalk behavior

Figure 10. ESD response to IEC 61000-4-2

(-15 kV air discharge)

Vin

Vout

2.4.1 Crosstalk phenomenon

Figure 11. Crosstalk phenomenon

R

G1

V

G1

V

G2

The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12
or β21) increases when the gap across lines decreases, particularly in silicon dice. In the
above example the expected signal on load R
has got an extra value β
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into
account when the drivers impose fast digital data or high frequency analog signals in the
disturbing line. The perturbed line will be more affected if it works with low voltage signal or
high load impedance (few kΩ).

R

G2

DRIVERS

21VG1

Line 1

β

V

1

β

21

G1

V

G1

V

+

G2

12

Line 2

R

L1

R

L2

RECEIVERS

is α2VG2, in fact the real voltage at this point

L2

α

α

+

V

G2

2

. This part of the VG1 signal represents the effect of the

6/14 Doc ID 11265 Rev 5

USBLC6-2 Technical information

Figure 12. Analog crosstalk measurements

TEST BOARD

NETWORK ANALYSER

PORT 2

Vbus

NETWORK ANALYSER

PORT 1

-2SC6
C6

USBL

Figure 12. shows the measurement circuit for the analog application. In usual frequency

range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see

Figure 13.).

Figure 13. Analog crosstalk results

dB

0.00

- 30.00

- 60.00

- 90.00

F (Hz)

- 120.00

100.0k 1.0M 10.0M 100.0M 1.0G

As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good
transmission of operating signals. The frequency response (Figure 5.) gives attenuation
information and shows that the USBLC6-2 is well suitable for data line transmission up to
480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies,
for instance.

Doc ID 11265 Rev 5 7/14

Technical information USBLC6-2

2.5 Application examples

Figure 14. USB 2.0 port application diagram using USBLC6-2

DEVICE­UPSTREAM
TRANSCEIVER

V

BUS

R

X LS/FS

R

X HS

T

X HS

R

X LS/FS -

R

X HS -

T

X HS -

GND GND

T

X LS/FS

T

X LS/FS -

DEVICE­UPSTREAM
TRANSCEIVER

V

BUS

R

X LS/FS

R

X HS

T

X HS

R

X LS/FS -

R

X HS -

T

X HS -

GND

T

X LS/FS

T

X LS/FS -

+ 3.3V

R

PU

SW

2

SW

1

+ R
+ R
+ T

USB

connector

V

BUS

D+

+ 5V

D-

R

S

+ T

R

S

USBLC6-2SC6

GND

R

PD

+ 3.3V

R

PU

SW

2

SW

1

+
+
+

USB

connector

V

BUS

D+

D-

R

S

+

R

S

USBLC6-2P6

GND

USBLC6-4SC6

R

PD

Protecting
Bus Switch

R

R

R

PD

R

R

R

PD

DOWNSTREAM

TRANSCEIVER

V

BUS

X LS/FS

+

X HS

+

X HS

R

X LS/FS -

R

X HS -

T

X HS -

S

X LS/FS

S

T

X LS/FS -

R

X LS/FS

R

+

X HS

T

+

X HS

R

X LS/FS -

R

X HS -

T

X HS -

GND

S

T

X LS/FS

S

T

X LS/FS -

HUB-

+

+

+

+

Mode

SW

SW

1

2

ClosedOpenLow Speed LS

OpenClosedFull Speed FS

OpenClosed then openHigh Speed HS

Figure 15. T1/E1/Ethernet protection

+V

Tx

SMP75-8

Rx

SMP75-8

8/14 Doc ID 11265 Rev 5

100nF

+V

100nF

CC

CC

USBLC6-2SC6USBLC6-2SC6

DATA

TRANSCEIVER

USBLC6-2 Technical information

2.6 PSpice model

Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are

defined by the PSpice parameters given in Figure 17.

Figure 16. PSpice model

D+in

LI/O

LGND

GND

LI/O

D-in

RI/O

MODEL = Dlow MODEL = Dhigh

RGND RI/O

MODEL = Dlow MODEL = Dhigh

RI/O

MODEL = Dzener

RI/O

RI/O

LI/O

LI/O

LI/O

Note: This simulation model is available only for an ambient temperature of 27 °C.

Figure 17. PSpice parameters Figure 18. USBLC6-2 PCB layout

considerations

Dlow Dhigh Dzener

BV 50 50 7.3

CJ0 0.9p 2.0p 40p

IBV 1m 1m 1m

M 0.3333 0.3333 0.3333

RS 0.2 0.52 0.84

VJ 0.6 0.6 0.6

TT 0.1u 0.1u 0.1u

LI/O 750p

RI/O 110m

LGND 550p

RGND 60m

D+in

GND

D-in

1

USBLC6-2

D+out

V

BUS

D-out

D+out

VBUS

D-out

C = 100nF

BUS

Doc ID 11265 Rev 5 9/14

Ordering information scheme USBLC6-2

3 Ordering information scheme

Figure 19. Ordering information scheme

USB LC 6 - 2 xxx

Product Designation

Low capacitance

Breakdown Voltage

6 = 6 Volts

Number of lines protected

2 = 2 lines

Packages

SC6 = SOT23-6L
P6 = SOT-666

10/14 Doc ID 11265 Rev 5

USBLC6-2 Package information

4 Package information

● Epoxy meets UL94, V0

● Lead-free packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

Table 3. SOT-666 dimensions

L1

L3

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

b1

b

D

e

Figure 20. SOT-666 footprint

dimensions in mm

Dimensions

Ref.

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.45 0.60 0.018 0.024

A3 0.08 0.18 0.003 0.007

E1

b 0.17 0.34 0.007 0.013

b1 0.19 0.27 0.34 0.007 0.011 0.013

A

L2

E

A3

D 1.50 1.70 0.059 0.067

E 1.50 1.70 0.059 0.067

E1 1.10 1.30 0.043 0.051

e0.50 0.020

L1 0.19 0.007

L2 0.10 0.30 0.004 0.012

L3 0.10 0.004

Figure 21. SOT-666 marking

0.99

0.50

0.30

0.62

2.60

F

Doc ID 11265 Rev 5 11/14

Package information USBLC6-2

Table 4. SOT23-6L dimensions

Dimensions

c

q

b

L

H

E

Figure 22. SOT23-6L footprint

dimensions in mm

A1

e

e

0.60

Ref.

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.90 1.45 0.035 0.057

A

A1 0 0.10 0 0.004

A2 0.90 1.30 0.035 0.051

b 0.35 0.50 0.014 0.020

c 0.09 0.20 0.004 0.008

D 2.80 3.05 0.11 0.118

D

E 1.50 1.75 0.059 0.069

e 0.95 0.037

A2

H 2.60 3.00 0.102 0.118

L 0.10 0.60 0.004 0.024

θ 0° 10° 0° 10°

Figure 23. SOT23-6L marking

1.20

3.50 2.30

0.95

1.10

12/14 Doc ID 11265 Rev 5

UL26

USBLC6-2 Ordering information

5 Ordering information

Table 5. Ordering information

Order code Marking Package Weight Base qty Delivery mode

USBLC6-2SC6 UL26 SOT23-6L 16.7 mg 3000 Tape and reel

USBLC6-2P6 F SOT-666 2.9 mg 3000 Tape and reel

6 Revision history

Table 6. Document revision history

Date Revision Changes

14-Mar-2005 1 First issue.

07-Jun-2005 2 Format change to figure 3; no content changed.

Added marking illustrations - Figures 21 and 23. Added

20-Mar-2008 3

ECOPACK statement. Updated operating junction temperature
range in absolute ratings, page 2. Technical information section
updated. Reformatted to current standards.

27-Jun-2011 4

24-Oct-2011 5 Updated legal statement.

Updated leakage current for V
standard. Updated marking illustrations Figure 21 and Figure 23.

= 5.25 V as specified in USB

RM

Doc ID 11265 Rev 5 13/14

USBLC6-2

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14/14 Doc ID 11265 Rev 5