ST MICROELECTRONICS UC3844BN Datasheet

UC2842B/3B /4B/5B

®

UC3842B/3B /4B/5B

HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER

TRIMMED OSCILLATOR FOR PRECISE FRE-

.

QUENCY CO NT ROL OSCILLATOR FREQUENCY GUARANTEED

.

AT 250kHz CURRENT MODE OPERATION TO 5 00kHz

.

AUTOMATIC FEED FORWARD COMPENSA-

.

TION LATCHING PWM FOR CYCLE-BY-CYCLE

.

CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH

.

UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT

.

UNDERVOLTAGE LOCKOUT WITH HYSTER-

.

ESIS LOW STAR T-UP A ND OPER ATING CU RRENT

.

DESCRIPTION

The UC38 4xB family of control ICs provi des the necessary features to implement off-line or DC to DC fixed freq uency c urren t mode co ntrol s chemes with a minimal external parts count. Internally implemented cir cuits i nclude a trimmed os cil lator fo r precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input , logic to in sure la tched oper ation, a P WM

comparator which also provi des current limit control, and a totem pole output stage designed to source or sink high pe ak current. The output stage, su itable for driving N-Channel MOSFETs, is low in the offstate.

Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842B and UC3844B have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843B and UC3845B are 8.5 V and 7.9 V. The UC3842B and UC3843B can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844B and UC3845B by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.

Minidip

SO8

BLOCK DIAGRAM (toggle flip flop use d only in UC3844B and UC3845B)

7

Vi

2.50V

UVLO

S/R

2R

R1V

5V

REF

VREF GOOD

LOGIC

S R

CURRENT

SENSE

COMPARATOR

INTERNAL

BIAS

T

LATCH

PWM

UC3842B

March 1999

GROUND

RT/CT

VFB

COMP

CURRENT

SENSE

34V

5

4

2

1

3

OSC

ERROR AMP.

+

-

D95IN331

8

6

VREF

5V 50mA

OUTPUT

1/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

i

V

i

I

O

E

O

P

tot

P

tot

T

stg

T

J

T

L

*

All voltages are with respect to pin 5, all currents are positive into the speci f ied ter min al.

PIN CONNECTION (top view)

Supply Voltage (low impedance source) 30 V Supply Voltage (Ii < 30mA) Self Limiting Output Cur re nt

1

±

Output Energy (capacitive load) 5 Analog Inputs (pins 2, 3) – 0.3 to 5.5 V Error Amplifier Output Sink Current 10 mA Power Dissipation at T

≤ 25 °C (Minidip)

amb

Power Dissipation at Tamb ≤ 25 °C (SO8)

1.25 W 800 mW

Storage Temperature Range – 65 to 150 Junction Operating Temperature – 40 to 150 °C Lead Temperature (soldering 10s) 300

Minidi p/ SO 8

A

J

µ

C

°

C

°

COMP

V

I

SENSE

RT/C

1

FB

T

2 3 4

D95IN332

8 7 6 5

V

REF

Vi OUTPUT GROUND

PIN FUNCTIONS

No Function Description

1 COMP This pin is the Error Amplifier output and is made available for loop compensation. 2V

3I

4R

SENSE

T/CT

5 GROUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced

7V 8V

This is the inverting input of the Error Amplifier. It is normally connected to the switching

FB

power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this

information to terminate the output switch conduction. The oscillator frequency and maximum Output duty cycle are programmed by connecting

resistor R

to Vref and cpacitor CT to ground. Operation to 500kHz is possible.

T

and sunk by this pin. This pin is the positive supply of the control IC.

CC

This is the reference output. It provides charging current for capacitor CT through resistor RT.

ref

ORDERING NUMBERS

UC2842BD1; UC3842BD1 UC2843BD1; UC3843BD1 UC2844BD1; UC3844BD1 UC2845BD1; UC3845BD1

2/15

SO8 Minidip

UC2842BN; UC3842BN UC2843BN; UC3843BN UC2844BN; UC3844BN UC2845BN; UC3845BN

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

THERMAL DATA

Symbol Description Minidip SO8 Unit

R

th j-amb

ELECTRICAL CHARACTERISTIC S ( [note 1] Unless otherwise stated , these specificat ions apply for

-25

< T

Thermal Resistance Junction-ambient. max. 100 150

< 85° C for UC284XB; 0 < T

amb

< 70°C for UC384XB; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)

amb

C/W

°

Symbol Parameter Test Conditions

REFERENCE SECTION

V

∆

V

∆

V

∆

REF

Output Voltage

REF

Line Regulation

REF

Load Regulation

REF

Temperature Stability (Note 2) 0.2 0.2

/∆T

T

= 25°C Io = 1mA

j

12V ≤ V 1 ≤ I

≤ 25V

i

≤ 20mA

o

Total Output Variation Line, Load, Temperature 4.9 5.1 4.82 5.18 V

e

Output Noise Voltage

N

10Hz ≤ f ≤ 10KHz T (note 2)

Long Term Stability

T

= 125°C, 1000Hrs

amb

(note 2)

I

Output Short Circuit -30 -100 -180 -30 -100 -180 m A

SC

OSCILLATOR SECTION

f

OSC

Frequency

T

= 25°C

j

T

= T

A

low

to T

high

TJ = 25°C (RT = 6.2k, CT = 1nF)

f

∆

OSC

f

∆

OSC

V I

dischg

Frequency Cha nge wit h V olt. V

/∆V

Frequency Change with Temp. T

/∆T

Oscillator Voltage Swing (peak to peak) – 1.6 – – 1.6 – V

OSC

Discharge Current (V

=2V) TJ = 25°C

OSC

= 12V to 25V – 0.2 1 – 0.2 1 %

CC

= T

to T

A

low

high

T

= T

to T

A

low

high

ERROR AMP SECTION

V

BW Unity Gain Bandwidth T

PSRR Power Supply Rejec. Ratio

Input Voltage V

2

Input Bias Current VFB = 5V -0.1 -1 -0.1 -2

I

b

A

VOL

= 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V

PIN1

2V ≤ Vo ≤ 4V

= 25°C 0.7 1 0.7 1 MHz

J

12V ≤ Vi ≤ 25V

Output Sink Current V

I

o

I

Output Source Current V

o

High V

V

OUT

V

Low V

OUT

= 2.7V V

PIN2

= 2.3V V

PIN2

= 2.3V;

PIN2

= 15KΩ to Ground

R

L

= 2.7V;

PIN2

= 15KΩ to Pin 8

R

L

PIN1

= 5V -0.5 -1 -0.5 -1 mA

PIN1

CURRENT SENSE SECTION

G

V

SVR Supply Voltage Rejection

Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V

V

Maximum Input Signal V

3

Input Bias Current -2 -10 -2 -10

I

b

= 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V

PIN1

12 ≤ V

≤ 25V (note 3)

i

Delay to Output 150 300 150 300 ns

UC284XB UC384XB

Min. Typ. Max. Min. Typ. Max.

Unit

4.95 5.00 5.05 4.90 5.00 5.10 V 220 220mV 325 325mV

mV/°C

= 25°C

j

50 50

µ

525 525mV

KHz

55

52

49

55

52

49

KHz

56

–

48

56

–

48

KHz

275

250

225

275

250

225

–1––0.5–%

7.8

8.3–8.8

7.5

8.8

7.8

7.6

8.3–8.8

8.8mAmA

µ

65 90 65 90 dB

60 70 60 70 dB

= 1.1V 2 12 2 12 mA

5 6.2 5 6.2 V

0.8 1.1 0.8 1.1 V

70 70 dB

µ

V

A

3/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

ELECT RICAL CHAR AC T E RIS T ICS ( co nt inu ed)

Symbol Parameter Test Conditions

OUTPUT SECTION

V

Output Low Level I

OL

Output High Level I

OH

UVLO Saturation VCC = 6V; I

OLS

t

Rise Time

r

Fall Time

t

f

= 20mA 0.1 0.4 0.1 0.4 V

SINK

I

= 200mA 1.6 2.2 1.6 2.2 V

SINK

= 20mA 13 13.5 13 13.5 V

SOURCE

I

= 200mA 12 13.5 12 13.5 V

SOURCE

= 1mA 0.1 1.1 0.1 1.1 V

SINK

T

= 25°C CL = 1nF (2)

j

= 25°C CL = 1nF (2)

T

j

UNDER-VOLTAGE LOCKOUT SECTION

Start Threshold X842B/4B 15 16 17 14.5 16 17.5 V

X843B/5B 7.8 8.4 9.0 7.8 8.4 9.0 V

Min Operating Voltage After Turn-on

X842B/4B 9 10 11 8.5 10 11.5 V X843B/5B 7.0 7.6 8.2 7.0 7.6 8.2 V

PWM SECTION

Maximum Duty Cycle X842B/3B 94 96 100 94 96 100 %

X844B/5B 474850474850 %

Minimum Duty Cycle 0 0 %

TOTAL STANDBY CURRENT

I

Start-up Current Vi = 6.5V for UCX843B/45B 0.3 0.5 0.3 0.5 mA

st

V

= 14V for UCX842B/44B 0.3 0.5 0.3 0.5 mA

i

I

Operating Supply Current V

i

V

Zener Voltage Ii = 25mA 30 36 30 36 V

iz

PIN2

= V

= 0V 12 17 12 17 mA

PIN3

UC284XB UC384XB

Min. Typ. Max. Min. Typ. Max.

50 150 50 150 ns 50 150 50 150 ns

Unit

Notes :

4/15

1. Max package power dissipation l imits must be re specte d; low duty cy cle puls e tec hniques are us ed d urin g tes t maint ain T close to T

2. These parameters, although guarante ed, are not 100% tested in product i on.

3. Parameter measured a t trip poi nt of la tch wi th V

4. Gain defined as : A = ; 0 ≤ V

5. Adjust Vi above the start th reshold bef ore set t i ng at 15 V .

V

∆

V

∆

as possible.

amb

PIN1 PIN3

PIN3

≤ 0.8 V

PIN2

= 0.

as

j

Figure 1: Open Loop Te st Ci rc ui t .

4.7KΩ

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

V

REF

R

T

V

REF

ERROR AMP.

ADJUST

4.7KΩ

1KΩ

100KΩ

I

SENSE

ADJUST

D95IN343

5KΩ

COMP

V

I

SENSE

RT/C

FB

T

1 2

UC2842B

3

4

High peak cur rents assoc iated with capac itive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close

Figure 2: Timing Resistor vs. Oscillator Fre-

quency

T

=100pF

D95IN333

OSC

(KHz)

RT

(KΩ)

C

T

=1nF

T

=200pF

C

T

=500pF

CT=2nF

C

50

20

10

5

2

Vi=15V T

=25˚C

A

1

0.8 10K 20K 30K 50K 100K 200K 300K 500K f

CT=5nF

CT=10nF

A2N2222

7

6

5

0.1µF

V

i

OUTPUT

GROUND

0.1µF

1W

1KΩ

8

C

T

V

i

OUTPUT

GROUND

to pin 5 in a si ngle point ground. The tra ns is to r and 5 KΩ potentiom eter are used to sample the oscillator waveform a nd apply an adjus table ramp to pin 3 .

Figure 3: Output Dead-Time vs. Oscillator Fre-

quency

%

50

30 20

10

5

3 2

1

CT=200pF

10K 20K 30K 50K 100K 200K 300K 500K fOSC(KHz)

CT=1nF

CT=500pF

CT=10nF

CT=100pF

CT=5nF

CT=2nF

Vi=15V T

A

D95IN334

=25˚C

5/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

Figure 4: Oscillator Discharge Current vs. Tem-

perature.

I

dischg

(mA)

Vi=15V V

8.5

8.0

7.5

7.0

-55 -25 0 25 50 75 100 TA(˚C)

OSC

D95IN335

=2V

Figure 6: Error Amp Open-Loop Gain and

Phase vs. Frequency.

(dB)

80

60

40

Gain

Vi=15V V

O

R

L

T

A

D95IN337

=2V to 4V =100K =25˚C

Phase

φ

30

60

90

Figure 5: Maximum Output Duty Cycle vs. Tim-

ing Resistor.

=3.3nF

T

=25˚C

A

D95IN336

D

max

(%)

90

I

=7.5mA

80

70

60

50

40

0.8 RT(KΩ)

dischg

I

=8.8mA

dischg

Vi=15V C T

1235

Figure 7: Current Sense Input Threshold vs. Er-

ror Amp Output Voltage.

V (V)

1.0

0.8

0.6

th

Vi=15V

TA=25˚C

TA=125˚C

D95IN338

20

0

-20 10 100 1K 10K 100K 1M f(Hz)

Figure 8: Reference Voltage Change vs.

Source Current.

60

D95IN339

Vi=15V

50

40

TA=-40˚C

TA=125˚C

30

20

10

0

0 20406080100I

=25˚C

A

T

ref

120

150

180

(mA)

0.4

TA=-40˚C

0.2

0.0 0246V

(V)

O

Figure 9: Reference Short Circuit Current vs.

Temperature.

≤0.1Ω

L

D95IN340

I

SC

(mA)

100

90

80

70

60

50

-55 -25 0 25 50 75 100 TA(˚C)

Vi=15V R

6/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

Figure 10: Output Saturation Voltagevs. Load

Figure 11: Supply Current vs. Supply Voltage.

Current.

V

sat

(V)

V

-1

-2 Vi=15V

80µs Pulsed Load 120Hz Rate

3

2

1

0

0 200 400 600 IO(mA)

Source Saturation

i

(Load to Ground)

TA=25˚C

TA=-40˚C

Sink Saturation (Load to V

)

i

TA=-40˚C

TA=25˚C

D95IN341

GND

I

i

(mA)

20

15

10

5

0

UCX843/45

0 102030V

UCX842/44

RT=10K C

T

V

FB

I

Sense

T

A

Figure 12: Output Waveform. Figure 13: Output Cross Conduction

Vi =15V

= 1.0nF

C

90%

L

= 25°C

T

A

V

O

D95IN342

=3.3nF

=0V

=25˚C

Vi =30V

= 15pF

C

L

= 25°C

T

A

(V)

i

20V/DIV

10%

50ns/DIV

Figure 14: Oscillator and Output Waveforms.

V

i

7

8

PWM

R

T

4

I

C

T

5V REG

CLOCK

OSCILLATOR

D

5

GND

6

I

CC

OUTPUT

CT

100ns/DIV

LARGE R

SMALL R

/SMALL C

T

/LARGE C

T

D95IN344

100mA/DIV

T

7/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

Figure 15 : Error Amp C onfiguration.

V

Z

i

Figure 16 : Under Voltage Lockout.

Z

f

FB

COMP

2.5V

1mA

+

2

-

1

D95IN345

V

i

7

ON/OFF COMMAND

TO REST OF IC

UC3842B UC3844B

V

ON

V

OFF

Figure 17 : Current Sens e Cir c uit .

I

S

COMP

R

CURRENT

CR

S

D95IN347

SENSE

UC3843B UC3845B

16V 8.4V

10V 7.6V

1

3

5

GND

ERROR

AMPL.

<17mA

<0.5mA

D95IN346

I

CC

V

OFFVON

During UVLO, the Output is l ow

2R

R1V

COMPARATOR

CURRENT

SENSE

V

CC

Peak curre nt (is) is determ ine d by th e form u la

≈

1.0 V R

S

I

S max

A small RC filt er ma y b e re quir ed to sup pres s s w it ch tran si ent s .

8/15

Figure 18 : Slope Compe ns at ion T ec hni ques.

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

V

REG

8

R

T

R

C

T

I

SENSE

T/CT

4

UC3842B

3

5

I

S

R

SLOPE

R

1

R

S

I

S

R

SLOPE

R

1

R

S

GND

Figure 19 : Isolated MOS FE T D riv e and Current Tran sfor m er Se ns ing .

V

CC

7

V

REG

8

R

T

R

T/CT

4

C

T

I

SENSE

UC3842B

3

5

GND

D95IN348

V

in

5.0V

+

-

+

ref

S

Q

R

COMP/LATCH

C

ISOLATION

BOUNDARY

R

S

VGS Waveforms

Q1

N

S

+ 0

50% DC 25% DC

V

I

=

pk

N

P

(pin 1)

3R

-1.4

S

+ 0

--

N

S

()

N

P

+

-

6

3

D95IN349

9/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

Figure 20 : Latched Shutdown.

2N

3905

SCR must be selected for a holding current of less than 0.5mA at T The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.

Figure 21: Error Amplifier Compensation

2N

3903

4

8

2

1

R

+

EA

OSC

BIAS

+

1mA

2R

R

5

D95IN350

.

A(min)

EA

+

1mA

2R

R

5

From V

O

R

i

R

C

d

f

2.5V

+

-

2

R

f

1

Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.

EA

+

1mA

2R

R

D95IN351

5

From V

R

P

C

P

O

R

i

R

C

d

f

2.5V

+

-

2

R

f

1

Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.

10/15

Figure 22: External Clock Synchronization.

V

R

T

REF

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

8

R

BIAS

R

4

C

T

+

EXTERNAL

SYNC INPUT

0.01µF

47Ω

+

2

EA

1

The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of C

to go more than 300mV below ground

T

Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.

V

REF

R

A

8

OSC

2R

R

5

D95IN352

R

f =

B

C

(R

1.44

+ 2RB)C

A

84

5K 6 5

5K

2

5K

+

-

+

-

1

D

=

max

RA + 2R

R

B

R

Q

S

NE555

B

3

7

BIAS

RR

4

+

2

EA

1

TO ADDITIONAL

UCX84XAs

OSC

2R

R

5

D95IN353

11/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

Figure 24: Soft-Start Circuit

8

R

BIAS

R

4

+

OSC

1mA

2R

R

1MΩ

+

2

EA

1

C

5

Figure 25: Soft-Start and Error Amplifier Output Duty Cycle Clamp.

5V

1V

ref

+

-

S

+

-

D95IN354

Q

R

V

CC

in

C

12/15

R2

R1

8

4

2

1

BC109

7

Q

V

CLAMP

+

-

7

6

5

R

S

D95IN355

Q1

R

S

5V

ref

R

BIAS

R

1

R1 + R

OSC

2R

R

where 0 <V

2

V

Clamp

5

CLAMP

+

1mA

+

EA

V

= ·

CLAMP

+

-

+

1V

<1V I

S

R

Comp/Latch

=

pk(max)

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

DIM.

D (1) 4.8 5.0 0.189 0.197

F (1) 3.8 4.0 0.15 0 .157

(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.75 0 .069 a1 0.1 0.25 0.004 0.010 a2 1.65 0.065 a3 0.65 0.85 0.026 0.033

b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010

C 0.25 0.5 0.010 0.020

c1 45° (typ.)

E 5.8 6.2 0.228 0.244

e 1.27 0.050 e3 3.81 0.150

L 0.4 1.27 0.016 0.050

M 0.6 0.024

S8° (max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO8

13/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200 L 3.18 3.81 0.125 0.150 Z 1.52 0.060

mm inch

OUTLINE AND

MECHANICAL DATA

Minidip

14/15

UC2842B/3B/4B/5B - UC3842B/3B/4B/5B

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