STMicroelectronics TDA7326, TDA7326D Schematic [ru]
AM-FM RADIO FREQUENCY SYNTHESIZER
FM INPUT AND PRECOUNTER FOR UP TO
140MHz
AM INPUTFOR UP TO 40MHz
6-BIT SWALLOW COUNTER, 8-BIT PRO-
GRAMMABLE COUNTER FOR FM ANDSW
14-BIT PROGRAMMABLE COUNTER FOR
LWAND MW
THREEWIRES 8-BITSERIALINTERFACE
ON-CHIP REFERENCE OSCILLATOR AND
COUNTER
PROGRAMMABLE SCANNING STEPS FOR
AM ANDFM
DIGITALPHASEDETECTOR AND LOOP FIL-
TER
TWO SEPARATE FREE PROGRAMMABLE
FILTERAPPLICATIONS AVAILABLE
TUNINGVOLTAGE OUTPUT0.5 TO 9.5V
PROGRAMMABLE CURRENT SOURCES TO
SET THE LOOP GAIN
ON-CHIPPOWER ON RESET
STANDBYMODE
TDA7326
DIP16
SO16W
ORDERING NUMBERS: TDA7326 (DIP16)
TDA7326D (SO16W)
DESCRIPTION
The TDA7326 is a PLL frequency synthesizer in
CMOStechnology that performs all the functionof
a PLL radio tuning system for FM and AM (LW,
MW, SW)
BLOCKDIAGRAM
July 1994
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TDA7326
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD1-VSS
V
DD2-VSS
V
IN
V
OUT
I
IN
I
OUT
T
stg
T
A
PIN CONNECTION
Supply Voltage - 0.3 to + 7 V
Supply Voltage - 0.3 to + 12 V
Input Voltage VSS - 0.3 to VDD+ 0.3 V
Output Voltage VSS - 0.3 to VDD+ 0.3 V
Input Current - 10 to + 10 mA
Output Current - 10 to + 10 mA
Storage Temperature - 55 to + 125
Ambient Temperature -40 to + 85
o
C
o
C
THERMALDATA
Symbol Parameter DIP 16 SO 16L Unit
th j-amb Thermal Resistance Junction-ambient 100 200 °C/W
R
Figure 1:Input Sensitivity
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TDA7326
ELECTRICAL CHARACTERISTICS (Tamb =25°C;VDD1 = 5V; VDD2 =9VfOSC = 4MHz; RISET =68KΩ;
unlessotherwisespecified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
DD1 Supply Voltage 4.5 5.0 5.5 V
V
DD2 Supply Voltage 9.0 10.0 V
V
DD1 FM Supply Current no output load, FM mode,
I
f
in = 100MHz
DD1 AM Supply Current no output load, AM mode,
I
fin= 1MHz
I
DD1 STB Supply Current Standby mode 3 20 µA
DD2 Supply Current 0.5 2 3 mA
I
REF Voltage at pin 3 3.0 3.5 4.0 V
V
iSET Voltage at pin 2 RiSET = 68KΩ 7.0 8.0 9.0 V
V
RF INPUT (AMIN FMIN)
fiAM Input Frequency AM DirectMode, Vin= 50mV 0.5 20 MHz
Swallow Mode, V
iFM InputFrequency FM Sinus, V
f
iAM Input Voltage AM Direct Mode
V
= 50mV 30 140 MHz
in
= 50mV 16 40 MHz
in
0.6 to 16MHz (Sinus)
Swallow Mode
16 to 40MHz (Sinus)
V
iFM Input Voltage FM 70 to 120MHz (Sinus) 30 600 mVrms
in Input Impedance FM fin= 120MHz 200 Ω
Z
in Input Impedance AM fin= 12MHz 1400 Ω
Z
OSCILLATOR
10 18 25 mA
3 5 10 mA
40 600 mVrms
40 600 mVrms
fOSC Oscillator Frequency 4 MHz
bu Built Up Time Euro-Quartz ITT 100 ms
t
in Internal Capacitance 9 pF
C
OUT Internal Capacitance 9 pF
C
in Input Impedance 4 15 KΩ
Z
in Input Voltage 0.5 V
V
DD1
PLL CHARACTERISTICS
fstep Step Width AM 1/2.5 KHz
step Step Width FM 12.5/25 KHz
f
ref Ref Frequency AM 1/2.5 KHz
f
ref Ref Frequency FM 12.5/25 KHz
f
LOOP FILTER INPUT (LPIN1,LPIN2 =PIN 15,16)
-Iin Input Leakage Current VIN= VSS; Phase Detector
Output = Tristate
I
in Input Leakage Current VIN = VDD; Phase Detector
Output = Tristate
-1 -0.1 µA
0.1 +1 µA
Vpp
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TDA7326
ELECTRICALCHARACTERISTICS (continued)
LOOP FILTER OUTPUT (LP
Symbol Parameter Test Condition Min. Typ. Max. Unit
OL Output Voltage Low ILOAD = 0.2mA VDD2;= 10V 0.5 0.8 V
v
OH Output Voltage High -ILOAD = 0.2mA VDD2; = 10V 9 9.5 V
V
CHARGE PUMP CURRENT GENERATION (LPIN1,LPIN2 = PIN 15,16)
Isi Sink Current LPIN1,2 CURR1 = 0, CURR2 = 0 2 5 7 µA
so Source CurrentLPIN1,2 CURR1 = 0, CURR2 = 0 2 5 7 µA
-I
DOUT1 OPENDRAIN OUTPUT(PIN9)
vOL Output Voltage Low ILOAD = 1mA 0.2 0.5 V
BUS INTERFACE
-IIL Input Leakage Current VIN = VSS -1 0.1 1 µA
IH Input Leakage Current VIN = VSS -1 0.1 1 µA
I
IH Input Voltage High Leading edge 3.4 4.0 V
v
IL Input Voltage Low Leadingedge 1.0 1.6 V
V
BUS INTERFACE, WAITINGTIME (see fig.5) The Data is Acquiredat the High → Low ClockTransition
OUT = PIN 14)
CURR1 = 0, CURR2 = 1 120 200 280 µA
CURR1 = 1, CURR2 = 1 180 300 420 µA
CURR1 = 1, CURR2 = 0 370 500 630 µA
CURR1 = 0, CURR2 = 1 120 200 280 µA
CURR1 = 1, CURR2 = 1 180 300 420 µA
CURR1 = 1, CURR2 = 0 370 500 630 µA
t1 CLK Low to DLEN L → H 0.2 µs
3 DATA Transition to CLK H → L 0.1 µs
t
5 CLK H → L to DATA Transition 0.4 µs
t
BUS INTERFACE, DATA REPETITION TIME (see fig. 5)
tr1 Release Time Between 2 bytes,
except byte 4
t
r2 Release Time after the
transmission of byte 4
FM mode 180 µs
AM mode 2 ms
5 µs
BUS INTERFACE, SETUPTIME (see fig.5)
t2 DLEN High to CLK L → H 0.1 µs
BUS INTERFACE, HOLD TIME (see fig.5)
t4 DATA Transition to CKL L → H0µs
6CLK H → L toDLEN H → L 0.4 µs
t
CLK CLK Frequency 500 KHz
f
Duty Cycle 50 %
pl Clock Pulse Low 1 µs
t
ph Clock Pulse High 1 µs
t
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TDA7326
2.0 GENERAL DESCRIPTION
This circuit contains a frequency synthesizer and
a loop filter for an FM and AM radio tuning system. Only a V
is required to build a complete
CO
PLLsystem.
For FM and SW application, the counter works in
a twostages configuration.
The first stage is a swallow counter with a four
modulus(:32/33/64/65)precounter.
The loopgain can be set for different conditions.
After a power on reset, all registers are reset to
zero andthe standbymode is activated.
In standby mode, oscillator, reference counter,
AM input and FM input are stopped. The power
consumption is reducedto a minimum.
3.0 DETAILED DESCRIPTION OF THE PLL
FREQUENCYSYNTHESIZER
The second stage is an 8-bit programmable
counter.
For LW and MWapplication, a 14-bit programmable counteris available.
Thecircuit receives the scaling factors for the pro-
3.1 INPUT AMPLIFIERS
The signals applied on AM and FM input are amplified to get a logic level in order to drive the fre-
quency dividers.
grammable counters and the values of the reference frequencies via a three line serial bus interface.
The reference frequencyis generatedby a 4MHz
XTALoscillatorfollowed bythe reference divider.
An external oscillator (f = 4MHz) can be used instead of the internal one; it must be connectedto
OSCIN (pin 7).
3.1.1 Input Impedance
The typical input impedance: for the FM input
is 200Ω and forAM input is 1.4kΩ.
3.1.2 Input sensitivity
(seeFigures 1a and 1b).
The reference step-frequency is 1 or 2.5kHz for
AM. For FM mode a step frequency of 12.5 and
25kHzcan be selected.
The circuit checks the format of the received data
words.
Valid data in the interface shift register are stored
automatically in buffer registers at the end of
transmission.
The output signals of the phase detector are
switching the programmablecurrent sources.
Their currents are integrated in the loop filter to a
DC voltage.The values of the current sources are
programmable by two bits also received via the
serialbus.
The loop filter amplifier is supplied by a separate
positive power supply, to minimize the noise in-
3.2 DATAAND CONTROLREGISTER
3.2.1 Register Location
The data registers (bit2...bit7) for the control
register and the data registers PC7...PC0,
SC5...SC0 for the counters are organized in
fourwords, identified by two addressbits (bit 7
and bit 6), bit 7 is the first bit to be sentby the
controller, bit0 is the last one. The order and
the number of the bytes to be transmitted is
free of choice. The modification of the
PC7...PC0 registers is valid for the internal
counters only after transmission of byte 4
(SC5...SC0).
duced by the digitalpart of thesystem.
3.2.2 CONTROL ANDSTATUS REGISTERS
RegisterConfiguration
ADDRESS BITS DATA BITS
BYTE MSB-BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 0
Function adr 0 adr 1 data 0 data 1 data 2 data 3 data 4 data 5
byte1 0 0 test 0 test 1 test 2 SOUT CURR2 f
byte2 0 1 PC7 PC6 LPF1/2 CURR 1 SWM/DIR AM/FM
byte3 1 0 PC5 PC4 PC3 PC2 PC1 PC0
byte4 1 1 SC5 SC4 SC3 SC2 SC1 SC0
REF
REGISTER NAME FUNCTION
SWM/DIR Swallow direct-mode switch 1 = SWM, 0 = DIR
AM/FM AM - FM band switch 1=AM, 0 = FM
REF Selection of reference frequency (see table 3.4)
f
CURR1 Current select of change pump
CURR2 Current select of change pump
LPF1/LPF2 Loop filter input select1= I
SOUT Switch output condition 1=output high,0 = output low
PF1,0=IPF2
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TDA7326
3.3 DIVIDER FROM VCOFREQUENCYTO
REFERENCEFREQUENCY
This divider provides a low frequency f
SYN
which
is phase compared with the reference frequency
f
.
REF
3.4 OPERATINGMODE
Four operating modes are available:
- FM mode,
- AMswallow mode,
- AMdirect mode,
- Standbymode
They are user programmable with the SWR/DIR
and AM/FM bits in the byte 2.
Standby mode: all functions are stopped. This allowslow current consumptionwithout lost of informationin all register, it is activatedby forcing bit 0
(AM/FM)and bit 1 (SWM/DIR)both at zero value.
MODE SECTION SWM/DIR AM/FM
STAND-BY 0 0
FM 1 0
AM SWALLOW 0 1
AM DIRECT 1 1
3.4.1 FM and AM (SW) Operation (Swallow
Mode)
The FM or AM signal is applied to a four
modulus: 32/33/64/65 high speed prescaler,
which is controlled by a 6 bit divider ’A’.This
divider is controlled by the 6 bit SC register.
In parallel the output of the prescaler is connected to a 8 bit divider ’B’. This divider is
controlled by the 8 bit PC register. For FM
mode with 25kHz reference frequency operation, the divider A is a 5 bit divider. The high
speed prescaler is working in : 32/33 dividing
mode. Bit 6 of the SC register has to be kept
to ”0”.
Dividing range calculation :
For FM mode with 12.5kHz reference frequencyand SWswallow modeoperation :
=[65⋅A1+(B1+1 -A1)⋅64 ]. f
f
VCO
f
= (64⋅ B1+A1+64) ⋅ f
VCO
REF
REF
or
Important : For correctoperation B ≥ 64 and B
≥ A.
At FM mode with25kHz referencefrequency :
=[33⋅A2+(B2+1-A2)⋅32 ]⋅ f
f
VCO
f
= (32 ⋅ B2+A2+ 32) ⋅ f
VCO
REF
REF
Important:For correct operation B ≥ 32 and B
≥ A.
A and B are variable values of the dividers.
To keep the actual tuning frequency after a
modification of the reference frequency, the
values of the dividers have to be modified in
the followingway.
Switching from 25kHz to 12.5kHz reference
frequency: B
1=B2,A1=A2
⋅2
Switching from 12.5kHz to 25kHz reference
frequency:
2=B1
,A2=
2
B
A
for odd values A
1
and A
.
1
(A
+ 1)
1
=
2
2
The AM signal is directly applied to the 14 bit
static divider ’C’. This divider is controlled by
both SC and PC registers.
Dividing range:
f
=(C+1)⋅f
VCO
REF
Figure2: FM and AM (SW) operation(swallow mode)
OSC IN
AM IN
FM IN
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PREDIVIDER
R
REGISTER
SC5 .. SC0
COUNTER
A
PREDIVIDER
M/M+1
fref
fsyn
PD
REGISTER
PC7 .. PC0
COUNTER
B
D94AU101
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