STMicroelectronics STP5NK100Z, STF5NK100Z, STW5NK100Z Technical data
STP5NK100Z - STF5NK100Z
STW5NK100Z
N-CHANNEL 1000V - 2.7Ω - 3.5A TO-220/TO-220FP/TO-247
Zener-Protected SuperMESH™MOSFET
Table 1: General Features
TYPE V
STF5NK100Z
STP5NK100Z
STW5NK100Z
■ TYPICAL R
■ EXTREMELY HIGH dv /d t CAPABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
DSSRDS(on)
1000 V
1000 V
1000 V
(on) = 2.7 Ω
DS
< 3.7 Ω
< 3.7 Ω
< 3.7 Ω
I
D
3.5 A (*)
3.5 A
3.5 A
Pw
30 W
125 W
125 W
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained thro ugh an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFET s including revolutionary MDmesh™ products.
Figure 1: Package
TO-220
TO-247
2
1
TO-220FP
3
Figure 2: Internal Schematic Diagram
3
2
1
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL F OR OFF-LINE POWER SUP PLIE S
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STF5NK100Z F5NK100Z TO-220FP TUBE
STP5NK100Z P5NK100Z TO-220 TUBE
STW5NK100Z W15NK100Z TO-247 TUBE
Rev. 3
1/13September 2005
STP5NK100Z - STF5NK100Z - STW5NK100Z
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
STP5NK100Z
STW5NK100Z
V
I
V
V
DM
P
DS
DGR
GS
I
D
I
D
TOT
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
()
Drain Current (pulsed) 14 14 (*) A
Total Dissipation at TC = 25°C
3.5 3.5 (*) A
2.2 2.2 (*) A
125 30 W
Derating Factor 1 0.24 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
T
j
T
stg
() Pulse width limited by safe operat i ng area
≤3.5A, di/dt ≤200A/µs, VDD ≤ V
(1) I
SD
(*) Limited only by maximum temperature allowed
Insulation Withstand Voltage (DC) - 2500 V
Operating Junction Temperature
Storage Temperature
, Tj ≤ T
(BR)DSS
JMAX.
-55 to 150
-55 to 150
Table 4: Thermal Data
TO-220
TO-247
Rthj-case Thermal Resistance Junction-case Max 1 4.2 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
STF5NK100Z
1000 V
1000 V
TO-220FP
300 °C
°C
°C
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
3.5 A
250 mJ
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only t he device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to p r otect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/13
STP5NK100Z - STF5NK100Z - ST W5NK100Z
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 0 1000 V
Voltage
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
= Max Rating
DS
V
= Max Rating,
DS
1
50
TC = 125°C
I
GSS
V
GS(th)
R
DS(on)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= ± 20 V ± 10 µA
GS
V
= VGS, ID = 100 µA 3
DS
3.75
4.5 V
VGS = 10 V, ID = 1.75 A 2.7 3.7 Ω
Resistance
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS = 15 V , ID = 1.75 A 4 S
fs
C
C
iss
C
oss
C
rss
oss eq
t
d(on)
t
r
t
d(off)
t
Q
Q
gs
Q
gd
f
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
= 25 V, f = 1 MHz,
V
DS
VGS = 0
1154
106
21.3
(3).Equivalent Outpu t Capacitance VGS = 0 V, VDS = 0 to 800 V 46.8 pF
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 500 V, ID = 1.75 A,
V
DD
R
= 4.7 Ω, V
G
GS
(see Figure 21)
= 800 V, ID = 3.5 A,
V
DD
V
= 10 V
GS
(see Figure 24)
= 10 V
22.5
7.7
51.5
19
42
7.3
21.7
59 nC
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse du rat i on = 300 µs, du ty cycle 1.5 % .
(2) Pulse width limited by safe operating area.
(3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 3.5 A, VGS = 0
= 3.5 A, di/dt = 100 A/µs
I
SD
V
= 35V
DD
(see Figure 22)
= 3.5 A, di/dt = 100 A/µs
I
SD
VDD = 35V, Tj = 150°C
(see Figure 22)
605
3.09
10.5
742
4.2
11.2
when VDS increase s from 0 to 80% V
oss
3.5
14
1.6 V
A
A
ns
µC
A
ns
µC
A
DSS
3/13
.
STP5NK100Z - STF5NK100Z - STW5NK100Z
Figure 3: Safe Operating Area For TO-220
Figure 4: Safe Operating Area For TO-220FP
Figure 6: Thermal Impedance TO-220
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Safe Operating Area For TO-247
4/13
Figure 8: Thermal Impedance For TO-247
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