ST MICROELECTRONICS STW26NM60N Datasheet

December 2016
DocID025246 Rev 2
1/12
www.st.com
STW26NM60N
N-channel 600 V, 0.135 Ω typ., 20 A MDmesh™ II
Power MOSFET in a TO-247 package
Datasheet - production data
Order code
VDS
R
DS(on)
max
ID
STW26NM60N
600 V
0.165 Ω
20 A
Order code
Marking
Package
Packaging
STW26NM60N
26NM60N
TO-247
Tube
TO-247
1
2
3
AM01475v1_noTab_noZen
D(2)
G(1)
S(3)
Features
100% avalanche tested  Low input capacitance and gate charge  Low gate input resistance
Applications
Switching applications
Description
Figure 1: Internal schematic diagram
Table 1: Device summary
This device is an N-channel Power MOSFET developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters.
Contents
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Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 TO-247 package information ............................................................. 9
5 Revision history ............................................................................ 11
STW26NM60N
Electrical ratings
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Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
600 V VGS
Gate-source voltage
±30 V ID
Drain current (continuous) at TC = 25 °C
20 A ID
Drain current (continuous) at TC = 100 °C
12.6
A
I
DM
(1)
Drain current (pulsed)
80 A P
TOT
Total dissipation at TC = 25 °C
140
W
dv/dt
(2)
Peak diode recovery voltage slope
15
V/ns
T
stg
Storage temperature range
-55 to 150
°C
Tj
Operating junction temperature range
Notes:
(1)
Pulse width limited by safe operating area.
(2)
ISD ≤ 20 A, di/dt ≤ 400 A/µs, V
DS(peak)
≤ V
(BR)DSS, VDD
≤ 80% V
(BR)DSS
Symbol
Parameter
Value
Unit
R
thj-case
Thermal resistance junction-case
0.89
°C/W
R
thj-amb
Thermal resistance junction-ambient
50
°C/W
Symbol
Parameter
Value
Unit
IAS
Single pulse avalanche current (pulse width limited by T
jmax
)
6
A
EAS
Single pulse avalanche energy (starting TJ=25 °C, ID=IAS, VDD=50 V)
610
mJ
1 Electrical ratings
Table 2: Absolute maximum ratings
Table 3: Thermal data
Table 4: Avalanche characteristics
Electrical characteristics
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source breakdown voltage
ID = 1 mA, VGS = 0 V
600
V
I
DSS
Zero gate voltage drain current
VGS = 0 V, VDS = 600 V
1
µA
VGS = 0 V, VDS = 600 V, TC= 125 °C
(1)
100
I
GSS
Gate-body leakage current
VDS = 0 V, VGS = ±25 V
±0.1
µA
V
GS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
2 3 4
V
R
DS(on)
Static drain-source on­resistance
VGS = 10 V, ID = 10 A
0.135
0.165
Ω
Notes:
(1)
Defined by design, not subject to production test.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
C
iss
Input capacitance
VDS = 50 V, f = 1 MHz, VGS = 0 V
-
1800 - pF
C
oss
Output capacitance
-
115 - pF
C
rss
Reverse transfer capacitance
- 6 -
pF
C
oss eq.
(1)
Equivalent output capacitance
VGS = 0 V, VDS = 0 to 480 V
-
310 - pF
Qg
Total gate charge
VDD = 480 V, ID = 20 A, VGS = 10 V
(see Figure 14: "Test circuit for
gate charge behavior")
-
60 - nC
Qgs
Gate-source charge
-
8.5 - nC
Qgd
Gate-drain charge
-
30 - nC
RG
Gate input resistance
f=1 MHz, ID=0 A
-
2.8 - Ω
Notes:
(1)
C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when VDS
increases from 0 to 80% V
DS
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on delay time
VDD = 300 V, ID = 10 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for
resistive load switching times"
and Figure 18: "Switching time
waveform")
-
13 - ns
tr
Rise time
-
25 - ns
t
d(off)
Turn-off delay time
-
85 - ns
tf
Fall time
-
50 - ns
2 Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 5: On/off states
Table 6: Dynamic
Table 7: Switching times
STW26NM60N
Electrical characteristics
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Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source-drain current
-
20
A
I
SDM
(1)
Source-drain current (pulsed)
-
80
A V
SD
(2)
Forward on voltage
ISD = 20 A, VGS = 0 V
-
1.5 V trr
Reverse recovery time
ISD = 20 A, di/dt = 100 A/µs VDD = 60 V
(see Figure 15: "Test circuit for
inductive load switching and diode recovery times")
-
370
ns
Qrr
Reverse recovery charge
-
5.8
µC
I
RRM
Reverse recovery current
-
31.6 A trr
Reverse recovery time
ISD = 20 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C
(see Figure 15: "Test circuit for
inductive load switching and diode recovery times" )
-
450
ns
Qrr
Reverse recovery charge
-
7.5
µC
I
RRM
Reverse recovery current
-
32.5 A
Notes:
(1)
Pulse width limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 8: Source-drain diode
Electrical characteristics
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Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Static drain-source on-resistance
Figure 7: Gate charge vs gate-source voltage
W
2.1 Electrical characteristics (curves)
STW26NM60N
Electrical characteristics
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Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage vs
temperature
Figure 10: Normalized on-resistance vs temperature
Figure 11: Source-drain diode forward
characteristics
Figure 12: Normalized V
(BR)DSS
vs temperature
Test circuits
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Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
3 Test circuits
STW26NM60N
Package information
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0075325_8
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 TO-247 package information
Figure 19: TO-247 package outline
Package information
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Dim.
mm
Min.
Typ.
Max.
A
4.85
5.15
A1
2.20
2.60 b 1.0
1.40
b1
2.0
2.40
b2
3.0
3.40
c
0.40
0.80
D
19.85
20.15
E
15.45
15.75
e
5.30
5.45
5.60
L
14.20
14.80
L1
3.70
4.30
L2
18.50
ØP
3.55
3.65
ØR
4.50
5.50
S
5.30
5.50
5.70
Table 9: TO-247 package mechanical data
STW26NM60N
Revision history
DocID025246 Rev 2
11/12
Date
Revision
Changes
07-Jul-2016
1
First release.
12-Dec-2016
2
Modified Table 6: "Dynamic" and Table 8: "Source-drain diode" Modified Section 2.1: "Electrical characteristics (curves)" Minor text changes
5 Revision history
Table 10: Document revision history
STW26NM60N
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