The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down,specialcareis taken to ensur e a very good dv/dt capability for the
most dem anding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDm es h™ products.
STP9NK50Z - STP9NK50ZF P - STB9NK50Z - STB9NK50Z-1
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
STP9NK50Z
STB9NK50Z
STB9NK50Z-1
I
V
DM
P
V
DGR
V
I
I
TOT
DS
GS
D
D
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
Gate- source Voltage± 30V
Drain Current (continuous) at TC=25°C
Drain Current (continuous) at TC= 100°C
()
Drain Current (pulsed)28.828.8 (*)A
Total Dissipation at TC=25°C
7.27.2 (*)A
4.54.5 (*)A
11030W
Derating Factor0.880.24W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ)3500V
dv/dt (1)Peak Diode Recovery voltage slope4.5V/ns
V
ISO
T
j
T
stg
() Pulse width limited by safe operating area
≤7.2A, di/dt ≤200A/µs, VDD≤ V
(1) I
SD
(*) Limited only by maximum temperature allowed
Insulation Withstand Voltage (DC)-2500V
Operating Junction Temperature
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
=25°C, ID=IAR,VDD=50V)
j
7.2A
190mJ
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to souce. In this respect the Zener voltage is appropriate to achieve an efficient and c osteffective intervention to prote ct the d ev ice’s integrity. These integrated Zener diodes thus avoid the usage
of external component s.
2/13
Page 3
STP9NK50Z - STP9NK50ZFP - STB9NK50Z - STB9NK50Z-1
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLES S OTHE RWISE SPECIFIED)
ON/OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Zero Gate Voltage
Drain Current (V
GS
=0)
Gate-body Leakage
Current (V
DS
=0)
Gate Threshold Voltage
Static Drain-source On
Resistance
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(1)Forward TransconductanceVDS=15V,ID= 3.6 A5.3S
fs
C
oss eq.
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3)Equivalent Output
Capacitance
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of u se of suc h informat ion n or for any in fring ement of paten ts or oth er ri ghts of th ird part ies whic h may resul t from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners