Page 1
N-CHANNEL 1000V - 1.60Ω - 6.5A - TO-220 - TO-220FP
1
3
1
3
General features
STF8NK100Z
STP8NK100Z
Zener-Protected SuperMESH™ MOSFET
Type
STF8NK100Z
STP8NK100Z
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE RATED
■ IMPROVED ESD CAPABILITY
■ VERY LOW INTRINSIC CAPACITANCE
V
DSSRDS(on)
1000 V
1000 V
<1.85Ω
<1.85Ω
I
D
6.5 ANote 1
6.5 A
Pw
40 W
160 W
Description
The SuperMESH™ seri es is obt ained throug h an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down, spec ial
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Applications
2
TO-220
2
TO-220FP
Internal schematic di agram
■ HIGH CURRENT,SWITCHING APPLICATION
■ IDEAL FOR OFF-LINE POWER SUPPLIES
Order codes
Sales Type Marking Package Packaging
STF8NK100Z F8NK100Z TO-220FP TUBE
STP8NK100Z P8NK100Z TO-220 TUBE
Rev 1
November 2005 1/13
www.st.com
13
Page 2
1 Electrical ratings STF8NK100Z - STP8NK100Z
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
TO-220 TO-220FP
V
DS
V
DGR
V
GS
I
Note 1 Drain Current (conti nuous) at TC = 25°C
D
I
D
I
Note 2
DM
P
TOT
Drain-source Voltage (VGS=0)
1000 V
Drain-gate Voltage 1000 V
Gate-Source Voltage ± 30 V
6.5 6.5 A
Drain Current (continuous) at TC = 100°C
4.3 4.3 A
Drain Current (pulsed ) 16 16 A
Total Dissipation at TC = 25°C
160 40 W
Derating Factor 1.28 0.32 W/°C
V
ESD(G-S)
Gate source ESD (HBM-C=100pF, R=1.5 KΩ) 4000 V
dv/dt Note 3 Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
T
T
stg
Insulation Withst and Voltage (DC) -- 2500 V
Operating Junction Temperature
j
Storage Temperature
-55 to 150 °C
Table 2. Thermal data
TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 0.78 3.1 ° C /W
Rthj-a Thermal Resist ance Junction-ambie nt Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering
Purpose
300 °C
Table 3. Avalanche Characteristics
Symbol Parameter Value Unit
I
AR
E
AS
2/13
Avalanche Current, Repetitive or
Not-Repetitive (pulse width limited by Tj max)
Single Pulse A valanche Energy
(startin g T j= 25 °C , I
D=IAR
, VDD=50V)
6.5 A
320 mJ
Page 3
STF8NK100Z - STP8NK100Z 2 Electrical characteristics
2 Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 4. On/off states
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-Source Breakdown
Voltage
Zero Gate Voltage Drain
Current (V
GS
= 0)
Gate Body Leakage Current
= 0)
(V
DS
Gate Threshold Voltage
St ati c Drai n-Source On
Resistance
I
= 1mA, VGS= 0
D
= Max Ra ting,
V
DS
= Max Rating,Tc = 125°C
V
DS
= ±20V
V
GS
= VGS, ID = 100 µA
V
DS
V
= 10 V, ID= 3.15 A
GS
1000 V
1
50
±10 µA
33.754.5 V
1.60 1.85 Ω
Table 5. Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
Note 6
fs
C
iss
C
oss
C
rss
C
oss eq.
Note 5
Forward Transconductance
Input Capacitance
Outp u t C a pacita nce
Rev er se Trans fer Capa citan ce
Equivalent Outp ut
Capacitance
V
=15V, ID=3.15 A
DS
=25V, f=1 MHz, VGS=0
V
DS
=0V, VDS=0 to 800V
V
GS
7S
2180
174
36
83 pF
µA
µA
pF
pF
pF
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
=800V, ID = 6.3A
V
DD
=10V
V
GS
(see Figure 17)
73
12
40
102 nC
nC
nC
3/13
Page 4
2 Electric al characteristic s STF8NK100Z - STP8NK100Z
Table 6. Switching times
Symbol Parameter Test Conditions Min. Typ. Max. Unit
=500 V, ID= 3.15 A,
V
t
d(on)
t
d(off)
Tur n-on Delay Tim e
t
r
Rise Time
Turn-off Delay Time
t
f
FallTime
DD
=4.7Ω, VGS=10V
R
G
(see Figure 18)
=500 V, ID=3.15 A,
V
DD
R
=4.7Ω, VGS=10V
G
(see Figure 18)
28
19
59
30
ns
ns
ns
ns
Table 7. Source drain diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SDM
V
SD
I
I
I
SD
Note 3
Note 2
t
rr
Q
rr
RRM
t
rr
Q
rr
RRM
Source-drain Current
Source-drain Current (pulsed)
Forward on Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD=6.3A, VGS=0
=6.3A, d i /d t = 100 A /µs,
I
SD
V
=50 V, Tj=25°C
DD
=6.3A, d i /d t = 100 A /µs,
I
SD
V
=50 V, Tj=150°C
DD
620
5.3
17
840
7.5
18
6.5
26
1.6 V
µC
µC
Table 8. Gate-source zener diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Note 4
(1) Limited only by maximum temp erature al lowed
≤ 6.5 A, di/dt ≤ 200A/µs, VDS ≤ V
(2)I
SD
(3) Puls e width limited by safe operating area
(4) The built-in-back-to-back Zener diodes have specifically been designed to enanche not only the device’s ESD capability, but
also to make them safely absorb possible voltage is appropriate to archieve an efficient and cost-effective intervention to
protect the device’s integr ity. These integrated Zener diodes thus avoid the usage of external components.
(5) C
oss eq.
to 80% V
(6) Pulsed: pulse duartion = 300µs, duty cycle 1.5%
Gate-Source Breakdown
Voltage
(BR)DSS,
is defined as a constant equivalent capacitance giving the same charging time as C
DSS
Igs = ± 1mA (Open Drain) 30 V
Tj≤ Tjmax
when VDS increases from 0
oss
A
A
ns
A
ns
A
4/13
Page 5
STF8NK100Z - STP8NK100Z 2 Electrical characteristics
2.1 Electrica l ch aracteristic s (c ur ves)
Figure 1. Safe Operating Area for TO-220 Figure 2. Thermal Impedance for TO-220
Figure 3. Safe Operating Area for TO-220FP Figure 4. Thermal Impedance for TO-220FP
Figure 5. Output Characteristics Figure 6. Transfer Characteristics
5/13
Page 6
2 Electric al characteristic s STF8NK100Z - STP8NK100Z
Figure 7. Transconductance Figure 8. Static Drain-source on Resistance
Figure 9. Gate Charge vs Gate-source Volatge Figure 10. Capacitance Variations
Figure 1 1. Normalized Gate Threshold Volta ge
vs. Temperature
6/13
Figure 12. Normalized On Resistance vs.
Temperature
Page 7
STF8NK100Z - STP8NK100Z 2 Electrical characteristics
Figure 13. Source-drain Diode Forward
Characteristics
Figure 15. Maximum Avalanche Energy vs
Temperature
Figure 14. Normalized BVDSS vs Temperature
7/13
Page 8
3 Test circuits STF8NK100Z - STP8NK100Z
3 Test circuits
Figure 16. Switching Times Test Circuit For
Resistive Load
Figure 18. Test Circuit For Indictive Load
Switching and Diode Recovery
Times
Figure 17. Gate Charge Test Circuit
Figure 20. Unclamped Inductive Load Test
Circuit
Figure 19. Unclamped Inductive Waveform
8/13
Page 9
STF8NK100Z - STP8NK100Z 4 Package mechanical data
4 P ack age mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com
9/13
Page 10
4 Package mechani cal data STF8NK100Z - STP8NK100Z
TO-220FP MECHANICAL DATA
DIM.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
E
A
D
B
L3
L6
L7
F1
F
H
L2
10/13
L5
F2
G1
G
123
L4
Page 11
STF8NK100Z - STP8NK100Z 4 Package mechanical data
TO-220 MECHANICAL DATA
DIM.
A 4.40 4.60 0.173 0.181
b 0.61 0.88 0.024 0.034
b1 1.15 1.70 0.045 0.066
c 0.49 0.70 0.019 0.027
D 15.25 15.75 0.60 0.620
E 10 10.40 0.393 0.409
e 2.40 2.70 0.094 0.106
e1 4.95 5.15 0.194 0.202
F 1.23 1.32 0.048 0.052
H1 6.20 6.60 0.244 0.256
J1 2.40 2.72 0.094 0.107
L 13 14 0.511 0.551
L1 3.50 3.93 0.137 0.154
L20 16.40 0.645
L30 28.90 1.137
øP 3.75 3.85 0.147 0.151
Q 2.65 2.95 0.104 0.116
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
11/13
Page 12
5 Revision Hist ory STF8NK100Z - STP8NK100Z
5 R evi sion History
Date Revision Changes
04-Nov-2005 1 First release
12/13
Page 13
STF8NK100Z - STP8NK100Z 5 Revision History
I
s
o
d
b
ct
t
ot
a
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13/13
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