ST MICROELECTRONICS STP7NK40Z Datasheet

DPAK

1

2

3

TAB

TO-220

1

2

3

TO-220FP

1

3

2

TAB

D(2, TAB)

G(1)

S(3)

AM01475V1

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Datasheet

N-channel 400 V, 0.85 Ω typ., 5.4 A, SuperMESH™ Power MOSFETs

in DPAK, TO-220 and TO-220FP packages

Features

Product status links

STD7NK40ZT4

STP7NK40Z

STP7NK40ZFP

Order code

V

DS

STD7NK40ZT4

STP7NK40Z 70 W

400 V 1 Ω 5.4 A

R

max. I

DS(on)

D

P

TOT

70 W

STP7NK40ZFP 25 W

• Extremely high dv/dt capability

• 100% avalanche tested

• Gate charge minimized

• Very low intrinsic capacitance

• Zener-protected

Applications

• Switching applications

Description

These high-voltage devices are Zener-protected N-channel Power MOSFETs
developed using the SuperMESH™ technology by STMicroelectronics, an
optimization of the well-established PowerMESH™. In addition to a significant
reduction in on-resistance, these devices are designed to ensure a high level of dv/dt
capability for the most demanding applications.

Product summary

STD7NK40ZT4

Marking D7NK40Z

Package DPAK

Packing Tape and reel

STP7NK40Z

Marking P7NK40Z

Package TO-220

Packing Tube

STP7NK40ZFP

Marking P7NK40ZFP

Package TO-220FP

Packing Tube

DS2855 - Rev 3 - July 2018

For further information contact your local STMicroelectronics sales office.

www.st.com

1 Electrical ratings

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter

V

V

DGR

V

DS

GS

Drain-source voltage 400 V

Drain-gate voltage (RGS = 20 kΩ)

Gate-source voltage ±30 V

Drain current (continuous) at TC = 25 °C

I

I

DM

P

TOT

I

AR

E

ESD

dv/dt

D

AS

Drain current (continuous) at TC = 100 °C

(2)

Drain current (pulsed) 21.6 21.6

Total dissipation at TC = 25 °C

Avalanche current, repetitive or non-repetitive

(pulse width is limited by TJ max.)

Single pulse avalanche energy

(starting TJ = 25 °C, ID = IAR, VDD = 50 V)

Gate-source, human body model,

R = 1.5 kΩ, C = 100 pF

(3)

Peak diode recovery voltage slope 4.5 V/ns

Insulation withstand voltage (RMS) from all

V

ISO

three leads to external heat sink

(t = 1 s, TC = 25 °C)

T

J

T

stg

Operating junction temperature range

Storage temperature range

1. This value is limited by maximum junction temperature.

2. Pulse width is limited by safe operating area.

3. ISD ≤ 5.4 A, di/dt ≤ 200 A/µs, VDD < V

(BR)DSS

Value

STD7NK40ZT4 STP7NK40Z STP7NK40ZFP

400 V

5.4 5.4

3.4 3.4

5.4

3.4

21.6

(1)

(1)

(1)

70 70 25 W

5.4 A

130 mJ

3 kV

2.5 kV

-55 to 150 °C

Unit

A

A

A

DS2855 - Rev 3

Table 2. Thermal data

Symbol

R

thj-case

R

thj-amb

R

thj-pcb

1. When mounted on an 1-inch² FR-4, 2 Oz copper board.

Thermal resistance junction-case 1.78 1.78 5 °C/W

Thermal resistance junction-ambient 62.5 °C/W

(1)

Thermal resistance junction-pcb 50 °C/W

Parameter

Value

Unit

DPAK TO-220 TO-220FP

page 2/22

2 Electrical characteristics

(TC = 25 °C unless otherwise specified)

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

1. Defined by design, not subject to production test.

Drain-source breakdown voltage

Zero gate voltage drain current

Gate body leakage current

Gate threshold voltage

Static drain-source on-resistance

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Electrical characteristics

Table 3. On/off states

ID = 1 mA, VGS = 0 V

V

= 0 V, V

GS

V

= 0 V, V

GS

TC = 125 °C

DS

DS

(1)

= 400 V

= 400 V,

VGS = ±20 V, VDS = 0 V

VDS = VGS, ID = 50 µA

VGS = 10 V, ID = 2.7 A

400 V

3 3.75 4.5 V

0.85 1 Ω

1 µA

50 µA

±10 µA

1. C

Table 4. Dynamic

Symbol

C

iss

C

oss

C

rss

C

oss eq.

Q

g

Q

gs

Q

gd

oss eq.

to 80% V

Input capacitance

Output capacitance 82

Reverse transfer capacitance 18

(1)

Equivalent output capacitance

Total gate charge

Gate-source charge 4

Gate-drain charge 10

is defined as the constant equivalent capacitance giving the same charging time as C

.

DSS

Parameter Test conditions Min. Typ. Max. Unit

VDS = 25 V, f = 1 MHz, VGS = 0 V

VGS = 0 V, VDS = 0 to 320 V

VDD = 320 V, ID = 5.4 A,

VGS = 0 to 10 V

(see Figure 16. Test circuit for gate

charge behavior)

Table 5. Switching times

Symbol

t

d(on)

t

r

t

d(off)

t

f

t

r(Voff)

t

f

t

c

Turn-on delay time

Rise time 15

Turn-off delay time 30

Fall time 12

Off-voltage rise time

Fall time 10

Crossover time 20

Parameter Test conditions Min. Typ. Max. Unit

VDD = 200 V, ID = 2.7 A,

RG = 4.7 Ω, V

GS

= 10 V

(see Figure 15. Test circuit for

resistive load switching times and
Figure 20. Switching time
waveform)

VDD = 320 V, ID = 5.4 A,

RG = 4.7 Ω, VGS = 10 V

(see Figure 17. Test circuit for

inductive load switching and diode
recovery times)

535

-

- pF

- 53 - pF

19 26

-

when VDS increases from 0

oss

nC

15

-

-

ns

12

-

-

DS2855 - Rev 3

page 3/22

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Electrical characteristics

Table 6. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

I

SD

(1)

I

SDM

(2)

V

SD

t

rr

Q

rr

I

RRM

1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.

2. Pulse width is limited by safe operating area.

Symbol Parameter Test conditions Min. Typ. Max. Unit

V

(BR)GSO

Source-drain current

5.4

-

Source-drain current (pulsed) 21.6

Forward on voltage

Reverse recovery time

Reverse recovery charge 990 nC

Reverse recovery current 9 A

ISD = 5.4 A, VGS = 0 V

ISD = 5.4 A, di/dt = 100 A/µs,

VDD = 50 V, TJ = 150 °C

(see Figure 17. Test circuit for

inductive load switching and diode

- 1.6 V

220 ns

-

recovery times)

Table 7. Gate-source Zener diode

Gate-source breakdown voltage

IGS = ±1 mA (open drain)

30 - - V

A

The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for
additional external componentry.

DS2855 - Rev 3

page 4/22

2.1 Electrical characteristics (curves)

GC20940

10

-1

10

-2

10

-3

10 -410 -310 -210 -110

0

K

t p (s)

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Electrical characteristics (curves)

Figure 1. Safe operating area for TO-220/DPAK

Figure 3. Safe operating area for TO-220FP

Figure 2. Thermal impedance for TO-220/DPAK

Figure 4. Thermal impedance for TO-220FP

Figure 5. Output characteristics Figure 6. Transfer characteristics

DS2855 - Rev 3

page 5/22

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Electrical characteristics (curves)

Figure 7. Static drain-source on-resistance Figure 8. Gate charge vs gate-source voltage

Figure 9. Capacitance variations

Figure 11. Normalized on-resistance vs temperature

Figure 10. Normalized gate threshold voltage vs

temperature

Figure 12. Source-drain diode forward characteristics

DS2855 - Rev 3

-100

0

page 6/22

STD7NK40ZT4, STP7NK40Z, STP7NK40ZFP

Electrical characteristics (curves)

Figure 13. Normalized V

V

(BR)DSS

(norm.)

-100

(BR)DSS

vs temperature

Figure 14. Maximum avalanche energy vs temperature

DS2855 - Rev 3

page 7/22