The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, spec ial
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Drain-Source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20kΩ)
Gate-Source Voltage± 30V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Current (pulsed)2424 (Note 2)A
Total Dissipation at TC = 25°C
Derating Factor0880.24W/°C
V
ESD(G-S)
dv/dt
Note 3
V
ISO
T
T
stg
G-S ESD (HBM C=100pF, R=1.5kΩ)3500V
Peak Diode Recovery voltage slope4.5V/ns
Insulation Withstand Volatge (DC)- -2500V
Operating Junction Temperature
(6) The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability,
but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In
this respect the Zener voltage is approp riate t o achieve an effi cient and cost-effecti ve interv ention to protect the devi ce’s
integrity. These integrated Zener diodes thus avoid the usage of external components
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
(BR)DSS
is defined as a constant equivalent capacitance giving the same charging time as C
3 Test circuitsSTB6NK60Z - STB6NK60Z-1 - STP6NK60Z - STP6NK60ZFP
3 Test circuits
Figure 15. Switching Times Test Circuit For
Resistive Load
Figure 17. Test Circuit For Inductive Load
Switching and Diode Recovery
Times
Figure 16. Gate Charge Test Circuit
8/16
Page 9
STB6NK60Z - STB6NK60Z-1 - STP6NK60Z - STP6NK60ZFP4 Package mechanical data
4 P ack age mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOP ACK specifications are
available at: www.st.com
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grante
y implic ation or oth erwise under any patent or pat ent rights of STMicroelectron i cs. Specific ations me nt i oned in thi s publication are s ubje
o change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are n
uthoriz ed for use as crit ic al component s i n l i fe support devic es or systems wi thout express written appr oval of STMicroelectron ics.
The ST logo is a registered trademark of ST M i croelectr onics.
All other nam es are the pro perty of their respective owners
Austra l i a - Be l gi um - Brazil - C anada - China - Czech Republic - Finland - F rance - Germany - Hong Kon g - India - Israe l - It al y - Japan -
Malaysi a - M al ta - Morocco - Singapore - Spain - Swede n - Switzerland - United Kingdom - United States of America