ST MICROELECTRONICS STP20N95K5 Datasheet
January 2017
DocID16825 Rev 5
1/22
This is information on a product in full production.
www.st.com
STB20N95K5, STF20N95K5,
STP20N95K5, STW20N95K5
N-channel 950 V, 0.275 Ω typ., 17.5 A MDmesh™ K5
Power MOSFETs in D²PAK, TO-220FP, TO-220 and TO-247
Datasheet - production data
Order code
VDS
R
DS(on)
max.
ID
P
TOT
STB20N95K5
950 V
0.330 Ω
17.5 A
250 W
STF20N95K5
40 W
STP20N95K5
250 W
STW20N95K5
Order code
Marking
Package
Packing
STB20N95K5
20N95K5
D²PAK
Tape and reel
STF20N95K5
TO-220FP
Tube
STP20N95K5
TO-220
STW20N95K5
TO-247
Features
Figure 1: Internal schematic diagram
Industry’s lowest R
Industry’s best FoM (figure of merit)
Ultra-low gate charge
DS(on)
x area
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
These very high voltage N-channel Power
MOSFETs are designed using MDmesh™ K5
technology based on an innovative proprietary
vertical structure. The result is a dramatic
reduction in on-resistance and ultra-low gate
charge for applications requiring superior power
density and high efficiency.
Table 1: Device summary
Contents
STB20N95K5, STF20N95K5, STP20N95K5,
STW20N95K5
2/22
DocID16825 Rev 5
Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package information ..................................................................... 10
4.1 D2PAK package information ............................................................ 10
4.2 TO-220FP package information ...................................................... 13
4.3 TO-220 type A package information ................................................ 15
4.4 TO-247 package information ........................................................... 17
4.5 D2PAK packing information ............................................................. 19
5 Revision history ............................................................................ 21
STB20N95K5, STF20N95K5, STP20N95K5,
STW20N95K5
Electrical ratings
DocID16825 Rev 5
3/22
Symbol
Parameter
Value
Unit
D²PAK
TO-220
TO-247
TO-220FP
VGS
Gate-source voltage
±30
V
ID
Drain current (continuous) at TC = 25 °C
17.5
A
ID
Drain current (continuous) at TC = 100 °C
11
A
I
D
(1)
Drain current (pulsed)
70
A
P
TOT
Total dissipation at TC = 25 °C
250
40
W
ESD
Gate-source human body model (R= 1,5 kΩ,
C = 100 pF)
2
kV
V
ISO
Insulation withstand voltage (RMS) from all
three leads to external heat sink (t = 1 s;
TC = 25 °C)
2500
V
dv/dt
(2)
Peak diode recovery voltage slope
6
V/ns
dv/dt
(3)
MOSFET dv/dt ruggedness
50
Tj
Operating junction temperature range
-55 to 150
°C
T
stg
Storage temperature range
Notes:
(1)
Pulse width limited by safe operating area.
(2)
ISD ≤ 17.5 A, di/dt ≤ 100 A/μs; VDS peak ≤ V
(BR)DSS
(3)
VDS ≤ 760 V
Symbol
Parameter
Value
Unit
D²PAK
TO-220
TO-247
TO-220FP
R
thj-case
Thermal resistance junction-case
0.5
3.1
°C/W
R
thj-amb
Thermal resistance junction-ambient
62.5
50
62.5
R
thj-pcb
(1)
Thermal resistance junction-pcb
30
Notes:
(1)
When mounted on 1 inch² FR-4 board, 2 Oz Cu.
Symbol
Parameter
Value
Unit
IAR
Avalanche current, repetitive or not repetitive (pulse width limited by T
jmax.
)
6 A EAS
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V)
200
mJ
1 Electrical ratings
Table 2: Absolute maximum ratings
Table 3: Thermal data
Table 4: Avalanche characteristics
Electrical characteristics
STB20N95K5, STF20N95K5, STP20N95K5,
STW20N95K5
4/22
DocID16825 Rev 5
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source breakdown voltage
VGS = 0 V, ID = 1 mA
950
V
I
DSS
Zero-gate voltage drain current
VGS = 0 V, VDS = 950 V
1
µA
VGS = 0 V, VDS = 950 V
TC = 125 °C
(1)
50
µA
I
GSS
Gate body leakage current
VDS = 0 V, VGS = ±20 V
±10
µA
V
GS(th)
Gate threshold voltage
VDS = VGS, ID = 100 µA
3 4 5 V R
DS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 9 A
0.275
0.330
Ω
Notes:
(1)
Defined by design, not subject to production test.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
C
iss
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 V
-
1550 - pF
C
oss
Output capacitance
-
140 - pF
C
rss
Reverse transfer capacitance
- 1 -
pF
C
o(er)
(1)
Equivalent capacitance energy
related
VGS = 0 V, VDS = 0 to
760 V
-
65 - pF
C
o(tr)
(2)
Equivalent capacitance time
related
178 - pF
Rg
Intrinsic gate resistance
f = 1 MHz , ID = 0 A
-
3.5 - Ω
Qg
Total gate charge
VDD = 760 V,
ID = 17.5 A
VGS= 10 V
(see Figure 20: "Test
circuit for gate charge
behavior")
-
48 - nC
Qgs
Gate-source charge
- 9 -
nC
Qgd
Gate-drain charge
-
32.5 - nC
Notes:
(1)
C
o(er)
is a constant capacitance value that gives the same stored energy as C
oss
while VDS is rising from 0 to
80% V
DSS
.
(2)
C
o(tr)
is a constant capacitance value that gives the same charging time as C
oss
while VDS is rising from 0 to
80% V
DSS
.
2 Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off-state
Table 6: Dynamic
STB20N95K5, STF20N95K5, STP20N95K5,
STW20N95K5
Electrical characteristics
DocID16825 Rev 5
5/22
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on
delay time
VDD= 475 V, ID = 9 A, RG = 4.7 Ω
VGS = 10 V
(see Figure 19: "Test circuit for resistive
load switching times" and Figure 24:
"Switching time waveform")
-
18 - ns
tr
Rise time
- 9 -
ns
t
d(off)
Turn-off
delay time
-
65 - ns
tf
Fall time
-
18 - ns
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source-drain
current
- 17.5
A
I
SDM
(1)
Source-drain
current (pulsed)
- 70
A
V
SD
(2)
Forward on
voltage
ISD = 17.5 A, VGS = 0 V
- 1.5
V
trr
Reverse recovery
time
ISD = 17.5 A, di/dt = 100 A/µs,
VDD = 60 V
(see Figure 21: "Test circuit for
inductive load switching and diode
recovery times")
-
513 ns
Qrr
Reverse recovery
charge
-
12 µC
I
RRM
Reverse recovery
current
-
46
A
trr
Reverse recovery
time
ISD = 17.5 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 21: "Test circuit for
inductive load switching and diode
recovery times")
-
670 ns
Qrr
Reverse recovery
charge
-
15 µC
I
RRM
Reverse recovery
current
-
44 A
Notes:
(1)
Pulse width limited by safe operating area
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
(BR) GSO
Gate-source breakdown voltage
IGS = ± 1 mA, ID = 0 A
30 - -
V
Table 7: Switching times
Table 8: Source-drain diode
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD
performance of the device. The Zener voltage facilitates efficient and cost-effective device
integrity protection, thus eliminating the need for additional external componentry.
Table 9: Gate-source Zener diode
Electrical characteristics
STB20N95K5, STF20N95K5, STP20N95K5,
STW20N95K5
6/22
DocID16825 Rev 5
Figure 2: Safe operating area for D²PAK and TO-220
Figure 3: Thermal impedance for D²PAK and
TO-220
Figure 4: Safe operating area for TO-220FP
Figure 5: Thermal impedance for TO-220FP
Figure 6: Safe operating area for TO-247
Figure 7: Thermal impedance for TO-247
2.1 Electrical characteristics (curves)
STB20N95K5, STF20N95K5, STP20N95K5,
STW20N95K5
Electrical characteristics
DocID16825 Rev 5
7/22
Figure 8: Output characteristics
Figure 9: Transfer characteristics
Figure 10: Gate charge vs gate-source voltage
Figure 11: Static drain-source on-resistance
Figure 12: Capacitance variation
Figure 13: Output capacitance stored energy
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