STMicroelectronics STP16C596 Technical data

STP16C596

16-BIT CONSTANT CURRENT LED SINK DRIVER

16 CONSTANT CURRENT OUTPUT CHANNELS

ADJUSTABLE OUTPUT CURRENT THROUGH EXTERNAL RESISTOR

SERIAL DATA IN/PARALLEL DATA OUT

SERIAL OUT CHANGE STATE ON THE FALLING EDGES OF CLOCK

OUTPUT CURRENT: 15-120 mA

25 MHz CLOCK FREQ.

AVAILABLE IN HIGH THERMAL TSSOP EXPOSED PAD

EFFICIENCY PACKAGE

DESCRIPTION

The STP16C596 is a monolithic, medium-voltage, low current power 16-bit shift register designed for LED panel displays. The STP16C596 contains a 16-bit serial-in, parallel-out shift register that feeds a 16-bitD-type storage register. In the output stage, sixteen regulated current sources are designed to provide 15-120mA constant current to drive the LEDs.

The serial output change state on the falling edges of clock, this special feature will provide an improved performance of the application when the clock signal is skewed because the daisy chain is too long.

Table 1: Order Codes

DIP-24

SO-24

TSSOP24

TSSOP24

 

(exposed pad)

Through an external resistor, users may adjust the STP16C596 output current, controlling in this way the light intensity of LEDs.

The STP16C596 guarantees a 16V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 25 MHz, also satisfies the system demand for high volume data transmission. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor.

Part Number

Package

Comments

 

 

 

STP16C596B1R

DIP-24

15 parts per tube

 

 

 

STP16C596M

SO-24 (Tube)

40 parts per tube

 

 

 

STP16C596MTR

SO-24 (Tape & Reel)

1000 parts per reel

 

 

 

STP16C596TTR

TSSOP24 (Tape & Reel)

2500 parts per reel

 

 

 

STP16C596XTTR

TSSOP24 Exposed-Pad (Tape & Reel)

2500 parts per reel

 

 

 

July 2005

Rev. 8

1/18

 

 

STP16C596

Table 2: Current Accuracy

Output Voltage

 

Current accuracy

Output Current

 

 

 

Between bits

 

Between ICs

 

 

 

 

 

 

 

 

0.7V

TYP. ± 3%

 

± 10%

15 to 120 mA

 

 

 

 

 

Figure 1: Pin Connection (Note 1)

Note 1: The exposed Pad is electrically not connected.

Table 3: Pin Description

PIN N°

Symbol

Name and Function

 

 

 

1

GND

Ground Terminal

 

 

 

 

2

 

SDI

Serial data input terminal

 

 

 

3

CLK

Clock input terminal

4

 

/LE

Latch input terminal

 

 

 

5-20

OUT 0-15

Output terminal

 

 

 

 

21

 

/OE

 

Input terminal of output enable (active low)

 

 

 

22

SDO

Serial data out terminal

 

 

 

23

R-EXT

Input terminal of an external resistor for constant current programing

 

 

 

24

VDD

Supply voltage terminal

2/18

 

 

 

STP16C596

Table 4: Absolute Maximum Ratings

 

 

 

 

 

 

 

 

Symbol

Parameter

Value

 

Unit

 

 

 

 

 

VDD

Supply Voltage

0 to 7

 

V

VO

Output Voltage

-0.5 to 16

 

V

IO

Output Current

120

 

mA

VI

Input Voltage

-0.4 to VDD+0.4

 

V

IGND

GND Terminal Current

1920

 

mA

fCLK

Clock Frequency

25

 

MHz

TOPR

Operating Temperature Range

-40 to +125

 

°C

TSTG

Storage Temperature Range

-65 to +150

 

°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Under these conditions, functional operation is not implied.

Table 5: Thermal Data

Symbol

Parameter

DIP-24

SO-24

TSSOP24

TSSOP24 (*)

Unit

(exposed pad)

 

 

 

 

 

 

 

 

 

 

 

 

 

Rthj-amb

Thermal Resistance Junction-ambient

60

75

85

37.5

°C/W

(*) The exposed pad should be soldered directly to the PCB to realize the thermal benefits.

Table 6: Recommended Operating Conditions

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

VDD

Supply Voltage

 

4.5

5.0

5.5

V

VO

Output Voltage

 

 

 

16.0

V

IO

Output Current

OUTn

5

 

120

mA

IOH

Output Current

SERIAL-OUT

 

 

+1

mA

IOL

Output Current

SERIAL-OUT

 

 

-1

mA

VIH

Input Voltage

 

0.7VDD

 

VDD+0.3

V

VIL

Input Voltage

 

-0.3

 

0.3VDD

V

twLAT

/LE Pulse Width

VDD = 4.5 to 5.5V

20

 

 

ns

twCLK

CLK Pulse Width

 

20

 

 

ns

twEN

/OE Pulse Width

 

400

 

 

ns

tSETUP(D)

Setup Time for DATA

 

20

 

 

ns

tHOLD(D)

Hold Time for DATA

 

15

 

 

ns

tSETUP(L)

Setup Time for LATCH

 

15

 

 

ns

fCLK

Clock Frequency

Cascade Operation

 

 

25

MHz

3/18

STP16C596

Table 7: Electrical Characteristics (VDD=5V, T = 25°C, unless otherwise specified.)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

VIH

Input Voltage High Level

 

 

0.7VDD

 

VDD

V

VIL

Input Voltage Low Level

 

 

GND

 

0.3VDD

V

IOH

Output Leakage Current

VOH = 16 V

 

 

10

µA

VOL

Output Voltage (Serial-OUT)

IOL = 1mA

 

 

0.4

V

VOH

Output Voltage (Serial-OUT)

IOH = -1mA

VDD-0.4V

 

 

V

IOL1

Output Current

VO = 0.7V

REXT = 910 Ω

18.6

20.4

22.4

mA

IOL2

 

VO = 0.7V

REXT = 360 Ω

45.7

50.2

55.2

mA

∆IOL1

Output Current Error

VO = 0.7V

REXT = 910 Ω

 

± 3

± 4

%

 

between bit (All Output ON)

 

 

 

 

 

 

∆IOL2

VO = 0.7V

REXT = 360 Ω

 

± 3

± 4

%

 

 

RSIN(up)

Pull-up Resistor

 

 

150

300

600

KΩ

RSIN(down)

Pull-down Resistor

 

 

100

200

400

KΩ

IDD(OFF1)

Supply Current (OFF)

REXT = OPEN OUT 0 to 15 = OFF

 

0.3

0.6

mA

IDD(OFF2)

 

REXT = 470 Ω OUT 0 to 15 = OFF

 

5.5

7.7

 

IDD(OFF3)

 

REXT = 250 Ω OUT 0 to 15 = OFF

 

10.1

14.1

 

IDD(ON1)

Supply Current (ON)

REXT = 470 Ω OUT 0 to 15 = ON

 

5.5

7.7

 

IDD(ON2)

 

REXT = 250 Ω OUT 0 to 15 = ON

 

10.1

14.1

 

Table 8: Switching Characteristics (VDD=5V, T = 25°C, unless otherwise specified.)

Symbol

 

 

 

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

tPLH1

Propagation Delay Time,

VDD = 5 V

VIH = VDD

 

200

280

ns

 

CLK-OUTn, /LE = H, /OE = L

VIL = GND

CL = 13pF

 

 

 

 

tPLH2

 

Propagation Delay Time,

 

160

250

ns

 

IO = 40mA

VL = 3 V

 

 

 

 

 

 

/LE-OUTn, /OE = L

 

 

 

 

 

 

 

 

 

REXT = 470 Ω

RL = 65 Ω

 

 

 

 

tPLH3

 

Prop

agation Delay Time,

 

145

200

ns

 

/OE-OUTn, /LE = H

 

 

 

 

 

 

tPLH

Propagation Delay Time,

 

 

 

15

30

ns

 

CLK-SDO

 

 

 

 

 

 

tPHL1

Propagation Delay Time,

 

 

 

15

30

ns

 

CLK-OUTn, /LE = H, /OE = L

 

 

 

 

 

 

tPHL2

 

Propagation Delay Time,

 

 

 

15

30

ns

 

 

 

 

 

 

/LE-OUTn, /OE = L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPHL3

 

Prop

agation Delay Time,

 

 

 

45

60

ns

 

/OE-OUTn, /LE = H

 

 

 

 

 

 

tPHL

Propagation Delay Time,

 

 

 

15

300

ns

 

CLK-SDO

 

 

 

 

 

 

tr

Output Rise Time

 

 

 

160

200

ns

tf

Output Fall Time

 

 

 

15

25

ns

4/18

STMicroelectronics STP16C596 Technical data

STP16C596

EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS

Figure 2: /OE Terminal

Figure 3: /LE Terminal

Figure 4: CLK, SDI Terminal

5/18

STP16C596

Figure 5: SDO Terminal

Figure 6: Block Diagram

6/18

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