ST MICROELECTRONICS STM8 S105C6T6TR Datasheet

STM8S105xx

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,

Datasheet - production data

integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C

Features

Core

• 16 MHz advanced STM8 core with Harvar d architecture and 3-stage pipeline

• Extended instruction set

Memories

• Medium-density Flash/EEPROM :

− Program memory up to 32 Kbytes; data

retention 20 years at 55°C after 10 kcycles

− Data memory up to 1 Kbytes true data

EEPROM; endurance 300 kcycles

• RAM: Up to 2 Kbytes

Timers

• 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM)

• Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary output s , dead-time insertion and flexible synchronization

• 8-bit basic timer with 8-bit prescaler

• Auto wake-up timer

• Window and independent watchdog t i mers

Communications interfaces

• UART with clock output for synchronous operation, Smartcard, IrDA, L IN

• SPI interface up to 8 Mbit/s

• I2C interface up to 400 Kbit/s

Analog-to-digital converter (ADC)

• 10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog

I/Os

• Up to 38 I/Os on a 48-pin package including 16 high sink outputs

• Highly robust I/O design, immune against current injection

Clock, reset and supply management

• 2.95 V to 5.5 V operating voltage

• Flexible clock control, 4 master clock sources:

− Low power crystal resonator oscill ator

− External clock input

− Internal, user-trimmable 16 MHz RC

− Internal low power 128 kHz RC

• Clock security system with clock monitor

• Power management:

− Low power modes (wait, active-halt, halt)

− Switch-off peripheral clocks individually

• Permanently active, low consumption power-on

and power-down reset

Development support

• Embedded single wire interface module (SWIM) for fast on-chip programming and non-intrusive debugging

Unique ID

• 96-bit unique key for each device

Table 1: Device summary

Interrupt management

• Nested interrupt controller with 32 interrupts

• Up to 37 external interrupts on 6 vectors

Reference

STM8S105xx

STM8S105K4, STM8S105K6, STM8S105S4,

Part number

STM8S105S6, STM8S105C4, STM8S105C6

February 2014 DocID14771 Rev 13 1/99 This is information on a product in full production

www.st.com

Contents

STM8S105xx

Contents

1 Introduction ....................................................................................... 8

2 Description ........................................................................................ 9

3 Block diagram ................................................................................. 10

4 Product overview ............................................................................ 11

4.1 Single wire interf ac e module (SWIM) and debug module (DM) ....... 11

4.2 Interrupt controller ........................................................................... 12

4.3 Flash program and data EEPROM memory .................................... 12

4.4 Clock controller ............................................................................... 13

4.5 Power management ........................................................................ 14

4.6 Watchdog timers ............................................................................. 14

4.7 Auto wakeup counter ...................................................................... 15

4.8 Beeper ............................................................................................ 15

4.9 TIM1 - 16-bit advanced control timer ............................................... 15

4.10 TIM2, TIM3 - 16-bit general purpose timers .................................... 15

4.11 TIM4 - 8-bit basic timer ................................................................... 16

4.12 Analog-to-digital converter (ADC1) ................................................. 16

4.13 Communication interfaces ............................................................... 17

4.13.1 UART2 .............................................................................................. 17

4.13.2 SPI .................................................................................................... 17

4.13.3 I²C ..................................................................................................... 18

5 Pinout and pin description ............................................................ 19

5.1 STM8S105 pinouts and pin description ........................................... 19

5.1.1 Alternate function remapping ........................................................... 24

6 Memory and register map .............................................................. 25

6.1 Memory map ................................................................................... 25

6.2 Register map ................................................................................... 26

6.2.1 I/O port hardware register map ........................................................ 26

6.2.2 General hardware register map ........................................................ 27

6.2.3 CPU/SWIM/debug module/interrupt controlle r registers .................. 34

7 Interrupt vector mapping ............................................................... 36

8 Option bytes .................................................................................... 37

9 Unique ID ......................................................................................... 41

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Contents

10 Electrical characteristics ............................................................... 42

10.1 Parameter conditions ...................................................................... 42

10.1.1 Minimum and maximum values ........................................................ 42

10.1.2 Typical values ................................................................................... 42

10.1.3 Typical curves ................................................................................... 42

10.1.4 Typical current consumption ............................................................ 42

10.1.5 Loading capacitor ............................................................................. 43

10.1.6 Pin input voltage ............................................................................... 43

10.2 Absolute maximum ratings .............................................................. 43

10.3 Operating conditions ....................................................................... 45

10.3.1 VCAP external capacitor .................................................................. 46

10.3.2 Supply current characteristics .......................................................... 47

10.3.3 External clock sources and timing characteristics ............................ 56

10.3.4 Internal clock sources and timing characteristics ............................. 58

10.3.5 Memory characteristics ..................................................................... 60

10.3.6 I/O port pin characteristics ................................................................ 61

10.3.7 Typical output level curves ............................................................... 64

10.3.8 Reset pin characteristics .................................................................. 68

10.3.9 SPI serial peripheral interface .......................................................... 70

10.3.10 I2C interface characteristics ............................................................. 73

10.3.11 10-bit ADC characteristics ................................................................ 74

10.3.12 EMC characteristics .......................................................................... 77

11 Package information ...................................................................... 80

11.1 48-pin LQFP package mechanical data .......................................... 80

11.2 44-pin LQFP package mechanical data .......................................... 81

11.3 32-pin LQFP package mechanical data .......................................... 82

11.4 32-lead UFQFPN package mechanical data ................................... 84

11.5 SDIP32 package mechanical data .................................................. 85

12 Thermal characteristics ................................................................. 87

12.1 Reference document ....................................................................... 87

12.2 Selecting the product temperature range ........................................ 87

13 Ordering information ...................................................................... 89

14 STM8S105 FASTROM microcontro ller option list ....................... 90

15 STM8 development tools ............................................................... 94

15.1 Emulation and in-circuit debugging tools ......................................... 94

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Contents

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15.2 Software tools ................................................................................. 94

15.2.1 STM8 toolset .................................................................................... 94

15.2.2 C and assembly toolchains .............................................................. 95

15.3 Programming tools .......................................................................... 95

16 Revision history .............................................................................. 96

17 Disclaimer ....................................................................................... 99

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STM8S105xx

List of tables

Table 1: Device summary ........................................................................................................................... 1

Table 2: STM8S105xx access line features ............................................................................................... 9

Table 3: Peripheral clock gating bit assignments in C LK_PCKENR1/2 registers .................................... 14

Table 4: TIM timer features ....................................................................................................................... 16

Table 5: Legend/abbreviations for pinout t ables ....................................................................................... 19

Table 6: Pin description for STM8S105 microcontrollers ......................................................................... 22

Table 7: Flash, Data EEPROM and RAM boundary addresses ............................................................... 26

Table 8: I/O port hardware register map ................................................................................................... 26

Table 9: General hardware register map .................................................................................................. 27

Table 10: CPU/SWIM/debug module/interrupt cont roller registers .......................................................... 34

Table 11: Interrupt mapping ...................................................................................................................... 36

Table 12: Option bytes .............................................................................................................................. 37

Table 13: Option byte description ............................................................................................................. 38

Table 14: Description of alternate function remapping bits [7:0] of OPT2 ................................................ 39

Table 15: Unique ID registers (96 bits) ..................................................................................................... 41

Table 16: Voltage characteristics .............................................................................................................. 43

Table 17: Current characteristics .............................................................................................................. 44

Table 18: Thermal characteristics ............................................................................................................. 45

Table 19: General operating conditions .................................................................................................... 45

Table 20: Operating conditions at power-up/power-down ........................................................................ 46

Table 21: Total current consumption with code execut ion in run mode at VDD = 5 V ............................. 47

Table 22: Total current consumption with code execut ion in run mode at VDD = 3.3 V .......................... 48

Table 23: Total current consumption in wait mode at VDD = 5 V ............................................................. 49

Table 24: Total current consumption in wait mode at V DD = 3.3 V .......................................................... 49

Table 25: Total current consumption in active halt m ode at VDD = 5 V ................................................... 50

Table 26: Total current consumption in active halt mode at VDD = 3.3 V ................................................ 51

Table 27: Total current consumption in halt mode at V DD = 5 V ............................................................. 51

Table 28: Total current consumption in halt mode at V DD = 3.3 V .......................................................... 52

Table 29: Wakeup times ........................................................................................................................... 52

Table 30: Total current consumption and timing in f orc ed reset state ...................................................... 53

Table 31: Peripheral current consumption ................................................................................................ 53

Table 32: HSE user external clock characteristic s ................................................................................... 56

Table 33: HSE oscillator characteristics ................................................................................................... 56

Table 34: HSI oscillator characteristics ..................................................................................................... 58

Table 35: LSI oscillator characteristics ..................................................................................................... 59

Table 36: RAM and hardware registers .................................................................................................... 60

Table 37: Flash program memory/data EEPROM memory ...................................................................... 60

Table 38: I/O static characteristics ............................................................................................................ 61

Table 39: Output driving current (standard ports) ..................................................................................... 63

Table 40: Output driving current (true open drain ports) .......................................................................... 63

Table 41: Output driving current (high sink ports) .................................................................................... 63

Table 42: NRST pin characteristics .......................................................................................................... 68

Table 43: SPI characteristics .................................................................................................................... 71

Table 44: I2C characteristics .................................................................................................................... 73

Table 45: ADC characteristics .................................................................................................................. 74

Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V ...................................................................... 75

Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V .......................................................... 76

Table 48: EMS data .................................................................................................................................. 78

Table 49: EMI data .................................................................................................................................... 78

Table 50: ESD absolute maximum ratings ............................................................................................... 79

Table 51: Electrical sensitivities ................................................................................................................ 79

Table 52: 48-pin low profile quad flat package mechanical data .............................................................. 80

Table 53: 44-pin low profile quad flat package mechanical data .............................................................. 81

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List of tables

STM8S105xx

Table 54: 32-pin low profile quad flat package mechanical data .............................................................. 82

Table 55: 32-lead ultra thin fine pitch quad flat no-lead pac kage me chani cal dat a ................................. 84

Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data ................................................. 86

Table 57: Thermal characteristics (1) ....................................................................................................... 87

Table 58: Document revision history ........................................................................................................ 96

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STM8S105xx

List of figures

Figure 1: STM8S105xx access line block diagram ................................................................................... 10

Figure 2: Flash memory organization ....................................................................................................... 13

Figure 3: LQFP 48-pin pinout ................................................................................................................... 19

Figure 4: LQFP 44-pin pinout ................................................................................................................... 20

Figure 5: LQFP/UFQFPN 32-pin pinout .................................................................................................... 21

Figure 6: SDIP 32-pin pinout .................................................................................................................... 21

Figure 7: Memory map .............................................................................................................................. 25

Figure 8: Supply current measurement conditions ................................................................................... 42

Figure 9: Pin loading conditions ................................................................................................................ 43

Figure 10: Pin input voltage ...................................................................................................................... 43

Figure 11: fCPUmax versus VDD ............................................................................................................. 46

Figure 12: External capacitor CEXT ......................................................................................................... 47

Figure 13: Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz ...................................... 54

Figure 14: Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD= 5 V .............................................. 54

Figure 15: Typ. IDD(RUN) vs. VDD, HSI RC osc, fCPU = 16 MHz .......................................................... 54

Figure 16: Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz ....................................... 55

Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ............................................... 55

Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ........................................................... 55

Figure 19: HSE external clocksource ....................................................................................................... 56

Figure 20: HSE oscillator circuit diagram.................................................................................................. 57

Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temper at ures ........................................................... 58

Figure 22: Typical HSI accuracy vs VDD @ 4 temperat ures ................................................................... 59

Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures .................................................................... 59

Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures ..................................................................... 62

Figure 25: Typical pull-up resistance vs VDD @ 4 t em peratures ............................................................. 62

Figure 26: Typical pull-up current vs VDD @ 4 temperatures .................................................................. 63

Figure 27: Typ. VOL @ VDD = 5 V (standard ports) ................................................................................ 64

Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports) ............................................................................. 65

Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports) ...................................................................... 65

Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports) ................................................................... 66

Figure 31: Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................ 66

Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports) ............................................................................. 67

Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) ..................................................................... 67

Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports) .................................................................. 67

Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) .................................................................... 68

Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ................................................................. 68

Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures ........................................................... 69

Figure 38: Typical NRST pull-up resistance vs VDD @ 4 t em peratures .................................................. 69

Figure 39: Typical NRST pull-up current vs VDD @ 4 tem peratures ....................................................... 70

Figure 40: Recommended reset pin protection ........................................................................................ 70

Figure 41: SPI timing diagram - slave mode and CPH A = 0 .................................................................... 72

Figure 42: SPI timing diagram - slave mode and CPH A = 1(1) ................................................................ 72

Figure 43: SPI timing diagram - master mode(1) ..................................................................................... 73

Figure 44: Typical application with I2C bus and timing diagram (1) ......................................................... 74

Figure 45: ADC accuracy characteristics .................................................................................................. 76

Figure 46: Typical application with ADC ................................................................................................... 77

Figure 47: 48-pin low profile quad flat package (7 x 7) ............................................................................. 80

Figure 48: 44-pin low profile quad flat package ........................................................................................ 81

Figure 49: 32-pin low profile quad flat package (7 x 7) ............................................................................. 82

Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) .............................................. 84

Figure 51: 32-lead shrink plastic DIP (400 ml) package ........................................................................... 85

Figure 52: STM8S105xx access line ordering information scheme ......................................................... 89

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Introduction

STM8S105xx

1 Introduction

This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.

• For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcont roller family reference manual (RM0016).

• For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manu al (P M 0051).

• For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug mo dul e user manual (UM0470).

• For information on the STM8 core, please refer to the S T M 8 CP U programming manual (PM0044).

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STM8S105xx

Description

2 Description

The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash program memory, plus integrated true data EE PROM. They are referred to as mediumdensity devices in the STM8S microcontroller family reference manual (RM0016).

All devices of the STM8S105xx access line provide t he f ol l owing benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300k write/erase cycles and a high system integration level with internal clock oscillators, watchdog, and brown-out reset.

Device performance is ensured by a 16 MHz CPU clock frequency and enhanced characteristics which include robust I/O, indepe ndent watchdogs (with a separate clock source), and a clock security system.

Short development cycles are guaranteed due to ap plication scalability across common family product architecture with compatible pinout , memory map and modular peripherals. Full documentation is offered with a wide choi ce of development tools.

Product longevity is ensured in the STM8S family t hanks to their advanced core which is made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.

Table 2: STM8S105xx access line features

Device

Pin count Maximum

number of GPIOs Ext. Interrupt pins

Timer CAPCOM

channels

complementary

A/D Converter

channels

High sink I/Os

Medium density

Flash Program

memory (bytes) Data EEPROM

RAM (bytes)

Peripheral set

Timer

outputs

(bytes)

STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4

48 38

35

9

3

10

16

32K

1024

2K

Advanced control t i me r (TI M1 ) , G en eral-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C,

48 38

35

9

3

10

16

16K

1024

2K

UART, Window WDG, Independent WDG, ADC

44 34

31

8

3

9

15

32K

1024

2K

44 34

31

8

3

9

15

16K

1024

2K

32 25

23

8

3

7

12

32K

1024

2K

32 25

23

8

3

7

12

16K

1024

2K

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Block diagram

STM8S105xx

3 Block diagram

Figure 1: STM8S105xx access line block diagram

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STM8S105xx

Product overview

4 Product overview

The following section intends to give an overview of the basic features of the device functional modules and peripherals.

For more detailed information please refer to t he corresponding family reference manual (RM0016).

Central processing unit STM8 The 8-bit STM8 core is designed for code efficien cy and performance. It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

• Harvard architecture

• 3-stage pipeline

• 32-bit wide program memory bus - single cycle fetching for most instructions

• X and Y 16-bit index registers - enabling indexed addres sing m odes with or without

offset and read-modify-write type data manipulations

• 8-bit accumulator

• 24-bit program counter - 16-Mbyte linear memory space

• 16-bit stack pointer - access to a 64 K-level stack

• 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

• 20 addressing modes

• Indexed indirect addressing mode for look-up table s located anywhere in the address

space

• Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

• 80 instructions with 2-byte average instruction siz e

• Standard data movement and logic/arithmetic functions

• 8-bit by 8-bit multiplication

• 16-bit by 8-bit and 16-bit by 16-bit division

• Bit manipulation

• Data transfer between stack and accumulator (push/pop) with direct stack access

• Data transfer using the X and Y registers or direct memory-to-memory transfers

4.1 Single wire interface module (SWIM) a nd debug module (DM)

The single wire interface module and debug module permi ts non-intrusive, real-time incircuit debugging and fast memory programming.

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms.

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Product overview

STM8S105xx

Debug module

The non-intrusive debugging module features a pe rf ormance close to a full-featured emulator. Beside memory and peripherals, also CPU operat i on can be monitored in realtime by means of shadow registers.

• R/W to RAM and peripheral registers in real-time

• R/W access to all resources by stalling the CPU

• Breakpoints on all program-memory instructions (software breakpoi nts)

• Two advanced breakpoints, 23 predefined configurati ons

4.2 Interrupt controller

• Nested interrupts with three software priority l evels

• 32 interrupt vectors with hardware priority

• Up to 37 external interrupts on 6 vectors including TLI

• Trap and reset interrupts

4.3 Flash program and data EEPROM memory

• Up to 32 Kbytes of Flash program single voltage Flash m em ory

• Up to 1 Kbytes true data EEPROM

• Read while write: Writing in data memory possible whil e executing code in program

memory

• User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid

unintentional overwriting of memory that could re sult from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access

security system). MASS is always enabled and prot ects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IA P), this write protection can be removed by writing a MASS key sequence in a control register. T his all ows the application to write to data EEPROM, modify the contents of main progr am memory or the device option bytes.

A second level of write protection, can be enabl ed to further protect a specific area of memory known as UBC (user boot code). Refer to t he figure below.

The size of the UBC is programmable through the UBC option byte, in increments of 1 page (512 bytes) by programming the UBC option byte in I CP mode.

This divides the program memory into two areas:

• Main program memory: Up to 32 Kbytes minus UBC

• User-specific boot code (UBC): Configurable up to 32 Kbytes

The UBC area remains write-protected during in-appl i cat i on programming. This means that the MASS keys do not unlock the UBC area. It protects the m emory used to store the boot program, specific code libraries, reset and int errupt vectors, the reset routine and usually the IAP and communication routines.

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STM8S105xx

Product overview

Figure 2: Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing t he Flash program memory and data EEPROM memory in ICP mode (and debug mode). Onc e the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

4.4 Clock controller

The clock controller distributes the system clock (f to the core and the peripherals. It also manages clo ck gating for low power modes and ensures clock robustness.

Features

• Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock sig nal is not switched until the new clock source is ready. The design guarantees glitch-f ree switching.

• Clock management: To reduce power consumption, t he cloc k controller can stop the

clock to the core, individual peripherals or memory .

• Master clock sources: Four different clock sour ces can be used to drive the master

clock:

− 1-16 MHz high-speed external crystal (HSE)

− Up to 16 MHz high-speed user-external clock (HSE user-ext)

− 16 MHz high-speed internal RC oscillator (HSI)

− 128 kHz low-speed internal RC (LSI)

) coming from different oscillators

MASTER

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Product overview

STM8S105xx

• Startup clock: After reset, the microcontroller restarts by default with an internal 2

MHz clock (HSI/8). The prescaler ratio and clock so urce can be changed by the application program as soon as the code execution st art s.

• Clock security system (CSS): This feature can be e nabled by software. If an HSE

clock failure occurs, the internal RC (16 MHz/8) is a ut om atically selected by the CSS and an interrupt can optionally be generated.

• Configurable main clock output (CCO): This outputs an external clock for use by

the application.

Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit Peripheral

PCKEN17 PCKEN16 PCKEN15 PCKEN14

clock

TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU TIM2 PCKEN11 TIM4 PCKEN10

Bit Peripheral

clock

4.5 Power management

For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.

• Wait mode: In this mode, the CPU is stopped, but peripheral s are kept running. The

wakeup is performed by an internal or external interrupt or reset.

• Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

stopped. An internal wakeup is generated at program mabl e i ntervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AW U interrupt, external interrupt or reset.

• Active halt mode with regulator off: This mode is the same as active halt with

regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

• Halt mode :In this mode the microcontroller uses the least power. The CPU and

peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

Bit Peripheral

clock

SPI PCKEN25 Reserved PCKEN21 Reserved

I2C PCKEN24 Reserved PCKEN20 Reserved

Bit Peripheral

clock

4.6 Watchdog timers

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The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdo g behavior to match the application perfectly.

STM8S105xx

Product overview

The application software must refresh the counter b efore time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up

to 64 ms.

2. Refresh out of window: The downcounter is refreshed bef ore i t s value is lower than

the one stored in the window register.

Independent watchdog timer

The independent watchdog peripheral can be us ed to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, an d thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

4.7 Auto wakeup counter

• Used for auto wakeup from active halt mode

• Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

• LSI clock can be internally connected to TIM3 input capture channel 1 for calibration

4.8 Beeper

The beeper function outputs a signal on the BEE P pin for so und generation. The signal is in the range of 1, 2 or 4 kHz.

The beeper output port is only available through the alternate function remap option bit AFR7.

4.9 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of cont rol applications. With its complementary outputs, dead-time control and c enter-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver

• 16-bit up, down and up/down autoreload counter with 16-bit prescaler

• Four independent capture/compare channels (CAPCOM) configurable as input

capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output

• Synchronization module to control the timer with external signals

• Break input to force the timer outputs into a defined state

• Three complementary outputs with adjustable dead ti m e

• Encoder mode

• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.10 TIM2, TIM3 - 16-bit general purpose timers

• 16-bit autoreload (AR) up-counter

• 15-bit prescaler adjustable to fixed power of 2 ratios 1… 32768

• Timers with 3 or 2 individually configurable capture/compare channels

• PWM mode

• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

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Product overview

STM8S105xx

Additional AIN12 analog input is not selectable in A DC scan mode or with analog

4.11 TIM4 - 8-bit basic timer

• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

• Clock source: CPU clock

• Interrupt source: 1 x overflow/update

Table 4: TIM timer features

Timer Counter

size

(bits)

TIM1 16 Any

TIM2 16 Any

TIM3 16 Any

TIM4 8 Any

Prescaler Counting

mode

Up/Down 4 3 Yes No

integer

from 1 to

65536

Up 3 0 No

power of 2

from 1 to

32768

Up 2 0 No

power of 2

from 1 to

32768

Up 0 0 No

power of 2

from 1 to

128

CAPCOM channels

4.12 Analog-to-digital converter (ADC1)

The STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1) with up to 10 multiplexed input channels and the following main features:

Complem.

outputs

Ext.

trigger

Timer

synchronization/

chaining

• Input voltage range: 0 to V

DD DDA

• Conversion time: 14 clock cycles

• Single and continuous and buffered continuous conver sion m odes

• Buffer size (n x 10 bits) where n = number of input channels

• Scan mode for single and continuous conversion of a sequence of channels

• Analog watchdog capability with programmable uppe r and l ower thresholds

• Analog watchdog interrupt

• External trigger input

• Trigger from TIM1 TRGO

• End of conversion (EOC) interrupt

watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.

16/99 DocID14771 Rev 13

STM8S105xx

Product overview

4.13 Communication interfaces

The following communication interfaces are implem ented:

• UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,

IrDA mode, LIN2.1 master/slave capability

• SPI : Full and half-duplex, 8 Mbit/s

• I²C: Up to 400 Kbit/s

4.13.1 UART2

Main features

• One Mbit/s full duplex SCI

• SPI emulation

• High precision baud rate generator

• Smartcard emulation

• IrDA SIR encoder decoder

• LIN master mode

• LIN slave mode

Asynchronous communication (UART mode)

• Full duplex communication - NRZ standard format (mark/space)

• Programmable transmit and receive baud rates up to 1 M bi t/s (f

following any standard baud rate regardless of t he i nput frequency

• Separate enable bits for transmitter and receiver

• Two receiver wakeup modes:

− Address bit (MSB)

− Idle line (interrupt)

• Transmission error detection with interrupt generation

• Parity control

/16) and capable of

CPU

Synchronous communication

• Full duplex synchronous transfers

• SPI master operation

• 8-bit data communication

• Maximum speed: 1 Mbit/s at 16 MHz (f

LIN master mode

• Emission: Generates 13-bit synch break frame

• Reception: Detects 11-bit break frame

LIN slave mode

• Autonomous header handling - one single interrupt per valid message header

• Automatic baud rate synchronization - maximum toler ated initial clock deviation ±15 %

• Synch delimiter checking

• 11-bit LIN synch break detection - break detection always active

• Parity check on the LIN identifier field

• LIN error management

• Hot plugging support

4.13.2 SPI

• Maximum speed: 8 Mbit/s (f

• Full duplex synchronous transfers

/16)

CPU

/2) both for master and slave

MASTER

DocID14771 Rev 13 17/99

Product overview

STM8S105xx

• Simplex synchronous transfers on two lines with a possibl e bi directional data line

• Master or slave operation - selectable by hardware or software

• CRC calculation

• 1 byte Tx and Rx buffer

• Slave/master selection input pin

4.13.3 I²C

• I²C master features:

• I²C slave features:

• Generation and detection of 7-bit/10-bit addressing and general call

• Supports different communication speeds:

− Clock generation

− Start and stop generation

− Programmable I2C address detection

− Stop bit detection

− Standard speed (up to 100 kHz)

− Fast speed (up to 400 kHz)

18/99 DocID14771 Rev 13

STM8S105xx

Pinout and pin description

5 Pinout and pin description

Table 5: Legend/abbreviations for pinout tables

Type I= Input, O = Output, S = Power supply

Level

Output speed

Port and control

configuration

Reset state Bold X (pin state after internal res et release).

5.1 STM8S105 pinouts and pin descripti on

Input CM = CMOS

Output HS = High sink

O1 = Slow (up to 2 MHz)

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmabilit y with slow as default state after reset

O4 = Fast/slow programmabilit y with fast as default state after reset

Input float = floating, wpu = weak pull-up

Output T = True open drain, OD = Open drain, PP = Push pull

Unless otherwise specified, the pin state is the same during the reset

phase and after the internal reset r elease.

Figure 3: LQFP 48-pin pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to V

not implemented).

DD

3. [ ] alternate function remapping option (If the same al ternate function is shown twice, it

indicates an exclusive choice not a duplication of t he function).

DocID14771 Rev 13 19/99

Pinout and pin description

STM8S105xx

Figure 4: LQFP 44-pin pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to V

not implemented).

DD

3. [ ] alternate function remapping option (If the same al ternate function is shown twice, it

indicates an exclusive choice not a duplication of t he function).

20/99 DocID14771 Rev 13

STM8S105xx

Pinout and pin description

Figure 5: LQFP/UFQFPN 32-pin pinout

1. (HS) high sink capability.

2. [ ] alternate function remapping option (If the same al ternate function is shown twice, it

indicates an exclusive choice not a duplication of t he function).

Figure 6: SDIP 32-pin pinout

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to V

not implemented).

DD

3. [ ] alternate function remapping option (If the same al ternate function is shown twice, it

indicates an exclusive choice not a duplication of t he function).

DocID14771 Rev 13 21/99

Pinout and pin description

STM8S105xx

LQFP32/

UFQFPN32

PP

Table 6: Pin description for STM8S105 microcontrollers

Pin number

LQFP48 LQFP44

1 1 1 6 2 2 2 7 PA1/ OSC IN I/O

3 3 3 8 PA2/ OSC OUT I/O 4 4 - 5 5 4 9 6 6 5 10 7 7 6 11 8 8 7 12 9 - - - PA3/ TIM2 _CH3

10 9 - 11 10 - 12 11 - -

- - 8 13 PF4/ AIN1 2 13 12 9 14 14 13 10 15 15 14 - - PB7/ AIN7 I/O 16 15 - - PB6/ AIN6 I/O 17 16 11 16 PB5/ AIN5

18 17 12 17 PB4/ AIN4

19 18 13 18 PB3/ AIN3

20 19 14 19 PB2/ AIN2

21 20 15 20 PB1/ AIN1

22 21 16 21 PB0/ AIN0

23 - - - PE7/ AIN8 I/O 24 22 - - PE6/ AIN9 I/O 25 23 17 22 PE5/SPI_NSS I/O 26 24 18 23 PC1/ TIM1_CH1

SDIP32

Pin name

NRST

V

SSIO_1

VSS

VCAP

VDD

V

DDIO_1

[TIM3 _CH1]

PA4 PA5 PA6

(1)

V

DDA

V

SSA

2

[I

C_ SDA]

2

[I

C_ SCL]

[TIM1_ ETR]

[TIM1_CH3N]

[TIM1_CH2N]

[TIM1_CH1N]

UART2_CK

I/O

I/O I/O I/O I/O

I/O

Type

S S S S S

S S

Input

floating

X

X X X X

X X X

X

X X X X

wpu

Ext. interrupt

X

X X

X X HS O3 X X X X HS O3 X X X X HS O3 X X X

X X X X X X

X X

X X X X X X X X HS O3 X X

Output

High sink

O1 X X

O1 X X O1 X X O1 X X

O1 X X

O1 X X O1 X X O1 X X

Speed

OD

Main

function

(after

reset)

Port A1

Port A2

I/O ground

Digital ground

1.8 V regulator capacitor Digital power supply

I/O power supply

Port A3

Port A4 Port A5 Port A6

Port F4

Analog power supply

Analog ground

Port B7 Port B6 Port B5

Port B4

Port B3

Port B2

Port B1

Port B0

Port E7 Port E6 Port E5

SPI master/slave select

Port C1

Alternate function

Default alternate

function

Reset

Resonator crystal in

Resonator crystal out

Timer 2 - channel 3 TIM3_CH1 [AFR1]

clock

(2)

(3)

Analog input 12

Analog input 7 Analog input 6 Analog input 5

Analog input 4

Analog input 3

Analog input 2

Analog input 1

Analog input 0

Analog input 8

Analog input 9

Timer 1 – channel 1/ UART2 synchronous

after remap [option bit]

I2C_SDA [AFR6]

I2C_SCL [AFR6]

TIM1_ETR [AFR5]

TIM1_CH3N [AFR5]

TIM1_ CH2N [AFR5]

TIM1_CH1N [AFR5]

22/99 DocID14771 Rev 13

STM8S105xx

Pinout and pin description

LQFP32/

UFQFPN32

PP

Pin number

LQFP48 LQFP44

27 25 19 24 PC2/ TIM1_CH2 I/O 28 26 20 25 PC3/ TIM1_CH3 I/O 29 - 21 26 PC4/ TIM1_CH4 I/O 30 27 22 27 PC5/ SPI_SCK I/O 31 28 - 32 29 - 33 30 23 28 PC6/ SPI_MOSI I/O 34 31 24 29 PC7/ SPI_MISO I/O 35 32 - 36 33 - 37 - - - PE3/ TIM1_BKIN I/O 38 34 - - PE2/ I2C_SDA I/O 39 35 - - PE1/ I2C_ SCL I/O 40 36 - - PE0/ CLK_ CCO I/O

41 37 25 30 PD0/ TIM3_CH2

SDIP32

Pin name

Type

V

S S

SSIO_2

V

DDIO_2

PG0

I/O

PG1

I/O

Input

floating

X X X X

X X X X X X X X

X

wpu

Ext. interrupt

X X HS O3 X X X X HS O3 X X X X HS O3 X X X HS O3 X X

X X HS O3 X X X X HS O3 X X X X X X

X X

X X HS O3 X X

Output

High sink

O1 X X O1 X X O1 X X O1 T O1 T

Speed

OD

(4)

[TIM1_BKIN]

[CLK_CCO]

42 38 26 31 PD1/ SWIM

(5)

43 39 27 32 PD2/ TIM3_CH1

[TIM2_CH3]

44 40 28 1

PD3/

I/O I/O

I/O

X

X X HS O4 X X

X

X X HS O3 X X

X

X X HS O3 X X

TIM2_CH2

[ADC_ETR]

X

45 41 29 2

PD4/

I/O

X X HS O3 X X

TIM2_CH1

[BEEP]

X

46 42 30 3

47 43 31 4

48 44 32 5

PD5/

UART2_TX

PD6/

UART2_RX

PD7/ TLI

I/O

X

X X

O1 X X

[TIM1_CH4]

Notes:

(1)

A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.

(2)

AIN12 is not selectable in ADC scan mode or with analog watchdog.

(3)

In 44-pin package, AIN9 cannot be used by ADC scan mode.

(4)

In the open-drain out put column, ‘T’ defines a true op en -drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented).

(5)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

Main

function

(after reset)

Port C2 Port C3 Port C4 Port C5

Port C6 Port C7 Port G0 Port G1 Port E3 Port E2 Port E1 Port E0

Port D0

Port D1 Port D2

Port D3

Port D4

Port D5

Port D6

Port D7

Alternate function

Default alternate

function

SPI clock

Timer 1- channel 2 Timer 1 - channel 3 Timer 1 - channel 4

I/O ground

I/O power supply

SPI master out/slave in SPI master in/ slave out

Timer 1 - break input

I2C data

I2C clock

Configurable clock

output

Timer 3 - channel 2 TIM1_BKIN [AFR3]/

SWIM data interface

Timer 3 - channel 1 TIM2_CH3 [AFR1]

Timer 2 - channel 2 ADC_ETR [AFR0]

Timer 2 - channel 1 BEEP output [AFR7]

UART2 data transmit

UART2 data receive

Top level interrupt TIM1_CH4 [AFR4]

after remap [option bit]

CLK_CCO [AFR2]

DocID14771 Rev 13 23/99

Pinout and pin description

STM8S105xx

5.1.1 Alternate function remapping

As shown in the rightmost column of the pin descripti on table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. When the remapping option is act i ve, the default alternate function is no longer available.

To use an alternate function, the corresponding peri pheral must be enabled in the peripheral registers.

Alternate function remapping does not aff ect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0 016).

24/99 DocID14771 Rev 13

STM8S105xx

Memory and register map

6 Memory and register map

6.1 Memory map

Figure 7: Memory map

The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case.

DocID14771 Rev 13 25/99

Memory and register map

STM8S105xx

Table 7: Flash, Data EEPROM and RAM boundary addresses

Memory area Size (bytes) Start address End address

Flash program memory 32K 0x00 8000 0x00 FFFF

RAM 2K 0x00 0000 0x00 07FF

Data EEPROM 1024 0x00 4000 0x00 43FF

6.2 Register map

6.2.1 I/O port hardware register map

Table 8: I/O port hardware register map

Address Block Register label Register name Reset status

0x00 5000 Port A PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR P ort A input pin value register 0xXX 0x00 5002 PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 Port B PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR P ort B input pin value register 0xXX 0x00 5007 PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A Port C PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xXX 0x00 500C PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F Port D PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xXX 0x00 5011 PD_DDR Port D data direction re gister 0x00 0x00 5012 PD_CR1 Port D control register 1 0x02 0x00 5013 PD_CR2 Port D control register 2 0x00 0x00 5014 Port E PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR P ort E input pin value register 0xXX 0x00 5016 PE_DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 Port F PF_ODR Port F data output latch register 0x00

16K 0x00 8000 0x00 BFFF

26/99 DocID14771 Rev 13

STM8S105xx

Memory and register map

Address Block Register label Register name Reset status

0x00 501A PF_IDR Port F input pin value register 0xXX 0x00 501B PF_DDR Port F data direction re gister 0x00 0x00 501C PF_CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00 501E Port G PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0xXX 0x00 5020 PG_DDR Port G data direction register 0x00 0x00 5021 PG_CR1 Port G control register 1 0x00 0x00 5022 PG_CR2 Port G control register 2 0x00 0x00 5023 Port H PH_ODR Port H data output latch regis ter 0x00 0x00 5024 PH_IDR Port H input pin value register 0xXX 0x00 5025 PH_DDR Port H data direction re gister 0x00 0x00 5026 PH_CR1 Port H control register 1 0x00 0x00 5027 PH_CR2 Port H control register 2 0x00 0x00 5028 Port I PI_ODR Port I data output latch register 0x00 0x00 5029 PI_IDR Port I input pin value register 0xXX 0x00 502A PI_DDR Port I data direction register 0x00 0x00 502B PI_CR1 Port I control register 1 0x00 0x00 502C PI_CR2 Port I control register 2 0x00

6.2.2 General hardware register map

Table 9: General hardware register m ap

Address Block Register label Register name Reset

0x00 5050 to

0x00 5059 0x00 505A Flash FLASH_CR1 Flash control r egister 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control

0x00 505D FLASH _FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Flash complementary protection

0x00 505F FLASH _IAPSR Flash in-application programming

0x00 5060 to

0x00 5061 0x00 5062 Flash FLASH _PUKR Flash program memory

status

Reserved area (10 bytes)

0xFF

register 2

0xFF

register

0x00

status register

Reserved area (2 bytes)

0x00

unprotection register

DocID14771 Rev 13 27/99

Memory and register map

STM8S105xx

(2)

Address Block Register label Register name Reset

0x00 5063 Reserved area (1 byte) 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection

register

0x00 5065 to

Reserved area (59 bytes)

0x00 509F 0x00 50A0 ITC EXTI_CR1 External interru pt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 to

Reserved area (17 bytes)

0x00 50B2 0x00 50B3 RST RST_SR Reset status register 0xXX

0x00 50B4 to

Reserved area (12 bytes)

0x00 50BF 0x00 50C0 CLK CLK_ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area (1 byte) 0x00 50C3 CLK CLK_CMSR Clock master status register 0xE1 0x00 50C4 CLK_SWR Clock master switch register 0xE1 0x00 50C5 CLK_SWCR Clock switch control register 0xXX 0x00 50C6 CLK_CKDIVR Clock divider regist er 0x18 0x00 50C7 CLK_PCKENR1 Peripher al clock gating register 1 0xFF 0x00 50C8 CLK_CSSR Clock security system register 0x00

0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating registe r 2 0xFF 0x00 50CB CLK_CANCCR CAN clock control register 0x00 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming

register

0x00 50CD CLK_SWIMCCR

0x00 50CE to

SWIM clock control register 0bXXXX

Reserved area (3 bytes)

0x00 50D0 0x00 50D1 WWDG WWDG_CR WWDG control regist er 0x7F 0x00 50D2 WWDG_WR WWDR window register 0x7F

0x00 50D3 to

Reserved area (13 bytes)

0x00 50DF

0x00 50E0 IWDG IWDG_KR IWDG key register 0xXX

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3 to

Reserved area (13 bytes)

0x00 50EF

0x00 50F0 AWU AWU_CSR1 AWU control/ status register 1 0x00

status

0x00

(1)

0x00

XXX0

28/99 DocID14771 Rev 13

STM8S105xx

Memory and register map

Address Block Register label Register name Reset

0x00 50F1 AWU_APR AWU asynchronous prescaler

buffer register 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP_CSR BEEP control/ status register 0x1F

0x00 50F4 to

Reserved area (12 bytes)

0x00 50FF 0x00 5200 SPI SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF 0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF

0x00 5208 to

Reserved area (8 bytes)

0x00 520F 0x00 5210 I2C I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C Own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 Reserved 0x00 5216 I2C_DR I2C data register 0x00 0x00 5217 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C clock control register low 0x00

0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02

0x00 521E I2C_PECR I2C packet error checking register 0x00

0x00 521F to

Reserved area (17 bytes)

0x00 522F

0x00 5230 to

Reserved area (6 bytes)

0x00 523F 0x00 5240 UART2 UART2_SR UART2 status register 0xC0 0x00 5241 UART2_DR UART2 data register 0xXX 0x00 5242 UART2_BRR1 UART2 baud rate regist er 1 0x00

status

0x3F

DocID14771 Rev 13 29/99

Memory and register map

STM8S105xx

Address Block Register label Register name Reset

0x00 5243 UART2_BRR2 UART2 baud rate regist er 2 0x00 0x00 5244 UART2_CR1 UART2 control register 1 0x00 0x00 5245 UART2_CR2 UART2 control register 2 0x00 0x00 5246 UART2_CR3 UART2 control register 3 0x00 0x00 5247 UART2_CR4 UART2 control register 4 0x00 0x00 5248 UART2_CR5 UART2 control register 5 0x00 0x00 5249 UART2_CR6 UART2 control register 6 0x00 0x00 524A UART2_GTR UART2 guard ti me register 0x00 0x00 524B UART2_PSCR UART2 prescaler register 0x00

0x00 524C to

Reserved area (4 bytes)

0x00 524F 0x00 5250 TIM1 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00

TIM1_CR1 TIM1 control register 1 0x00

0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture/ compare mode

register 1

0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode

register 2

0x00 525A TIM1_CCMR3 TIM1 capture/ compare mode

register 3

0x00 525B TIM1_CCMR4 TIM1 capture/compare mode

register 4

0x00 525C TIM1_CCER1 TIM1 capture/ compare enable

register 1

0x00 525D TIM1_CCER2 TIM1 capture/compare enable

register 2 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF 0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00

status

0x00

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STM8S105xx

Memory and register map

Address Block Register label Register name Reset

0x00 5265 TIM1_CCR1H TIM1 capture/ compare register 1

high

0x00 5266 TIM1_CCR1L TIM1 capture/ compare register 1

low

0x00 5267 TIM1_CCR2H TIM1 capture/ compare register 2

high

0x00 5268 TIM1_CCR2L TIM1 capture/ compare register 2

low

0x00 5269 TIM1_CCR3H TIM1 capture/ compare register 3

high

0x00 526A TIM1_CCR3L TIM1 capture/ compare register 3

low

0x00 526B TIM1_CCR4H TIM1 capture/ compare register 4

high

0x00 526C TIM1_CCR4L TIM1 capture/ compare register 4

low

0x00 526D TIM1_BKR TIM1 break r egister 0x00

0x00 526E TIM1_DTR TIM1 dead-time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00

0x00 5270 to

Reserved area (147 bytes)

0x00 52FF 0x00 5300 TIM2 0x00 5301 TIM2_IER T IM2 interrupt enable register 0x00

TIM2_CR1 TIM2 control register 1 0x00

0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2_CCMR1 TIM2 capture/ compare mode

register 1 0x00 5306 TIM2_CCMR2 TIM2 capture/ compare mode

register 2 0x00 5307 TIM2_CCMR3 TIM2 capture/ compare mode

register 3 0x00 5308 TIM2_CCER1 TIM2 capture/ compare enable

register 1 0x00 5309 TIM2_CCER2 TIM2 capture/ compare enable

register 2 0x00 530A TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2_CNTRL TIM2 counter low 0x00

0x00 530C TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH T IM2 auto-reload register high 0xFF

0x00 530E TIM2_ARRL TIM2 auto-reload register low 0xFF

status

0x00

DocID14771 Rev 13 31/99

Memory and register map

STM8S105xx

Address Block Register label Register name Reset

0x00 530F TIM2_CCR1H TIM2 capture/ compare regis ter 1

high

0x00 5310 TIM2_CCR1L TIM2 capture/ compare register 1

low 0x00 5311 TIM2_CCR2H TIM2 capture/ compare reg. 2 high 0x00 0x00 5312 TIM2_CCR2L TIM2 capture/ compare register 2

low 0x00 5313 TIM2_CCR3H TIM2 capture/ compare register 3

high

0x00 5314 TIM2_CCR3L TIM2 capture/ compare register 3

low

0x00 5315 to

Reserved area (11 bytes)

0x00 531F 0x00 5320 TIM3 TIM3_CR1 TIM3 control register 1 0x00 0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3_CCMR1 TIM3 capture/ compare mode

register 1

0x00 5326 TIM3_CCMR2 TIM3 capture/ compare mode

register 2

0x00 5327 TIM3_CCER1 TIM3 capture/ compare enable

register 1 0x00 5328 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 532B TIM3_ARRH TIM3 auto-reload register high 0xFF

0x00 532C TIM3_ARRL TIM3 auto-reload register lo w 0xFF 0x00 532D TIM3_CCR1H TIM3 c apture/ compare register 1

high

0x00 532E TIM3_CCR1L TIM3 capture/ compare register 1

low

0x00 532F TIM3_CCR2H TIM3 capture/ compare regis ter 2

high

0x00 5330 TIM3_CCR2L T IM3 capture/ compare register 2

low

0x00 5331 to

Reserved area (15 bytes)

0x00 533F 0x00 5340 TIM4 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00

status

0x00

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STM8S105xx

Memory and register map

Address Block Register label Register name Reset

0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM 4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF

0x00 5347 to

Reserved area (153 bytes)

0x00 53DF

0x00 53E0 to

ADC1 ADC _DBxR ADC data buffer registers 0x00

0x00 53F3

0x00 53F4 to

Reserved area (12 bytes)

0x00 53FF 0x00 5400 ADC1 ADC _CSR ADC control/ status register 0x00 0x00 5401 ADC_CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configurat i on r egister 2 0x00 0x00 5403 ADC_CR3 ADC configurat i on r egister 3 0x00 0x00 5404 ADC_DRH ADC data register high 0xXX 0x00 5405 ADC_DRL ADC data register low 0xXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable

register high

0x00 5407 ADC_TDRL ADC Schmitt trigger disable

register low 0x00 5408 ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low 0xFF 0x00 540A ADC_LTRH ADC low threshold r egister high 0x00 0x00 540B ADC_LTRL ADC low threshold register low 0x00

0x00 540C ADC_AWSRH ADC analog watchdog status

register high

0x00 540D ADC_AWSRL ADC analog watchdog status

register low 0x00 540E ADC _AWCRH ADC analog watchdog control

register high

0x00 540F ADC_AWCRL ADC analog watchdog control

register low

0x00 5410 to

Reserved area (1008 bytes)

0x00 57FF

Notes:

(1)

Depends on the previous reset source.

(2)

Write only register.

status

0x00

DocID14771 Rev 13 33/99

Memory and register map

STM8S105xx

6.2.3 CPU/SWIM/debug module/interrupt controller registers

Table 10: CPU/SWIM/debug module/interrupt controller registers

Address Block Register

Register name Reset

label

0x00 7F00 CPU 0x00 7F01 PCE Program counter extended 0x00

(1)

A Accumulator 0x00

0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x07 0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CCR Condition code register 0x28

0x00 7F0B to 0x00

Reserved area (85 bytes)

7F5F 0x00 7F60 CPU CFG_GCR Global configurat ion register 0x00 0x00 7F70 ITC ITC_SPR1 Interrupt software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF 0x00 7F74 ITC_SPR5 Interrupt software priority regist er 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF

0x00 7F78 to 0x00

Reserved area (2 bytes)

7F79 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81 to 0x00

Reserved area (15 bytes)

7F8F 0x00 7F90 DM DM_BK1RE DM breakpoint 1 register extended

byte 0x00 7F91 DM_BK1RH DM breakpoint 1 regis ter high byte 0xFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE DM breakpoi nt 2 register extended

byte 0x00 7F94 DM_BK2RH DM breakpoint 2 regis ter high byte 0xFF 0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 DM debug module control 0x00

status

0xFF

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STM8S105xx

Memory and register map

register 1

Address Block Register

label

Register name Reset

status

0x00 7F97 DM_CR2 DM debug module control

register 2

0x00 7F98 DM_CSR1 DM debug module control/status

register 1

0x00 7F99 DM_CSR2 DM debug module control/status

register 2

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B to 0x00

Reserved area (5 bytes)

7F9F

Notes:

(1)

Accessible by debug module only

0x00

0x10

0x00

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Interrupt vector mapping

STM8S105xx

7 Interrupt vector mapping

Table 11: Interrupt mapping

IRQ

no.

Source

block

Description Wakeup from

halt mode

Wakeup from

active-halt

Vector

address

mode

RESET Reset Yes Yes 0x00 8000

TRAP Software interrupt - - 0x00 8004

0 TLI Exter nal top level interrupt

- - 0x00 8008 1 AWU Auto wake up from halt - Yes 0x00 800C 2 CLK Clock controller - - 0x00 8010 3 EXTI0 Port A external interrupts Yes

(1)

Yes

(1)

0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 9

Reserved - - 0x00 802C

0x00 8028

10 SPI End of transfer Yes Yes 0x00 8030 11 TIM1 TIM1 update/ overflow/

- - 0x00 8034

underflow/ trigger/ break 12 TIM1 TIM1 capture/ compare - - 0x 00 8038 13 TIM2 TIM update/ overflow - - 0x00 803C 14 TIM2 TIM capture/ compare - - 0x00 8040 15 TIM3 Update/ overflow - - 0x00 8044 16 TIM3 Capture/ comp ar e - - 0x00 8048 17 18

Reserved - - 0x00 804C

Reserved - - 0x00 8050 19 I2C I2C interrupt Yes Yes 0x00 8054 20 UART2 Tx complete - - 0x00 8058 21 UART2 Receive register DATA

- - 0x00 805 C

FULL

22 ADC1 ADC1 end of conversion/

- - 0x00 8060

analog watchdog interrupt 23 TIM4 TIM update/ overflow - - 0x00 8064 24 Flash EOP/ WR_PG_DIS - - 0x00 8068

Reserved

0x00 806C to

0x00807C

Notes:

(1)

Except PA1

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STM8S105xx

Option bytes

8 Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byt e has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in the table below.

Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (v ia S WIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user m anual (UM0470) for information on SWIM programming procedures.

Addr.

Option

name

0x4800 Read-out

protection

(ROP) 0x4801 User boot 0x4802 0x4803 Alternate 0x4804

0x4805h Miscell.

0x4806

0x4807

0x4808

0x4809 HSE clock 0x480A 0x480B Reserved OPT6 0x480C 0x480D Reserved OPT7 0x480E

0x480F0x48FD

0x487E Bootloader OPTBL

code(UBC)

function

remapping

Reserved

(AFR)

option

Clock option

startup

Option

byte no.

7

OPT0

OPT1

NOPT1

OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0

NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0

OPT3

NOPT3

OPT4

NOPT4

OPT5

NOPT5

NOPT6

NOPT7

6

Reserved

Table 12: Option bytes

Option bits

5

4

ROP [7:0]

UBC [7:0]

NUBC [7:0]

HSI

TRIM NHSI

TRIM

HSECNT [7:0]

NHSECNT [7:0]

Reserved Reserved Reserved Reserved

BL[7:0]

3

LSI_

EN

NLSI_

EN

EXT CLK

IWDG

_HW

NIWDG

_HW

CKAWU

SEL

NCKA

WUSEL

2

WWDG

NWWDG

PRS C1 PRS C0

NPRSC1 NPR

1

_HW

0

WWDG

_HALT

NWW

G_HALT

SC0

Factory

default setting

00h

00h FFh 00h FFh

00h

FFh

00h

FFh

00h FFh 00h FFh 00h FFh

00h

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Option bytes

STM8S105xx

Addr.

0x487F

Option

name

Option

byte no.

NOPTBL

Option bits

7

6

5

4

NBL[7:0]

3

2

1

0

Factory

default setting

Table 13: Option byte descripti on

Option

byte no.

OPT0

OPT1

OPT2

OPT3

OPT4

Description

ROP[7:0] Memory readout protection (ROP)

AAh: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference ma nual (RM0016) section on Flash/EEP R OM

memory readout protection for detai ls.

UBC[7:0] User boot code area

0x00: no UBC, no write-protection 0x01: Page 0 to 1 defined as UBC, memory write-protected 0x02: Page 0 to 3 defined as UBC, memory write-protected 0x03: Page 0 to 4 defined as UBC, memory write-protected

...

0x3E: Pages 0 to 63 defined as UBC, memory write-protected

Other values: Reserved

Note: Refer to the family reference ma nual (RM0016) section on Flash write pr otection

for more details.

AFR[7:0]

Refer to following table for the alt ernate function remapping decriptions of bits [7:2].

HSITRIM:High speed internal clock tr i m ming register size

0: 3-bit trimming supported in CLK_HS ITRIMR register 1: 4-bit trimming supported in CLK_HS ITRIMR register

LSI_EN:Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activ ated by software

1: IWDG Independent watchdog activ ated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG ac tive

EXTCLK: External clock selection

0: External crystal connected t o OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL:Auto wake-up unit/clock 0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for for AWU

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STM8S105xx

Option bytes

Option

Description

byte no.

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler

OPT5

HSECNT[7:0]:HSE crystal oscillator stabilization time

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles OPT6 Reserved OPT7 Reserved

OPTBL

BL[7:0] Bootloader option byte

For STM8S products, this option is checked by the boot ROM code after reset.

Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the

CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S

bootloader manual) for more details.

For STM8L products, the bootloader option bytes are on addresses 0xXXXX a nd

0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not.

For more details, refer to the UM0560 (S TM8L/S bootloader manual) for more details.

Table 14: Description of alternate function remapping bits [7:0] of OPT2

Option

byte no.

OPT2

AFR7 Alternate function remapping option 7

0: AFR7 remapping option inactiv e: Default alternate function

1: Port D4 alternate function = BEEP .

AFR6 Alternate function remapping option 6

0: AFR6 remapping option inactiv e: Default alternate functions

1: Port B5 alternate function = I2C_SDA; port B4 alternate function = I2C_SCL.

AFR5 Alternate function remapping option 5

0: AFR5 remapping option inactiv e: Default alternate functions

1: Port B3 alternate function = TIM1_ETR; port B2 alternate function = TIM1_NCC3;

port B1 alternate function = TIM1_CH 2N; port B0 alternate function = TI M1_CH1N.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactiv e: Default alternate function

1: Port D7 alternate function = TI M1_CH4.

AFR3 Alternate function remapping option 3

0: AFR3 remapping option inactiv e: Default alternate function

1: Port D0 alternate function = TI M 1_BKIN.

AFR2 Alternate function remapping option 2

0: AFR2 remapping option inactiv e: Default alternate function

1: Port D0 alternate function = CLK_C C O. Note: AFR2 option has priorit y over AFR3 if

AFR1 Alternate function remapping option 1

0: AFR1 remapping option inactiv e: Default alternate functions

Description

both are activated.

(1)

(2)

.

(2)

.

(2)

.

(2)

.

(2)

.

(2)

.

(2)

.

DocID14771 Rev 13 39/99

Option bytes

STM8S105xx

(1)

1: Port A3 alternate function = TIM3_C H1; port D2 alternate function TIM2_CH3.

Option

byte no.

Description

AFR0 Alternate function remapping option 0

0: AFR0 remapping option inactiv e: Default alternate function

1: Port D3 alternate function = ADC_ETR.

Notes:

(1)

Do not use more than one remapping option in the same port.

(2)

Refer to pinout description.

(2)

.

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STM8S105xx

Unique ID

9 Unique ID

The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. T he 96 bits of the identifier can never be altered by the user.

The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm.

The unique device identifier is ideally suited:

• For use as serial numbers

• For use as security keys to increase the code security in the program memory while

using and combining this unique ID with software cr yptographic primitives and protocols before programming the internal memo ry .

• To activate secure boot processes

Address Content description Unique ID bits

0x48CD X co-ordinate on the wafer U_ID[7:0] 0x48CE U_ID[15:8] 0x48CF Y co-ordinate on the wafer U_ID[23:16] 0x48D0 U_ID[31:24] 0x48D1 Wafer number U_ID[39:32] 0x48D2 Lot number U_ID[47:40] 0x48D3 U_ID[55:48] 0x48D4 U_ID[63:56] 0x48D5 U_ID[71:64] 0x48D6 U_ID[79:72] 0x48D7 U_ID[87:80] 0x48D8 U_ID[95:88]

Table 15: Unique ID registers (96 bits)

7 6 5 4 3 2 1 0

DocID14771 Rev 13 41/99

Electrical characteristics

STM8S105xx

10 Electrical characteristics

10.1 Parameter conditions

Unless otherwise specified, all voltages are referr ed to VSS.

10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at T by the selected temperature range).

Data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested i n production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ).

10.1.2 Typical values

= 25 °C and TA = T

A

Amax

(given

Unless otherwise specified, typical data are based on TA = 25 °C, V only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temper ature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ).

10.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

10.1.4 Typical current consumption

For typical current consumption measurements, VDD, V together in the configuration shown in the following f i gure.

Figure 8: Supply current measurement conditions

DDIO

and V

= 5 V. They are given

DD

are connected

DDA

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STM8S105xx

Electrical characteristics

10.1.5 Loading capacitor

The loading conditions used for pin parameter measurement are shown in the following figure.

10.1.6 Pin input voltage

The input voltage measurement on a pin of the device is described in the following figure.

Figure 9: Pin loading conditions

Figure 10: Pin input voltage

10.2 Absolute maximum ratings

Stresses above those listed as ‘absolute maximum r atings’ may cause permanent damage to the device. This is a stress rating only and functio nal operation of the device under these conditions is not implied. Exposure to maximum rat i ng conditions for extended periods may affect device reliability.

Table 16: Voltage characteristics

Symbol Ratings Min Max Unit

V

- VSS Supply voltage (including V

DDx

V

DDIO

(1)

)

VIN Input voltage on true ope n drain

pins (PE1, PE2)

Input voltage on any other pin

|V

- Variations between different power

DDx

DocID14771 Rev 13 43/99

DDA and

(2)

V

-0.3 6.5 V

- 0.3 6.5

V

SS

- 0.3 V

SS

+ 0.3

DD

50 mV

Electrical characteristics

STM8S105xx

VDD|

pins

When several inputs are submitted to a current injection, the maximum ΣI

INJ(PIN)

is the absolute sum of the

Symbol Ratings Min Max Unit

|V

SSx

V

SS

V

ESD

Variations between all the different

-

|

ground pins

50

Electrostatic discharge voltage see Section 13.3.12.4: "Absolute maximum ratings

(electrical sensitivity)"

Notes:

(1)

All power (VDD, V

power supply

(2)

I

INJ(PIN)

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot

be respected, the injection current must be limited externally to the I

while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection

V

IN>VDD

current, and the corresponding V

DDIO

, V

) and ground (VSS, V

DDA

maximum must always be respected

IN

SSIO

, V

) pins must always be connected to the external

SSA

value. A positive injection is induced by

INJ(PIN)

Table 17: Current characteristics

Symbol Ratings Max.

I

Total current into V

VDD

I

Total curr ent out of V

VSS

power lines (source)

DD

ground lines (sink)

SS

(2)

60 mA

(2)

60

(1)

IIO Output current sunk by any I/O and control pin 20

Output current source by any I/Os and control pin 20

ΣI

Total output current sourced (sum of all I/O and control pi ns) for devices

I

INJ(PIN)

IO

with two V

DDIO

Total output current sourced (sum of al l I/O and control pins) for devices

with one V

DDIO

Total output current sunk (sum of all I/O and control pins) for devices

with two V

SSIO

Total output current sunk (sum of all I/O and control pins) for devices

with one V

(4)(5)

Injected current on NRST pin ±4

SSIO

pins

(3)

200

100

160

80

Injected current on OSCIN pin ±4

(6)

±4

(6)

±20

ΣI

INJ(PIN)

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

All power (VDD, V

supply.

(3)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package

between the V

(4)

I

INJ(PIN)

DDIO/VSSIO

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the I V

while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection

IN>VDD

current, and the corresponding V

(5)

Negative injection disturbs the analog performance of the device. See note in Section 7.11: "TIM2, TIM3 -

DDIO

, V

) and ground (VSS, V

DDA

pins.

maximum must always be respected

IN

SSIO

, V

) pins must always be connected to the external

SSA

value. A positive injection is induced by

INJ(PIN)

16-bit general purpose timers".

(6)

Unit

44/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

positive and negative injected currents (instantaneous values). These results are based on characterization with

ΣI

maximum current injection on four I/O port pins of the device.

INJ(PIN)

Table 18: Thermal characteristics

Symbol Ratings Value Unit

T

Storage temperature range -65 to 150 °C

STG

TJ Maximum junction t emperature 150

10.3 Operating conditions

The device must be used in operating conditions that respect the parameters in the table below. In addition, full account must be taken of all physical capacitor characteristics and tolerances.

Table 19: General operating conditions

Symbol Parameter Conditions Min Max Unit

f

Internal CPU clock

CPU

VDD/

V

DD_IO

VCAP

(1)

(3)

P

Power dissipation at TA

D

TA Ambient temperature for

TJ Junction temperature

Notes:

(1)

Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range.

(2)

This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.

(3)

To calculate P the value for T

(4)

Refer to Section 7.7: "Watchdog timers"

frequency

Standard operating

voltage

: capacitance of

C

EXT

external capacitor

ESR of external

capacitor

ESL of external

capacitor

= 85 °C for suffix 6or

TA= 125° C for suffix 3

6 suffix version

Ambient temperature for

3 suffix version

range

), use the formula P

Dmax(TA

given in the current table and the value for Θ

Jmax

at 1 MHz

(2)

44 and 48-pin devices, with output on

eight standard ports, two high sink

ports and two open drain ports

simultaneously

(4)

32-pin package, with output on eight

standard ports and two high sink ports

simultaneously

(4)

Maximum power dissipation -40 85 °C

Maximum power dissipation -40 125

6 suffix version -40 105 3 suffix version -40 130

= (T

- T

)/Θ

Dmax

Jmax

(see Section 7.7: "Watchdog timers" ) with

A

JA

given in Section 7.7: "Watchdog timer s ".

JA

0 16 MHz

2.95 5.5 V

470 3300 nF

- 0.3

Ohm

- 15 nH

- 443 mW

- 360

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Electrical characteristics

STM8S105xx

Figure 11: fCPUmax versus VDD

Table 20: Operating condition s at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit

t

VDD rise time rate

VDD

VDD fall time rate

t

Reset releasedelay VDD rising

TEMP

V

Power-on reset thres hold

IT+

V

Brown-out reset threshold

IT-

V

Brown-out reset hysteresis

HYS(BOR)

(1)

2.0

(1)

∞ µs/V ∞

(1)

1.7

ms

2.65 2.8 2.95 V

2.58 2.7 2.88 70

mV

Notes:

(1)

Guaranteed by design, not tested in production.

10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved c onnecting an external capacitor C

pin. C

V

CAP

the series inductance to less than 15 nH.

46/99 DocID14771 Rev 13

is specified in the Operating conditions section. Care should be taken to limit

EXT

to the

STM8S105xx

Electrical characteristics

Figure 12: External capacitor CEXT

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

10.3.2 Supply current characteristics

The current consumption is measured as described i n Section 7.3: "Interrupt controller".

10.3.2.1 Total current consumption in run mode

Table 21: Total current consumption with code execution in run mode at VDD = 5 V

Symbol

I

DD(RUN)

I

DD(RUN)

Parameter Conditions Typ Max

Supply current in run mode,

code executed from RAM

Supply current in run mode,

code executed from Flash

f

CPU

= 16 MHz

f

= f

CPU

125 kHz

f

= f

CPU

15.625 kHz

f

CPU

= 128 kHz

f

CPU

= 16 MHz

f

CPU

= f

MASTER

= f

MASTER

= f

MASTER

= f

MASTER

HSE crystal

osc.

(16 MHz)

HSE user

ext. clock (16 MHz)

HSI RC osc.

(16 MHz)

/128 =

HSE user

ext. clock (16 MHz)

HSI RC osc.

(16 MHz)

/128 =

HSI RC osc. (16 MH3z/8)

LSI RC osc.

(128 kHz)

HSE crystal

osc.

(16 MHz)

HSE user

ext. clock (16 MHz)

HSI RC osc.

(16 MHz)

HSI RC osc. 1.5

(1)

3.2

2.6 3.2

2.5 3.2

1.6 2.2

1.3 2.0

0.75

0.55

7.7

7.0 8.0

Unit

mA

DocID14771 Rev 13 47/99

Electrical characteristics

STM8S105xx

= 2 MHz

(16 MHz/8)

Symbol

Parameter Conditions Typ Max

(2)

f

= f

CPU

125 kHz

f

= f

CPU

15.625 kHz

f

CPU

= 128 kHz

MASTER

= f

MASTER

/128 =

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

LSI RC osc.

(128 kHz)

1.35 2.0

0.75

0.6

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Table 22: Total current consumption with code execution in run mode at VDD = 3.3 V

Unit

(1)

Symbol

I

DD(RUN)

Parameter Conditions Typ Max

Supp ly current in run mode,

code executed from RAM

Supply current in run mode,

code executed from Flash

f

= f

CPU

f

= f

CPU

= 125 kHz

f

= f

CPU

15.625 kHz

f

= f

CPU

f

= f

CPU

f

= f

CPU

MASTER

MHz

MASTER

kHz

MASTER

MHz

MASTER

MHz

= 16

/128

/128 =

= 128

= 16

= 2

HSE crystal

osc.

(16 MHz)

HSE user ext.

clock

(16 MHz)

HSI RC osc.

(16 MHz)

HSE user ext.

clock

(16 MHz)

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

LSI RC osc.

(128 kHz)

HSE crystal

osc.

(16 MHz)

HSE user ext.

clock

(16 MHz)

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

(2)

2.8

2.6 3.2

2.5 3.2

1.6 2.2

1.3 2.0

0.75

0.55

7.3

7.0 8.0

1.5

Unit

(1)

mA

48/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

Symbol

Parameter Conditions Typ Max

f

= f

CPU

MASTER

= 125 kHz

f

= f

CPU

MASTER

15.625 kHz

f

= f

CPU

MASTER

kHz

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

10.3.2.2 Total current consumption in wait mode

Table 23: Total current consumption in wait mode at VDD = 5 V

/128

/128 =

= 128

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

LSI RC osc.

(128 kHz)

(1)

1.35 2.0

0.75

0.6

Unit

Symbol

I

Supply current in wait

DD(WFI)

Parameter Conditions Typ Max

f

CPU

= f

= 16 MHz HSE crystal

MASTER

mode

f

CPU

= f

MASTER

/128 = 125

kHz

f

CPU

= f

MASTER

/128 =

15.625 kHz

f

= f

CPU

= 128 kHz LSI RC osc.

MASTER

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

Table 24: Total current consumption in wait mode at VDD = 3.3 V

osc.

(16 MHz)

HSE user ext.

clock

(16 MHz)

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

(2)

(128 kHz)

2.15

1.55 2.0

1.5 1.9

1.3

0.7

0.5

Unit

(1)

mA

Symbol

I

Supply current in wait

DD(WFI)

Parameter Conditions Typ Max

mode

Unit

(1)

f

CPU

= f

= 16 MHz HSE crystal

MASTER

1.75

mA

osc.

(16 MHz)

HSE user ext.

1.55 2.0

clock

DocID14771 Rev 13 49/99

Electrical characteristics

STM8S105xx

(16 MHz)

Symbol

Parameter Conditions Typ Max

(1)

Unit

f

CPU

= f

MASTER

/128 = 125

kHz

f

CPU

= f

MASTER

/128 =

15.625 kHz

f

= f

CPU

= 128 kHz LSI RC osc.

MASTER

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

Default clock configuration measured with all peripherals off.

10.3.2.3 Total current consumption in active halt mode

Table 25: Total current consump tion in active halt mode at VDD = 5 V

Symbol Parameter Conditions Typ Max

I

Supply current

DD(AH)

in active halt

mode

Main voltage

regulator

(MVR)

(2)

On Operating

Off Operating

Flash

mode

Power-

down mode

mode

Power-

down mode

(3)

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz)

HSI RC osc.

(16 MHz/8)

(128 kHz)

Clock

source

HSE

crystal

osc.

(16

MHz)

LSI RC

osc.

(128 kHz)

HSE

crystal

osc.

(16

MHz)

LSI RC

osc.

(128 kHz)

LSI RC

osc.

(128 kHz)

1.5 1.9

1.3

0.7

(2)

0.5

Max

at 85

°C

at 125

(1)

°C

1080

200 320 400

1030

140 270 350

68 120 220

12 60 150

Unit

(1)

µA

50/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

Notes:

(1)

Data based on characterization results, not tested in production

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Table 26: Total current consump tion in active halt mode at VDD = 3.3 V

Symbol Parameter Conditions Typ Max

at 85

°C

(1)

I

Supply current

DD(AH)

in active halt

mode

Main voltage

regulator

(MVR)

(2)

On Operating

Flash

mode

Clock

source

HSE

680

(3)

crystal

osc.

(16 MHz)

LSI RC

200 320 400

osc. (128

kHz)

Power-

down mode

HSE

crystal

osc.

630

(16 MHz)

LSI RC

140 270 350

osc. (128

kHz)

Off Operating

mode

Power-

LSI RC

osc. (128

kHz)

66 120 220

10 60 150 down mode

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

Configured by the REGAH bit in the CLK_ICKR register.

(3)

Configured by the AHALT bit in the FLASH_CR1 register.

Max

at 125

(1)

°C

Unit

µA

10.3.2.4 Total current consumption in halt mode

Table 27: Total current consumption in halt mode at VDD = 5 V

Symbol

I

Supply current in

DD(H)

Notes:

(1)

Data based on characterization results, not tested in production.

Parameter Conditions Typ Max at

Flash in operating mode, HSI

halt mode

clock after wakeup

Flash in powerdown mode,

HSI clock after wakeup

DocID14771 Rev 13 51/99

85 °C

Max at

(1)

125 °C

Unit

(1)

62 90 150 µA

6.5 25 80

Electrical characteristics

STM8S105xx

Table 28: Total current consumption in halt mode at VDD = 3.3 V

Symbol

I

Supply current in

DD(H)

Parameter Conditions Typ Max at

Flash in operating mode, HSI

halt mode

clock after wakeup

Flash in powerdown mode,

HSI clock after wakeup

Notes:

(1)

Data based on characterization results, not tested in production.

10.3.2.5 Low power mode wakeup times

Table 29: Wakeup times

Symbol

t

WU(WFI)

t

WU(AH)

t

WU(H)

Notes:

(1)

Data guaranteed by design, not tested in production.

(2)

Measured from interrupt event to interrupt vector fetch.

(3)

t

WU(WFI)

(4)

Configured by the REGAH bit in the CLK_ICKR register.

(5)

Configured by the AHALT bit in the FLASH_CR1 register.

Parameter Conditions Typ Max

Wakeup time

from

wait mode to run

(2)

active

from

+ 67 x 1/f

master

MVR

voltage

regulator

(2)

on

(4)

MVR

voltage

regulator

(2)

on

(4)

MVR

voltage

regulator

(2)

off

(4)

MVR

voltage

regulator

(2)

off

(4)

Flash in operating mode

Flash in power-down mode

(2)

CPU.

mode

Wakeup time

halt mode to run

mode

Wakeup time

halt mode to run

mode

Wakeup time

halt mode to run

mode

Wakeup time

halt mode to run

mode

Wak eup time

halt mode to run

mode

= 2 x 1/f

f

CPU

= f

0 to 16 MHz

= 16 MHz 0.56

MASTER

Flash in

operating

(5)

mode

Flash in

power-down

(5)

mode

Flash in

operating

(5)

mode

Flash in

power-down

(5)

mode

(1)

85 °C

125 °C

60 90 150 µA

4.5 20 80

See note

(6)

1

HSI

2

(after

wakeup)

HSI

3

(6)

(after

wakeup)

48

(6)

50

(6)

HSI

(after

wakeup)

HSI

(after

wakeup)

(5)

52

(5)

54

Max at

(1)

(3)

(6)

(1)

Unit

μs

52/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

(6)

Plus 1 LSI clock depending on synchronization.

(1)

10.3.2.6 Total current consumption and timing in forced reset state

Table 30: Total current consumption and timing in forced reset state

Symbol Parameter Conditions Typ Max

I

Supply current in reset state

DD(R)

(2)

VDD = 5 V 500

VDD = 3.3 V 400

t

Reset pin release to vector fetch

RESETBL

Notes:

(1)

Data guaranteed by design, not tested in production.

(2)

Characterized with all I/Os tied to VSS.

10.3.2.7 Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.

(1)

Unit

μA

150 μs

HSI internal RC/f

CPU

= f

MASTER

= 16 MHz.

Table 31: Peripheral current consumption

Symbol Parameter Typ. Unit

(1)

230 µA

(1)

115

90

(1)

30

(2)

110

(2)

45

(2)

65

(3)

955

I

DD(TIM1)

I

DD(TIM2)

I

DD(TIM3)

I

DD(TIM4)

I

DD(UART2)

I

DD(SPI)

I

DD(I2C)

I

DD(ADC1)

TIM1 supply current TIM2 supply current TIM3 timer supply current TIM4 timer supply current

UART2 supply current

SPI supply current

I2C supply current

ADC1 supply current when converting

Notes:

(1)

Data based on a differential IDD measurement between reset configuration and timer counter running at 16

MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

(2)

Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not tested in production.

(3)

Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Not tested in production.

10.3.2.8 Current consumption curves

The following figures show typical current consumpt ion measured with code executing in RAM.

DocID14771 Rev 13 53/99

Electrical characteristics

STM8S105xx

Figure 13: Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz

Figure 14: Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD= 5 V

Figure 15: Typ. IDD(RUN) vs. VDD, HSI RC osc, fCPU = 16 MHz

54/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

Figure 16: Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz

Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V

Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz

DocID14771 Rev 13 55/99

Electrical characteristics

STM8S105xx

10.3.3 External clock sources and timing characteristics

HSE user external clock

Subject to general operating conditions for VDD and TA.

Table 32: HSE user external clock characteristics

Symbol Parameter Conditions Min Max Unit

f

User external clock source

HSE_ext

(1)

V

I

LEAK_HSE

OSCIN input pin high level voltage 0.7 x

HSEH

(1)

OSCIN input pin low level voltage VSS 0.3 x VDD

HSEL

OSCIN input leakage current V

Notes:

(1)

Data based on characterization results, not tested in production.

frequency

SS

Figure 19: HSE external clocksource

< V

V

DD

<

IN

0 16

MHz

+ 0.3

V

DD

V

-1 +1 μA

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, t he resonator and the load capacitors have to be placed as close as possible to the oscillator pin s in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).

Table 33: HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

External high speed

HSE

oscillator frequency

RF Feedback resistor

56/99 DocID14771 Rev 13

1

220

16 MHz

kΩ

STM8S105xx

Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

C

Recommended load

capacitance

I

HSE oscillator power

DD(HSE)

consumption

gm Oscillator

(2)

C = 20 pF,

= 16 MHz

f

OSC

C = 10 pF,

=16 MHz

f

OSC

5

20 pF

6 (startup)

1.6 (stabilized) 6 (startup)

1.2 (stabilized)

(3)

mA

mA/V

transconductance

(4)

t

SU(HSE)

Startup time VDD is stabilized

1

ms

Notes:

(1)

C is approximately equivalent to 2 x crystal Cload.

(2)

The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm

value. Refer to crystal manufacturer for more details

(3)

Data based on characterization results, not tested in production.

(4)

t oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz

SU(HSE)

Figure 20: HSE oscillator circuit diagram

HSE oscillator critical g

= (2 × Π × f

g

mcrit

: Notional resistance (see crystal specificat i on)

R

m

L

: Notional inductance (see crystal specification)

m

C

: Notional capacitance (see crystal specification)

m

)2 × Rm(2Co + C)2

HSE

equation

m

Co: Shunt capacitance (see crystal specification)

= C

C

L1

g

m

= C: Grounded external capacitance

L2

>> g

mcrit

DocID14771 Rev 13 57/99

Electrical characteristics

STM8S105xx

10.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA. High speed internal RC oscillator (HSI)

Table 34: HSI oscillator character istics

Symbol

f

Frequency

HSI

ACC

Accuracy of HSI

HSI

Parameter Conditions Min Typ Max Unit

User-trimmed with

oscillator

CLK_HSITRIMR register for given

VDD and TA conditions

Accuracy of HSI

oscillator (factory

calibrated)

VDD = 5 V, TA = 25°C

V

= 5 V, 25 °C ≤ TA ≤ 85 °C -2.0

DD

2.95 ≤ V

≤ 5.5 V,-40 °C ≤ T

DD

125 °C

t

HSI oscillator wake-up

su(HSI)

time including

calibration

I

HSI oscillator power

DD(HSI)

consumption

Notes:

(1)

Refer to application note.

(2)

Guaranteed by design, not tested in production.

(3)

Data based on characterization results, not tested in production.

Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temperatures

(1)

(3)

-1.0

≤

A

-3.0

(3)

16

170 250

1.0

(2)

1.0

2.0

3.0

(3)

1.0

(2)

(3)

MHz

%

µs

µA

58/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

Figure 22: Typical HSI accuracy vs VDD @ 4 temperat ures

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDD and TA.

Table 35: LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

f

Frequency 110 128 146 kHz

LSI

t

LSI oscillator wakeup time

su(LSI)

I

LSI oscillator power consumption

DD(LSI)

Notes:

(1)

Guaranteed by design, not tested in production.

Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures

5

(1)

7

µs

µA

DocID14771 Rev 13 59/99

Electrical characteristics

STM8S105xx

10.3.5 Memory characteristics

RAM and hardware registers

Table 36: RAM and hardware register s

Symbol Parameter Conditions Min Unit

VRM Data retention mode

Notes:

(1)

Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to

bit advanced control timer"

(2)

Refer to the Operating conditions section for the value of V

Flash program memory/data EEPROM memory

General conditions: TA = -40 to 125°C.

for the value of V

Table 37: Flash program memory/dat a E EPROM memory

(1)

Halt mode (or reset) V

Section 7.10: "TIM1 - 16-

IT-max

(2)

V

Symbol

VDD Operating voltage (all modes,

t

Standard programming t ime (including

prog

Parameter Conditions Min

f

≤ 16

execution/write/erase)

CPU

MHz

(1)

2.95

Typ Max Unit

5.5 V

6.0 6.6 ms

erase) for byte/word/block (1 byte/4

bytes/128 bytes)

Fast programming time for 1 block (128

3.0 3.3 ms

bytes)

t

Erase time for 1 block (128 bytes)

erase

NRW Erase/write cycles

(2)

(program memory) TA = +85 °C 10 k

Erase/write cycles(data memory)

t

Data retention (program memory) after 10k

RET

erase/write cycles at T

= +85 °C

A

Data retention (data memory) aft er 10k

erase/write cycles at T

= +85 °C

A

Data retention (data memory) aft er 300 k

erase/write cycles at T

= +125 °C

A

IDD Supply current (Flash programming or

(2)

TA = +125 °

C

T

= 55° C 20

RET

T

= 55° C 20

RET

T

= 85° C 1.0

RET

300

3.0 3.3 ms

1.0M

k

2.0

erasing for 1 to 128 bytes)

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

cycles

years

mA

60/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

10.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Table 38: I/O static characteristics

Symbol

VIL Input lo w level v oltag e V

VIH Input high level v ol tage 0.7 x

V

Hysteresis

hys

Rpu Pull-up resistor VDD = 5 V, V

tR, tF Rise and fall time(10 % -

Parameter Conditions Min Typ Max Unit

= 5 V -0.3

DD

0.3 x V

DD

VDD +

90 %)

V

DD

(1)

= VSS 30 55 80 kΩ

IN

700

Fast I/Os load = 50 pF

Standard and high sink

0.3 V

(2)

35

125

(2)

I/Os load = 50 pF

Fast I/Os load = 20 pF

Standard and high sink

20 50

(2)

I/Os load = 20 pF

I

Input leakage c urrent,

lkg

V

≤ V

SS

≤ VDD

IN

±1.0

(3)

analog and digital

I

Analog input leakage

lkg ana

V

≤ V

SS

≤ VDD

IN

±250

(3)

current

I

Leakage current in

lkg(inj)

adjacent I/O

(3)

Injection current ±4 mA

±1.0

(3)

Notes:

(1)

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in

production.

(2)

Data guaranteed by design.

(3)

Data based on characterization results, not tested in production.

V

mV

ns

µA

nA

µA

DocID14771 Rev 13 61/99

Electrical characteristics

STM8S105xx

Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures

Figure 25: Typical pull-up resistance vs VDD @ 4 temp er at ures

62/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

(1) (1)

(1)

Figure 26: Typical pull-up current vs VDD @ 4 temperatures

1. The pull-up is a pure resistor (slope goes through 0).

Table 39: Output driving current (standard ports)

Symbol Parameter Conditions Min Max Unit

VOL Output low level with four pins sunk IIO = 4 mA,

= 3.3 V

V

DD

Output low level with eight pins sunk IIO= 10 mA,

V

DD

VOH Output high level with four pin s sourced IIO = 4 mA,

V

= 3.3 V

DD

Output high level with eight pins sourc ed IIO = 10 mA,

V

DD

= 5 V

2.0

2.4

1.0

2.0

(1)

V

Notes:

(1)

Data based on characterization results, not tested in production

Table 40: Output driving current (true open drain ports)

Symbol Parameter Conditions Max Unit

VOL Output low level with two pins sunk IIO = 10 mA, V

Notes:

(1)

Data based on characterization results, not tested in production

Symbol Parameter Conditions Min Max Unit

VOL Output low level with four pins sunk IIO = 10 mA,

= 3.3 V 1.5

DD

IIO = 10 mA, V IIO = 20 mA, V

= 5 V 1.0

DD

= 5 V 2.0

DD

Table 41: Output driving current (high sink ports)

DocID14771 Rev 13 63/99

1.1

(1)

V

Electrical characteristics

STM8S105xx

V

= 3.3 V

Symbol Parameter Conditions Min Max Unit

Output low level with eight pins sunk IIO = 10 mA,

Output low level with four pins sunk IIO = 20 mA,

VOH Output high level with four pin s sourced IIO = 10 mA,

Output high level with eight pins sour c ed IIO = 10 mA,

Output high level with four pins sour c ed IIO = 20 mA,

Notes:

(1)

Data based on characterization results, not tested in production

10.3.7 Typical output level curves

The following figures show typical output lev el curves measured with output on a single pin.

Figure 27: Typ. VOL @ VDD = 5 V (standard ports)

DD

V

DD

V

DD

V

DD

V

DD

V

DD

= 5 V

= 3.3 V

= 5 V

1.9

3.8

2.9

0.9

(1)

1.6

(1)

64/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports)

Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports)

DocID14771 Rev 13 65/99

Electrical characteristics

STM8S105xx

Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports)

Figure 31: Typ. VOL @ VDD = 5 V (high sink ports)

66/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports)

Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports)

Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)

DocID14771 Rev 13 67/99

Electrical characteristics

STM8S105xx

Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports)

Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)

10.3.8 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 42: NRST pin characteristi cs

Symbol Parameter Conditions Min Typ Max Unit

V

R

t

68/99 DocID14771 Rev 13

NRST input low

IL(NRST)

level voltage

NRST input high

IH(NRST)

level voltage

NRST output low

OL(NRST)

level voltage

NRST pull-up

PU(NRST)

NRST input filtered

IFP(NRST)

resistor

pulse

(1)

IOL=2 mA 0.7 x VDD - VDD + 0.3

(1)

(2)

(3)

-0.3 - 0.3 x VDD V

- - 0.5

30 55 80 kΩ

- - 75 ns

STM8S105xx

Electrical characteristics

Symbol Parameter Conditions Min Typ Max Unit

t

INFP(NRST)

t

OP(NRST)

NRST input not

filtered pulse

(3)

NRST output

(3)

pulse

500 - -

20

- - μs

15

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

The RPU pull-up equivalent resistor is based on a resistive transistor

(3)

Data guaranteed by design, not tested in production.

Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures

Figure 38: Typical NRST pull-up resistance vs VDD @ 4 temperatures

DocID14771 Rev 13 69/99

Electrical characteristics

STM8S105xx

Figure 39: Typical NRST pull-up current vs VDD @ 4 temperatures

The reset network shown in the following figure prot ects the device against parasitic resets. The user must ensure that the level on the NRST pin c an go below V

IL(NRST)

max. (see

Table 38: "I/O static characteristics" ), ot herwise the reset is not taken into account

internally. For power consumption sensitive applications, t he external reset capacitor value can be

reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. M i ni mum recommended capacity is 100 nF.

10.3.9 SPI serial peripheral interface

70/99 DocID14771 Rev 13

Figure 40: Recommended reset pin protection

Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f conditions. t

MASTER

= 1/f

MASTER

.

frequency and VDD supply voltage

MASTER

Refer to I/O port characteristics for more detail s on t he input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

STM8S105xx

Electrical characteristics

(1) (1)

Table 43: SPI characteristics

Symbol Parameter Conditions Min Max Unit

f

SCK

t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

1

(1)

(1)(2)

(1)(3)

(1)

SPI clock frequency Mas ter mode 0 8

Slave mode 0 6

SPI clock rise and fall

time

Capacitive load: C = 30

pF

NSS setup time Slave mode 4 x

t

MASTER

NSS hold time Slave mode 70

SCK high and low time Master mode t

/2 - 15 t

SCK

Data input setup time Master mode 5 Data input setup time Slave mode 5

Data input hold time Master mode 7 Data input hold time Slave mode 10

Data output ac c ess time Slave mode

Data output disable time Slave mode 25

Data output valid time Slave mode

MHz

25 ns

ns

SCK

/2 +

ns

15

ns ns ns ns

3 x t

MASTER

ns

73 ns

(after enable edge)

(1)

t

Data output valid time Master mode

v(MO)

36 ns

(after enable edge)

(1)

t

Data output hold time Slave mode

h(SO)

28

ns

(after enable edge)

t

Master mode

h(MO)

12

ns

(after enable edge)

Notes:

(1)

Values based on design simulation and/or characterization results, and not tested in production.

(2)

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the

data.

(3)

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the

data in Hi-Z.

DocID14771 Rev 13 71/99

Electrical characteristics

STM8S105xx

Figure 41: SPI timing diagram - slave mode and CPHA = 0

Figure 42: SPI timing diagram - slave mode and CPHA = 1(1)

1. Measurement points are made at CMOS levels: 0.3 V

72/99 DocID14771 Rev 13

and 0.7 VDD.

DD

STM8S105xx

Electrical characteristics

(3)

(4)

(3)

Figure 43: SPI timing diagram - master mode(1)

1. Measurement points are made at CMOS levels: 0.3 V

10.3.10 I2C i nt er face characteristics

Table 44: I2C characteristics

Symbol Parameter Standard mode I2C Fast mode I2C

t

SCL clock low time 4.7

w(SCLL)

t

SCL clock high time 4.0

w(SCLH)

t

SDA setup time 250

su(SDA)

t

SDA data hold time 0

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

START condition hold time 4.0

h(STA)

t

Repeated START condition

su(STA)

t

STOP condition setup time 4.0

su(STO)

t

w(STO:STA)

STOP to START condition time

SDA and SCL rise time

SDA and SCL fall time

setup time

(bus free)

Min

4.7

(2)

Max

and 0.7 VDD.

DD

(2)

Min

1000

300

(2)

1.3

0.6 100 0

900

0.6

1.3

Max

300 ns

(1)

Unit

(2)

ns

μs μs

ns

μs μs

DocID14771 Rev 13 73/99

Electrical characteristics

STM8S105xx

(1)

Symbol Parameter Standard mode I2C Fast mode I2C

Cb Capacitive load for each bus line

Min

(2)

Max

400

(2)

Min

(2)

Max

Unit

(2)

400 pF

Notes:

(1)

f

(2)

Data based on standard I2C protocol requirement, not tested in production.

(3)

The maximum hold time of the start condition has only to be met if the interface does not stretch the low time.

(4)

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

, must be at least 8 MHz to achieve max fast I2C speed (400kHz).

MASTER

Figure 44: Typical application with I2C bus and timing diagram (1)

1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD

10.3.11 10-bi t ADC charact er istics

Subject to general operating conditions for V

Table 45: ADC characteristics

Symbol

f

ADC clock frequency V

ADC

V

Analog supply

DDA

V

Positive reference voltage

REF+

V

Negative reference voltage

REF-

Parameter Conditions Min Typ Max Unit

74/99 DocID14771 Rev 13

DDA

V

, f

DDA

, and TA unless otherwise specified.

MASTER

=2.95 to 5.5 V 1.0

=4.5 to 5.5 V 1.0

3.0

2.75

(1)

VSSA

4.0 MHz

6.0

5.5 V

V

DDA

0.5 V

STM8S105xx

Electrical characteristics

(1)

(2)

be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input.

Symbol

Parameter Conditions Min Typ Max Unit

V

Conversion voltage range

AIN

C

Internal sample and hold

ADC

(2)

Devices with external

V

REF+/VREF-

pins

VSSA

V

REF-

VDDA

V

REF+

V

3.0

capacitor

t

Sampling time f

S

t

Wakeup time from standby

STAB

t

Total conversion time (including

CONV

sampling time, 10-bit resolutio n)

= 4 MHz 0.75 µs

ADC

f

= 6 MHz 0.5

ADC

7.0

f

= 4 MHz 3.5 µs

ADC

f

= 6 MHz 2.33 µs

ADC

14 1/f

Notes:

(1)

Data guaranteed by design, not tested in production..

(2)

During the sample time the input capacitance C source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t

After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion

S.

result. Values for the sample clock t

depend on programming.

S

(3 pF max) can be charged/discharged by the external

AIN

Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V

Symbol Parameter Conditions Typ Max

|ET| Total unadjusted error

|EO| Offset error

|EG| Gain error

|ED| Differential linearity error

|EL| Integral linearity error

(2)

f

(2)

f

(2)

f

(2)

f

= 2 MHz 1.0 2.5 LSB

ADC

f

= 4 MHz 1.4 3.0

ADC

f

= 6 MHz 1.6 3.5

ADC

= 2 MHz 0.6 2.0

ADC

f

= 4 MHz 1.1 2.5

ADC

f

= 6 MHz 1.2 2.5

ADC

= 2 MHz 0.2 2.0

ADC

f

= 4 MHz 0.6 2.5

ADC

f

= 6 MHz 0.8 2.5

ADC

= 2 MHz 0.7 1.5

ADC

f

= 4 MHz 0.7 1.5

ADC

f

= 6 MHz 0.8 1.5

ADC

= 2 MHz 0.6 1.5

ADC

f

= 4 MHz 0.6 1.5

ADC

f

= 6 MHz 0.6 1.5

ADC

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should

(1)

Unit

pF

µs

ADC

DocID14771 Rev 13 75/99

Electrical characteristics

STM8S105xx

It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject

negative current. Any positive injection current within the limits specified for I pin characteristics section does not affect the ADC accuracy.

INJ(PIN)

and ΣI

INJ(PIN)

in the I/O port

Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V

Symbol Parameter Conditions Typ Max

|ET| Total unadjusted error

|EO| Offset error

|EG| Gain error

|ED| Differential linearity error

|EL| Integral linearity error

(2)

f

(2)

f

(2)

f

(2)

f

(2)

f

= 2 MHz 1.1 2.0 LSB

ADC

f

= 4 MHz 1.6 2.5

ADC

= 2 MHz 0.7 1.5

ADC

f

= 4 MHz 1.3 2.0

ADC

= 2 MHz 0.2 1.5

ADC

f

= 4 MHz 0.5 2.0

ADC

= 2 MHz 0.7 1.0

ADC

f

= 4 MHz 0.7 1.0

ADC

= 2 MHz 0.6 1.5

ADC

f

= 4 MHz 0.6 1.5

ADC

(1)

Unit

Notes:

(1)

Data based on characterization results, not tested in production.

(2)

ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I

13.3.6: "I/O port pin characteris tics"

does not affect the ADC accuracy.

INJ(PIN)

and ΣI

INJ(PIN)

in Section

Figure 45: ADC accuracy characteristics

1. Example of an actual transfer curve.

2. The ideal transfer curve

76/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

3. End point correlation line

= Total unadjusted error: maximum deviati on between the actual and the ideal

E

T

transfer curves.

= Offset error: deviation between the first actual tra nsition and the first ideal one.

E

O

= Gain error: deviation between the last ideal transition and the last actual one.

E

G

= Differential linearity error: maximum deviation between actual steps and the ideal

E

D

one.

= Integral linearity error: maximum deviation bet ween any actual transition and the

E

L

end point correlation line.

10.3.12 EMC charact er istics

Susceptibility tests are performed on a sample basi s during product characterization.

Figure 46: Typical application with ADC

10.3.12.1 Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

• FESD: Functional electrostatic discharge (positi ve and negative) is applied on all pins

of the device until a functional disturbance occ urs. This test conforms with the IEC 61000-4-2 standard.

• FTB: A burst of fast transient voltage (positive and ne gative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms to IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. Test results are given in table below based on the EMS levels and classes defined in application note AN1709 (EMC design guide for ST Microcontrollers).

10.3.12.2 Designing hardened software to avoid noise problems

EMC characterization and optimizatio n are performed at component level with a typical application environment and simplified MCU soft ware. It should be noted that good EMC performance is highly dependent on the user applicat ion and the software in particular.

Therefore it is recommended that the user applies E MC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

and VSS

DD

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

DocID14771 Rev 13 77/99

Electrical characteristics

STM8S105xx

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques for improving microcontr ol ler EMC performance).

Table 48: EMS data

Parameter Conditions Level/

Symbol

V

Voltage limits to be ap plied on any I/O

FESD

pin to induce a functional disturbance

V

Fast transient vol tage burst limits to be

EFTB

applied through 100 pF on V

DD

and V

pins to induce a functional distur bance

Notes:

(1)

Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers).

10.3.12.3 Electromagnetic interference (EMI)

Emission tests conform to the IEC61967-2 standa rd for test software, board layout and pin loading.

Table 49: EMI data

Symbol Parameter Conditions Unit

General conditions Monitored

S

Peak level V

EMI

LQFP48 package

SAE EMI

level

Notes:

(1)

Data based on characterization results, not tested in production.

= 5 V,

DD

TA = +25 °C,

conforming to

IEC61967-2

V

= 3.3 V, TA = 25 °C, f

DD

16 MHz (HSI clock), conforming to

IEC 61000-4-2

= 5 V, TA = 25 °C, f

V

DD

MHz, conforming to IEC 1000-4-2

VDD= 3.3 V, TA = 25 °C ,f

MHz (HSI clock),conforming to IEC

SS

61000-4-4

= 5 V, TA = 25 °C ,f

V

DD

MHz,conforming to IEC 1000-4-4

Max f

frequency band

8 MHz/

8 MHz

0.1 MHz to 30

13 14 dBµV

MHz

30 MHz to 130

23 19

MHz

130 MHz to 1

-4.0 -4.0

GHz

2.0 1.5 —

MASTER

HSE/fCPU

=

= 16

(1)

8 MHz/

16 MHz

class

2/B

4/A

(1)

78/99 DocID14771 Rev 13

STM8S105xx

Electrical characteristics

10.3.12.4 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performa nce in t erms of electrical sensitivity. For more details, refer to the application note AN11 81.

10.3.12.5 Electrostatic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 part s*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. F or more details, refer to the application note AN1181.

Table 50: ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum

V

ESD(HBM)

Electrostatic discharge

voltage (Human body model)

V

ESD(CDM)

Electrostatic discharge

voltage (Charge device

Notes:

(1)

Data based on characterization results, not tested in production

10.3.12.6 Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance:

• A supply overvoltage (applied to each power supply pin)

• A current injection (applied to each input, output and c onfigurable I/O pin) is performed

on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter Conditions Class

LU Static latch-up class TA = +25 °C A

Notes:

(1)

Class description: A Class is a STMicroelectronics internal specification. All limits are higher than JEDEC specifications, that means when a device belongs to class A it exceeds JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

model)

TA = +25°C, conforming

to JESD22-A114

TA=+25°C, conforming

to JESD22-C101

Table 51: Electrical sensitivities

TA = +85 °C A

TA = +125 °C A

Unit

value

(1)

A 2000 V

IV 1000 V

(1)

DocID14771 Rev 13 79/99

Package information

STM8S105xx

(1)

11 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product st atus are available at: www.st.com. ECOPACK

®

packages, depending on their level of en vironmental compliance. ECOPACK®

®

is an ST trademark.

11.1 48-pin LQFP package mechanical data

Figure 47: 48-pin low profile quad flat package (7 x 7)

Table 52: 48-pin low profile quad flat package mechanical data

Dim. mm inches

Min Typ Max Min Typ Max

A A1 0.050 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090

D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3

E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3

e

5.500

0.500

1.600

0.150 0.0020

0.200 0.0035

0.2165

0.0197

0.0630

0.0059

0.0079

80/99 DocID14771 Rev 13

STM8S105xx

Package information

(1)

Dim. mm inches

Min Typ Max Min Typ Max

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1

k 0° 3.5° 7.0° 0° 3.5° 7.0°

ccc

Notes:

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

1.000

0.080

11.2 44-pin LQFP package mechanical data

Figure 48: 44-pin low profile quad flat package

0.0394

0.0031

Table 53: 44-pin low profile quad flat package mechanical data

0.3150

(1)

0.0630

0.0059

0.0079

Dim. mm inches

Min Typ Max Min Typ Max

A A1 0.050 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090

D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D3

E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016

8.000

DocID14771 Rev 13 81/99

1.600

0.150 0.0020

0.200 0.0035

Package information

STM8S105xx

(1)

Dim. mm inches

Min Typ Max Min Typ Max

E3

e L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

ccc

Notes:

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

8.000

0.800

1.000

0.100

11.3 32-pin LQFP package mechanical data

Figure 49: 32-pin low profile quad flat package (7 x 7)

0.3150

0.0315

0.0394

0.0039

Table 54: 32-pin low profile quad flat package mechanical data

Dim. mm inches

Min Typ Max Min Typ Max

A A1 0.050 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.300 0.370 0.450 0.0118 0.0146 0.0177

c 0.090

D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3

5.600

1.600

0.150 0.0020

0.200 0.0035

82/99 DocID14771 Rev 13

0.0630

0.0059

0.0079

0.2205

STM8S105xx

Package information

(1)

Dim. mm inches

Min Typ Max Min Typ Max

E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3

e

L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1

k 0° 3.5° 7.0° 0° 3.5° 7.0°

ccc

Notes:

Values in inches are converted from mm and rounded to 4 decimal digits

(1)

5.600

0.800

1.000

0.2205

0.0315

0.0394

0.100

0.0039

DocID14771 Rev 13 83/99

Package information

STM8S105xx

11.4 32-lead UFQFPN package mechanical data

Figure 50: 32-lead, ultra-thin, fine pitch quad flat no-lead package (5 x 5)

1. Drawing is not to scale.

2. All leads/pads should be soldered to the PCB t o i m prov e the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground.

4. Dimensions are in millimeters.

Table 55: 32-lead ultra-thin fine pitch quad flat no-lead package mechanical data

Dim. mm inches

Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0 0.020 0.050 A3

b 0.180 0.250 0.300 0.0071 0.0098 0.0118

D 4.900 5.000 5.100 0.1909 0.1969 0.2028 D2 3.200 3.450 3.700 0.1260

E 4.900 5.000 5.100 0.1909 0.1969 0.2028

0.200

84/99 DocID14771 Rev 13

(1)

0.0008 0.0020

0.0079

0.1457

STM8S105xx

Package information

(1)

Dim. mm inches

Min Typ Max Min Typ Max

E2 3.200 3.450 3.700 0.1260 0.1358 0.1457

e

0.500

L 0.300 0.400 0.500 0.0118 0.0157 0.0197

ddd

0.080

Notes:

(1)

Values in inches are converted from mm and rounded to 4 decimal digits.

11.5 SDIP32 package mechanical data

Figure 51: 32-lead shrink plastic DIP (400 ml) packag e

0.0197

0.0031

DocID14771 Rev 13 85/99

Package information

STM8S105xx

Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data

Dim. mm inches

Min Typ Max Min Typ Max

A 3.556 3.759 5.080 0.1400 0.1480 0.2000 A1 0.508 A2 3.048 3.556 4.572 0.1200 0.1400 0.1800

B 0.356 0.457 0.584 0.0140 0.0180 0.0230 B1 0.762 1.016 1.397 0.0300 0.0400 0.0550

C 0.203 0.254 0.356 0.0079 0.0100 0.0140

D 27.430 27.940 28.450 1.0799 1.1000 1.1201

E 9.906 10.410 11.050 0.3900 0.4098 0.4350 E1 7.620 8.890 9.398 0.3000 0.3500 0.3700

e eA eB

L 2.540 3.048 3.810 0.1000 0.1200 0.1500

Notes:

(1)

Values in inches are converted from mm and rounded to 4 decimal digits

1.778

10.160

12.700

0.0200

0.0700

0.4000

(1)

0.5000

86/99 DocID14771 Rev 13

STM8S105xx

Thermal characteristics

12 Thermal characteristics

The maximum chip junction temperature (T

) must never exceed the values given in

Jmax

Section 7.10: "TIM1 - 16-bit advanced control timer"

The maximum chip-junction temperature, T

, in degrees Celsius, may be calculated

Jmax

using the following equation: T

Jmax

= T

Amax

+ (P

Dmax

x ΘJA)

Where:

• T

• Θ

• P

is the maximum ambient temperature in °C

Amax

is the package junction-to-ambient thermal resistanc e in ° C/ W

JA

is the sum of P

Dmax

is the product of I

INTmax

and P

INTmax

DD

I/Omax (PDmax

andVDD, expressed in Watts. This is the maximum chip

= P

INTmax

+ P

I/Omax

)

internal power.

• P

represents the maximum power dissipation on output pi nsWhere:P

I/Omax

(V

OL*IOL

) + Σ((V

DD-VOH)*IOH

), taking into account the actual VOL/I

I/Omax

OL and VOH/IOH

of the I/Os

at low and high level in the application.

Table 57: Thermal characteristics (1)

Symbol Parameter Value Unit

Θ

Thermal resistance junction-ambient

JA

57 °C/W

LQFP 48 - 7 x 7 mm

Θ

Thermal resistance junction-ambient

JA

54 °C/W

LQFP 44 - 10 x 10 mm

Θ

Thermal resistance junction-ambient

JA

60 °C/W

LQFP 32 - 7 x 7 mm

Θ

Thermal resistance junction-ambient

JA

38 °C/W

UFQFPN 32 - 5 x 5 mm

Θ

Thermal resistance junction-ambient

JA

60 °C/W

SDIP 32 - 400 mils

=Σ

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

12.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.

12.2 Selecting the product temperature range

When ordering the microcontroller, the tem perature range is specified in the order code. The following example shows how to calculate the t emperature range needed for a given

application. Assuming the following application conditions:

• Maximum ambient temperature T

• I

= 15 mA, VDD = 5.5 V

DDmax

DocID14771 Rev 13 87/99

= 82 °C (measured according to JESD51-2)

Amax

Thermal characteristics

STM8S105xx

• Maximum 8 standard I/Os used at the same time in output at low level with IOL = 10 mA, V

• Maximum 4 high sink I/Os used at the same time in output at low level with I mA, V

= 2 V

OL

= 1.5 V

OL

= 20

OL

• Maximum 2 true open drain I/Os used at the same time in output at low level with I 20 mA, V P

INTmax

P

IOmax

This gives: P P

Dmax

Thus: P for LQFP32 can be calculated as follows, using the thermal resistance ΘJA :

T

Jmax

= 82° C + (60° C/W x 443 mW) = 82°C + 27°C = 109° C

T

Jmax

This is within the range of the suffix 3 version parts (-40 < T

= 2 V

OL

= 15 mA x 5.5 V = 82.5 mW

= (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW

= 82.5 mW and P

INTmax

360 mW:

IOmax

= 82.5 mW + 360 mW

= 443 mW

Dmax

< 131° C). In this case, parts

J

must be ordered at least with the temperature range suffix 3.

OL

=

88/99 DocID14771 Rev 13

STM8S105xx

Ordering information

13 Ordering information

Figure 52: STM8S105xx access line ordering info rm at ion scheme

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of t hi s dev i ce, please go to www.st.com or contact the ST sales office nearest to you.

DocID14771 Rev 13 89/99

STM8S105 FASTROM microcontroller option list

STM8S105xx

See the option byte section in the datasheet for authorized option byte

14 STM8S105 FASTROM microcontroller option list

(last update: September 2010)

Customer

Address

Contact

Phone no.

Reference FASTROM code

Notes:

(1)

FASTROM code name is assigned by STMicroelectronics.

(1)

Preferable format for programing code is .Hex (.s19 is accepted) If data EEPROM programing is required, a separate file must be sent with the requested

data.

combinations and a detailed explanation.

...............................................................................................................

Device type/memory size/package (check only one option)

FASTROM device 16 Kbyte 32 K byte

LQFP32 [ ] STM8S105K4 [ ] STM8S105K6 LQFP44 [ ] STM8S105S4 [ ] STM8S105S6 LQFP48 [ ] STM8S105C4 [ ] STM8S105C6

Conditioning (check only one option)

[ ] Tape & reel or [ ] Tray

Special marking (check only one option)

[ ] No [ ] Yes Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character

counts are: LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" LQFP44: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" LQFP48: 2 lines of 8 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"

Temperature range

[ ] -40°C to +85°C or [ ] -40°C to +125°C

90/99 DocID14771 Rev 13

STM8S105xx

STM8S105 FASTROM microcontroller option

list

Padding value for unused program memory (check only one option)

[ ] 0xFF Fixed value

[ ] 0x83 TRA P ins truction opcode [ ] 0x75 Illegal opcode (causes a reset when executed)

OPT0 memory readout protection (check only one option)

[ ] Disable or [ ] Enable

OPT1 user boot code area (UBC)

0x(_ _) fill in the hexadecimal value, referring to t he datasheet and the binary format below.

UBC, bit0 [ ] 0: Reset

[ ] 1: Set

UBC bit1 [ ] 0: Reset

[ ] 1: Set

UBC bit2 [ ] 0: Reset

[ ] 1: Set

UBC bit3 [ ] 0: Reset

[ ] 1: Set

UBC bit4 [ ] 0: Reset

[ ] 1: Set

UBC bit5 [ ] 0: Reset

[ ] 1: Set

OPT2 alternate function remapping

AFR0

(check only one option)

AFR1

(check only one option)

AFR2

(check only one option)

AFR3

(check only one option)

[ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description.

[ ] 1: Port D3 alternate function = ADC_E TR [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout

description. [ ] 1: Port A3 alternate function = T IM3_CH1, port D2 alternate function =

TIM2_CH3. [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout

description. [ ] 1: Port D0 alternate function = CLK_CCO.

If both AFR2 and AFR3 are activated, AFR 2 option has priority over AFR3.

[ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description.

[ ] 1: Port D0 alternate function = TIM1_BKIN.

DocID14771 Rev 13 91/99

STM8S105 FASTROM microcontroller option list

STM8S105xx

AFR4 (check only

one option) AFR5

(check only one option)

AFR6 (check only

one option) AFR7

(check only one option)

[ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description.

[ ] 1: Port D7 alternate function = TIM1_CH4. [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout

description. [ ] 1: Port B3 alternate function = T IM1_ETR, port B2 alternate function =

TIM1_NCC3, port B1 alternate functi on = TIM1_CH2N, port B0 alternate function = TIM1_CH1N.

[ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout description

[ ] 1: Port B5 alternate function = I 2C_SDA, port B4 alternate function = I2C_S CL. [ ] 0: Remapping option inactive. Default alternate functions used. Refer to pinout

description. [ ] 1: Port D4 alternate function = BEEP.

OPT3 watchdog

WWDG_HALT

(check only one option)

WWDG_HW

(check only one option)

IWDG_HW

(check only one option)

LSI_EN

(check only one option)

HSITRIM

(check only one option)

OPT4 wakeup

PRSC

(check only one option)

CKAWUSEL

(check only one option)

EXTCLK

(check only one option)

[ ] 0: No reset generated on halt if WWDG active. [ ] 1: Reset generated on halt if WWDG active.

[ ] 0: WWDG activated by software. [ ] 1: WWDG activated by hardware.

[ ] 0: IWDG activated by software. [ ] 1: IWDG activated by hardware.

[ ] 0: LSI clock is not available as CPU cloc k source. [ ] 1: LSI clock is available as CPU clock source.

[ ] 0: 3-bit trimming supported in CLK_HSITRIMR regis ter. [ ] 1: 4-bit trimming supported in CLK_HSITRIMR regis ter.

[ ] for 16 MHz to 128 kHz prescaler. [ ] for 8 MHz to 128 kHz prescaler. [ ] for 4 MHz to 128 kHz prescaler.

[ ] 0: LSI clock source selected for AWU. [ ] 1: HSE clock with prescaler selected as clock source for AWU.

[ ] 0: External crystal connected to OSCIN/OSCOUT. [ ] 1: External clock signal on OSCIN.

OPT5 crystal oscillator stabilization HSECNT (check only one option)

[ ] 2048 HSE cycles [ ] 128 HSE cycles [ ] 8 HSE cycles [ ] 0.5 HSE cycles

92/99 DocID14771 Rev 13

STM8S105xx

STM8S105 FASTROM microcontroller option

list

OPT6 is reserved OPT7 is reserved OPTBL bootloader option byte (check only one option)

Refer to the UM0560 (STM8L/S bootloader manual) for more details. [ ] Disable (00h) [ ] Enable (55h)

Comments: ...........................................................................................

Supply operating range in the appl ication ...........................................................................................

Notes: ...........................................................................................

Date: ...........................................................................................

Signature: ...........................................................................................

DocID14771 Rev 13 93/99

STM8 development tools

STM8S105xx

15 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

15.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versati l ity and cost-effectiveness. In addition, STM8 application development is supported by a lo w -cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microco ntroller.

For improved cost effectiveness, STice is based o n a m odul ar design that allows you to order exactly what you need to meet your developm ent requirements and to adapt your emulation system to support existing and future ST microcontrollers.

STice key features

• Occurrence and time profiling and code coverage (ne w f eatures)

• Advanced breakpoints with up to 4 levels of condition s

• Data breakpoints

• Program and data trace recording up to 128 KB records

• Read/write on the fly of memory during emulation

• In-circuit debugging/programming via SWIM protocol

• 8-bit probe analyzer

• 1 input and 2 output triggers

• Power supply follower managing application v oltages between 1.62 to 5.5 V

• Modularity that allows you to specify the components y ou need to meet your

development requirements and adapt to future requirements

• Supported by free software tools that include integrat ed development environment (IDE), programming software interface and a ss em bler for STM8.

15.2 Software tools

STM8 development tools are supported by a complet e, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code.

15.2.1 STM8 toolset

94/99 DocID14771 Rev 13

STM8 toolset with STVD integrated development envi ronment and STVP programming software is available for free download at www.st.com/mcu. This package includes:

STM8S105xx

STM8 development tools

ST Visual Develop – Full-featured integrated development environment from ST, featuring

• Seamless integration of C and ASM toolsets

• Full-featured debugger

• Project management

• Syntax highlighting editor

• Integrated programming interface

• Support of advanced emulation features for STice suc h as code profiling and

coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

15.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to conf igure and control the building of your application directly from an easy-to-use graphical inte rface.

Available toolchains include:

• Cosmic C compiler for STM8 – Available in a free version that output s up to 16 Kbytes of code. For more information, see www. cosmic-software.com.

• Raisonance C compiler for STM8 – Available in a free version that output s up to 16 Kbytes of code. For more information, see www. raisonance.com.

• STM8 assembler linker – Free assembly toolchain in cluded in the STVD toolset, which allows you to assemble and link your application source code.

15.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

DocID14771 Rev 13 95/99

Revision history

STM8S105xx

Section 14: "Package information": Updated Table 57: "Thermal

16 Revision history

Date Revision Changes

05-Jun-

2008

23-Jun-

2008

12-Aug-

2008

17-Sep-

2008

05-Feb-

2009

27-Feb-

2009

12-May-

2009

1 Initial release.

2 Corrected number of high sink outputs to 9 in I/Os on Section 3: "Features".

Updated part numbers in Table 2: "STM8S105xx access line features".

3 Updated part numbers in Table 2: "STM8S105xx access line features".

USART renamed UART1, LINUART renamed UART2. Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access line

devices.

4 Removed STM8S102xx and STM8S104xx root part numbers corresponding

to devices without data EEPROM. Updated STM8S103 pinout in Section 5.2 on page 29. Added low and medium density Flash mem ory categories. Added Note 1 in Table 17: "Current characteristics". Updated Table 12: "Option bytes " .

5 Updated STM8S103 pinout in Section 5.2 on page 29

Updated number of High Sink I/O s in pinout. TSSOP20 pinout modified (PD4 moved to pin 1 etc.) Added WFQFN20 package Updated Section 11: "Option bytes". Added Section 4: "Introduction " .

6 Removed STM8S103x products (separate STM8S103 datasheet created)

Updated Section 4: "Introduction".

7 Added SDIP32 silhouette and package to Section 3: "Features" and Section

14.5: "SDIP32 package mechanical data" ; updated Section 8: "Pinout and pin description".

Updated VDD range (2.95 V to 5.5 V) on Section 3: "Features". Amended name of package VQFPN32 Added Table 5 on page 22 . Updated Section 7.8: "Auto wakeup counter". Updated pins 25, 30, and 31 in Section 8: "Pinout and pin description". Removed Table 7: Pin-to-pin comparison of pi n 7 to 12 in 32-pin access line

devices. Added Table 14: "Description of alternate function remapping bits [7:0] of

OPT2". Section 4: "Introduction": Updated VCAP specifications; updated Table 15,

Table 18, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, Table 27, Table 29, Table 35, and Table 42; added current consumption curves ; removed Figure 20: typical HSE frequency vs fcpu @ 4 temperatures; updated Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17 ; modified HSI accuracy in Table 33 ; added Figure 44 ; modified fSCK, tV(SO) and tV(MO) in Table 42 ; updated figures and tables of High speed internal RC oscillator (HSI) ; repl ac ed Figure 23, Figure 24, Figure 26, and Figure 39 .

Table 58: Document revision history

96/99 DocID14771 Rev 13

STM8S105xx

Revision history

characteristics(1)" and removed Table 57: Junction temperature range.

CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR, UART 2_DR, and ADC_DRx

Date Revision Changes

Updated Figure 52: "STM8S105xx acces s line ordering information scheme".

10-Jun-

2009

8 Document status changed from “preliminary data” to “datasheet”.

Standardized name of the VFQFPN package. Removed ‘wpu’ from I2C pins in Section 8: "Pinout and pin description"

21-Apr-

2010

9 Added UFQFPN32 package silhouette to the title page.

Section 3: "Features": added unique ID. Section 7.4: "Flash program and data EEPROM memory": updated bit

positions for TIM2 and TIM3.

Section 7.9: "Beeper": added infor mation about availability of the beeper

output port through option bit AFR7.

Section 7.13: "Analog-to-digital converter (ADC1)": added a note concerning

additional AIN12 analog input.

Section 8.1: "STM8S105 pinouts and pin description": added UFQFPN32

package details; updated default alternate function of PB2/AIN2[ TIM1_CH3N] pin in the "Pin description for STM8S105 microcontrollers" table.

Section 11: "Option bytes": added desc ription of STM8L bootloader option

bytes to the option byte description table. Added Section 4: "Introduction "

Section 7.10: "TIM1 - 16-bit advanced control timer": added introductory text;

removed low power dissipation cond i tion for T and added ESR and ESL data in table "general operating conditions".

Section 13.3.2.4: "Total curren t consumption in halt mode": replaced m ax

value of I powerdown mode, HSI clock after wakeup in the table "total current consumption in halt mode at VDD = 5 V.

Section 13.3.2.5: "Low power mode wakeup times": added first condition (0 to

16 MHz) for the t

Section 13.3.4: "Internal clock s ources and timing characteristics ": In the table

"HSI oscillator characteristics", replaced min and max values of "ACC factory calibrated parameter" and removed footnote 4 concerning fur ther characterization of results.

Section 13.3.12.1: "Functiona l E MS (electromagnetic susceptibili ty)": IEC

1000 replaced with IEC 61000.

Section 13.3.12.2: "Designing hardened software to avoid noise problems":

IEC 1000 replaced with IEC 61000.

Section 13.3.12.3: "Electromagnetic interference (EMI)": SAE J 1752/3

replaced with IEC61967-2.

Section 7.7: "Watchdog timers": Replac ed the thermal resistance junctio n

ambient temperature of LQFP32 7X7 mm f rom 59 °C to 60 °C in the thermal characteristics table.

Added Section 6: "Block diagram". Added Section 17: "STM8S105 FASTROM microcontroller option list".

21-Sep-

2010

10 Table 5: "Legend/abbreviations for pinout tables ": updated "reset state";

removed "HS", (T), and "[ ]".

Table 6: "Pin description for STM 8S 105 microcontrollers": added footnotes to

the PF4 and PD1 pins.

Table 8: "I/O port hardware register map": changed reset status of Px_IDR

from 0x00 to 0xXX.

Table 9: "General hardware register map"

state values; updated the reset st ate values of the RST_SR, CLK_SWCR,

, replaced "C

A

at 85 °C from 20 µA to 25 µA for the condition "Flash in

DD(H)

parameter in the table "wakeup tim es " .

WU(WFI)

: Standardized all address and reset

" by "VCAP",

EXT

HSI

DocID14771 Rev 13 97/99

Revision history

STM8S105xx

registers; replaced reserved addr es s "0x00 5248" with the UART2_CR5.

Date Revision Changes

Figure 40: "Recommended reset pin prot ection": replaced 0.01 µF with 0.1 µF

Updated Figure 44: "Typical application with I2C bus and timing diagram (1)". Updated footnote 1 in Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA=

5V and Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA=3.3V. Section 17: "STM8S105 FASTROM micr ocontroller option list": remov ed bits

6 and 7 from OPT1 user boot code area (UBC); added "disable" to 00h and "enable" to 55h of OPTBL bootloader option byte.

VFQFPN Package Mechanical datas : replaced note 1 and added note 2.

04-Apr-

2012

11 Removed VFQFPN32 package.

Modified Section 5: "Descripti on". Remove weak pull-up input for PE1 and PE2 in T able 6: "Pin description for

STM8S105 microcontrollers"

Updated Table 11: "Interrupt mapp ing" for TIM2 and TIM4. Updated notes related to V Added values of tR/tF for 50 pF load capacitance, and updated note i n Table

38: "I/O static characteristics".

Updated typical and maximum values of R

characteristics" and Table 42: "NRST pin character i s tics".

Changed SCK input to SCK output in Sec tion 13.3.9: "SPI serial peripheral

interface"

Added Θ

characteristics(1)", and updated Section 7.9: "Beeper"

28-Jun-

2012

7-Feb-

2014

12 Added UFQFPN package thickness in Figure 52: "STM8S105xx access line

ordering information scheme".

13 UART2_CK mapped to correct pin (pin 24) in Figure 4: "LQFP 44-pin pinout".

Reserved area updated in Table 12: " Option bytes ". Package Information updated in Table 55: "32-lead ultra-thin fine pi tch quad

flat no-lead package mechanical dat a".

in Table 19: "General operating condi tions".

CAP

in Table 38: "I/O static

PU

for UFQFPN32 and SDIP32 in Table 57: "T hermal

JA

98/99 DocID14771 Rev 13

STM8S105xx

Disclaimer

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DocID14771 Rev 13 99/99

ST MICROELECTRONICS STM8 S105C6T6TR Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

2 Description

3 Block diagram

4 Product overview

4.1 Single wire interface module (SWIM) a nd debug module (DM)

4.2 Interrupt controller

4.3 Flash program and data EEPROM memory

4.4 Clock controller

4.5 Power management

4.6 Watchdog timers

4.7 Auto wakeup counter

4.8 Beeper

4.9 TIM1 - 16-bit advanced control timer

4.10 TIM2, TIM3 - 16-bit general purpose timers

4.11 TIM4 - 8-bit basic timer

4.12 Analog-to-digital converter (ADC1)

4.13 Communication interfaces

4.13.1 UART2

4.13.2 SPI

4.13.3 I²C

5 Pinout and pin description

5.1 STM8S105 pinouts and pin descripti on

5.1.1 Alternate function remapping

6 Memory and register map

6.1 Memory map

6.2 Register map

6.2.1 I/O port hardware register map

6.2.2 General hardware register map

6.2.3 CPU/SWIM/debug module/interrupt controller registers

7 Interrupt vector mapping

8 Option bytes

9 Unique ID

10 Electrical characteristics

10.1 Parameter conditions

10.1.1 Minimum and maximum values

10.1.2 Typical values

10.1.3 Typical curves

10.1.4 Typical current consumption

10.1.5 Loading capacitor

10.1.6 Pin input voltage

10.2 Absolute maximum ratings

10.3 Operating conditions

10.3.1 VCAP external capacitor

10.3.2 Supply current characteristics

10.3.2.1 Total current consumption in run mode

10.3.2.2 Total current consumption in wait mode

10.3.2.3 Total current consumption in active halt mode

10.3.2.4 Total current consumption in halt mode

10.3.2.5 Low power mode wakeup times

10.3.2.6 Total current consumption and timing in forced reset state

10.3.2.7 Current consumption of on-chip peripherals

10.3.2.8 Current consumption curves

10.3.3 External clock sources and timing characteristics

10.3.4 Internal clock sources and timing characteristics

10.3.5 Memory characteristics

10.3.6 I/O port pin characteristics

10.3.7 Typical output level curves

10.3.8 Reset pin characteristics

10.3.9 SPI serial peripheral interface

10.3.10 I2C i nt er face characteristics

10.3.11 10-bi t ADC charact er istics

10.3.12 EMC charact er istics

10.3.12.1 Functional EMS (electromagnetic susceptibility)

10.3.12.2 Designing hardened software to avoid noise problems

10.3.12.3 Electromagnetic interference (EMI)

10.3.12.4 Absolute maximum ratings (electrical sensitivity)

10.3.12.5 Electrostatic discharge (ESD)

10.3.12.6 Static latch-up

11 Package information

11.1 48-pin LQFP package mechanical data

11.2 44-pin LQFP package mechanical data

11.3 32-pin LQFP package mechanical data

11.4 32-lead UFQFPN package mechanical data

11.5 SDIP32 package mechanical data

12 Thermal characteristics

12.1 Reference document