Figure 52: STM8S105xx access line ordering information scheme ......................................................... 89
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Introduction
STM8S105xx
1 Introduction
This datasheet contains the description of the device features, pinout, electrical
characteristics, mechanical data and ordering information.
•For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcont roller family reference manual
(RM0016).
•For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manu al (P M 0051).
•For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug mo dul e user manual (UM0470).
•For information on the STM8 core, please refer to the S T M 8 CP U programming
manual (PM0044).
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Description
2 Description
The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash
program memory, plus integrated true data EE PROM. They are referred to as mediumdensity devices in the STM8S microcontroller family reference manual (RM0016).
All devices of the STM8S105xx access line provide t he f ol l owing benefits: reduced system
cost, performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by a 16 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, indepe ndent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to ap plication scalability across common
family product architecture with compatible pinout , memory map and modular peripherals.
Full documentation is offered with a wide choi ce of development tools.
Product longevity is ensured in the STM8S family t hanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
Advanced control t i me r (TI M1 ) , G en eral-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C,
48
38
35
9
3
10
16
16K
1024
2K
UART, Window WDG, Independent WDG, ADC
44
34
31
8
3
9
15
32K
1024
2K
44
34
31
8
3
9
15
16K
1024
2K
32
25
23
8
3
7
12
32K
1024
2K
32
25
23
8
3
7
12
16K
1024
2K
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Block diagram
STM8S105xx
3 Block diagram
Figure 1: STM8S105xx access line block diagram
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Product overview
4 Product overview
The following section intends to give an overview of the basic features of the device
functional modules and peripherals.
For more detailed information please refer to t he corresponding family reference manual
(RM0016).
Central processing unit STM8
The 8-bit STM8 core is designed for code efficien cy and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus - single cycle fetching for most instructions
• X and Y 16-bit index registers - enabling indexed addres sing m odes with or without
offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter - 16-Mbyte linear memory space
• 16-bit stack pointer - access to a 64 K-level stack
• 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for look-up table s located anywhere in the address
space
•Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction siz e
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
4.1 Single wire interface module (SWIM) a nd debug module
(DM)
The single wire interface module and debug module permi ts non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
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Product overview
STM8S105xx
Debug module
The non-intrusive debugging module features a pe rf ormance close to a full-featured
emulator. Beside memory and peripherals, also CPU operat i on can be monitored in realtime by means of shadow registers.
• R/W to RAM and peripheral registers in real-time
• R/W access to all resources by stalling the CPU
• Breakpoints on all program-memory instructions (software breakpoi nts)
• Two advanced breakpoints, 23 predefined configurati ons
4.2 Interrupt controller
• Nested interrupts with three software priority l evels
• 32 interrupt vectors with hardware priority
• Up to 37 external interrupts on 6 vectors including TLI
• Trap and reset interrupts
4.3 Flash program and data EEPROM memory
• Up to 32 Kbytes of Flash program single voltage Flash m em ory
• Up to 1 Kbytes true data EEPROM
• Read while write: Writing in data memory possible whil e executing code in program
memory
•User option byte area Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could re sult from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and prot ects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IA P), this write protection can be removed by
writing a MASS key sequence in a control register. T his all ows the application to write to
data EEPROM, modify the contents of main progr am memory or the device option bytes.
A second level of write protection, can be enabl ed to further protect a specific area of
memory known as UBC (user boot code). Refer to t he figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1
page (512 bytes) by programming the UBC option byte in I CP mode.
This divides the program memory into two areas:
• Main program memory: Up to 32 Kbytes minus UBC
• User-specific boot code (UBC): Configurable up to 32 Kbytes
The UBC area remains write-protected during in-appl i cat i on programming. This means that
the MASS keys do not unlock the UBC area. It protects the m emory used to store the boot
program, specific code libraries, reset and int errupt vectors, the reset routine and usually
the IAP and communication routines.
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Product overview
Figure 2: Flash memory organization
Read-out protection (ROP)
The read-out protection blocks reading and writing t he Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Onc e the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
4.4 Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clo ck gating for low power modes and
ensures clock robustness.
Features
•Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
•Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock sig nal is not switched until the new clock
source is ready. The design guarantees glitch-f ree switching.
•Clock management: To reduce power consumption, t he cloc k controller can stop the
clock to the core, individual peripherals or memory .
•Master clock sources: Four different clock sour ces can be used to drive the master
clock:
− 1-16 MHz high-speed external crystal (HSE)
− Up to 16 MHz high-speed user-external clock (HSE user-ext)
− 16 MHz high-speed internal RC oscillator (HSI)
− 128 kHz low-speed internal RC (LSI)
) coming from different oscillators
MASTER
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Product overview
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•Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock so urce can be changed by the
application program as soon as the code execution st art s.
•Clock security system (CSS): This feature can be e nabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is a ut om atically selected by the CSS
and an interrupt can optionally be generated.
•Configurable main clock output (CCO): This outputs an external clock for use by
the application.
Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between
lowest power consumption, fastest start-up time and available wakeup sources.
•Wait mode: In this mode, the CPU is stopped, but peripheral s are kept running. The
wakeup is performed by an internal or external interrupt or reset.
•Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at program mabl e i ntervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current
consumption is higher than in active halt mode with regulator off, but the wakeup time
is faster. Wakeup is triggered by the internal AW U interrupt, external interrupt or reset.
•Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up
time is slower.
•Halt mode :In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
Bit Peripheral
clock
SPI PCKEN25 Reserved PCKEN21 Reserved
I2C PCKEN24 Reserved PCKEN20 Reserved
Bit Peripheral
clock
4.6 Watchdog timers
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The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdo g behavior to match the application
perfectly.
STM8S105xx
Product overview
The application software must refresh the counter b efore time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed bef ore i t s value is lower than
the one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be us ed to resolve processor malfunctions due
to hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, an d thus stays active even in
case of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.7 Auto wakeup counter
• Used for auto wakeup from active halt mode
• Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
• LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
4.8 Beeper
The beeper function outputs a signal on the BEE P pin for so und generation. The signal is
in the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.9 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of cont rol applications. With its
complementary outputs, dead-time control and c enter-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
• 16-bit up, down and up/down autoreload counter with 16-bit prescaler
• Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
• Synchronization module to control the timer with external signals
• Break input to force the timer outputs into a defined state
• Three complementary outputs with adjustable dead ti m e
• Encoder mode
• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.10 TIM2, TIM3 - 16-bit general purpose timers
• 16-bit autoreload (AR) up-counter
• 15-bit prescaler adjustable to fixed power of 2 ratios 1… 32768
• Timers with 3 or 2 individually configurable capture/compare channels
• PWM mode
• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
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Product overview
STM8S105xx
Additional AIN12 analog input is not selectable in A DC scan mode or with analog
4.11 TIM4 - 8-bit basic timer
• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
• Clock source: CPU clock
• Interrupt source: 1 x overflow/update
Table 4: TIM timer features
Timer Counter
size
(bits)
TIM1 16 Any
TIM2 16 Any
TIM3 16 Any
TIM4 8 Any
Prescaler Counting
mode
Up/Down 4 3 Yes No
integer
from 1 to
65536
Up 3 0 No
power of 2
from 1 to
32768
Up 2 0 No
power of 2
from 1 to
32768
Up 0 0 No
power of 2
from 1 to
128
CAPCOM
channels
4.12 Analog-to-digital converter (ADC1)
The STM8S105xx products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 10 multiplexed input channels and the following main features:
Complem.
outputs
Ext.
trigger
Timer
synchronization/
chaining
• Input voltage range: 0 to V
• Input voltage range: 0 to V
DD
DDA
• Conversion time: 14 clock cycles
• Single and continuous and buffered continuous conver sion m odes
• Buffer size (n x 10 bits) where n = number of input channels
• Scan mode for single and continuous conversion of a sequence of channels
• Analog watchdog capability with programmable uppe r and l ower thresholds
• Analog watchdog interrupt
• External trigger input
• Trigger from TIM1 TRGO
• End of conversion (EOC) interrupt
watchdog. Values converted from AIN12 are stored only into the
ADC_DRH/ADC_DRL registers.
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Product overview
4.13 Communication interfaces
The following communication interfaces are implem ented:
As shown in the rightmost column of the pin descripti on table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is act i ve, the default alternate function is no
longer available.
To use an alternate function, the corresponding peri pheral must be enabled in the
peripheral registers.
Alternate function remapping does not aff ect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0 016).
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Memory and register map
6 Memory and register map
6.1 Memory map
Figure 7: Memory map
The following table lists the boundary addresses for each memory size. The top of the
stack is at the RAM end address in each case.
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Memory and register map
STM8S105xx
Table 7: Flash, Data EEPROM and RAM boundary addresses
Memory area Size (bytes) Start address End address
Flash program memory 32K 0x00 8000 0x00 FFFF
RAM 2K 0x00 0000 0x00 07FF
Data EEPROM 1024 0x00 4000 0x00 43FF
6.2 Register map
6.2.1 I/O port hardware register map
Table 8: I/O port hardware register map
Address Block Register label Register name Reset status
0x00 5000 Port A PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR P ort A input pin value register 0xXX
0x00 5002 PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 Port B PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR P ort B input pin value register 0xXX
0x00 5007 PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A Port C PC_ODR Port C data output latch register 0x00
0x00 500B PC_IDR Port C input pin value register 0xXX
0x00 500C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F Port D PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 PD_DDR Port D data direction re gister 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014 Port E PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR P ort E input pin value register 0xXX
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019 Port F PF_ODR Port F data output latch register 0x00
16K 0x00 8000 0x00 BFFF
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Memory and register map
Address Block Register label Register name Reset status
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B PF_DDR Port F data direction re gister 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
0x00 501E Port G PG_ODR Port G data output latch register 0x00
0x00 501F PG_IDR Port G input pin value register 0xXX
0x00 5020 PG_DDR Port G data direction register 0x00
0x00 5021 PG_CR1 Port G control register 1 0x00
0x00 5022 PG_CR2 Port G control register 2 0x00
0x00 5023 Port H PH_ODR Port H data output latch regis ter 0x00
0x00 5024 PH_IDR Port H input pin value register 0xXX
0x00 5025 PH_DDR Port H data direction re gister 0x00
0x00 5026 PH_CR1 Port H control register 1 0x00
0x00 5027 PH_CR2 Port H control register 2 0x00
0x00 5028 Port I PI_ODR Port I data output latch register 0x00
0x00 5029 PI_IDR Port I input pin value register 0xXX
0x00 502A PI_DDR Port I data direction register 0x00
0x00 502B PI_CR1 Port I control register 1 0x00
0x00 502C PI_CR2 Port I control register 2 0x00
6.2.2 General hardware register map
Table 9: General hardware register m ap
Address Block Register label Register name Reset
0x00 5050 to
0x00 5059
0x00 505A Flash FLASH_CR1 Flash control r egister 1 0x00
0x00 505B FLASH_CR2 Flash control register 2 0x00
0x00 505C FLASH_NCR2 Flash complementary control