STM8S105xx
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
Datasheet - production data
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
Features
Core
• 16 MHz advanced STM8 core with Harvar d
architecture and 3-stage pipeline
• Extended instruction set
Memories
• Medium-density Flash/EEPROM :
− Program memory up to 32 Kbytes; data
retention 20 years at 55°C after 10 kcycles
− Data memory up to 1 Kbytes true data
EEPROM; endurance 300 kcycles
• RAM: Up to 2 Kbytes
Timers
• 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
• Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary output s , dead-time
insertion and flexible synchronization
• 8-bit basic timer with 8-bit prescaler
• Auto wake-up timer
• Window and independent watchdog t i mers
Communications interfaces
• UART with clock output for synchronous
operation, Smartcard, IrDA, L IN
• SPI interface up to 8 Mbit/s
• I2C interface up to 400 Kbit/s
Analog-to-digital converter (ADC)
• 10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
I/Os
• Up to 38 I/Os on a 48-pin package including 16
high sink outputs
• Highly robust I/O design, immune against current
injection
Clock, reset and supply management
• 2.95 V to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources:
− Low power crystal resonator oscill ator
− External clock input
− Internal, user-trimmable 16 MHz RC
− Internal low power 128 kHz RC
• Clock security system with clock monitor
• Power management:
− Low power modes (wait, active-halt, halt)
− Switch-off peripheral clocks individually
• Permanently active, low consumption power-on
and power-down reset
Development support
• Embedded single wire interface module (SWIM)
for fast on-chip programming and non-intrusive
debugging
Unique ID
• 96-bit unique key for each device
Table 1: Device summary
Interrupt management
• Nested interrupt controller with 32 interrupts
• Up to 37 external interrupts on 6 vectors
Reference
STM8S105xx
STM8S105K4, STM8S105K6, STM8S105S4,
Part number
STM8S105S6, STM8S105C4, STM8S105C6
February 2014 DocID14771 Rev 13 1/99
This is information on a product in full production
www.st.com
Contents
STM8S105xx
Contents
1 Introduction ....................................................................................... 8
2 Description ........................................................................................ 9
3 Block diagram ................................................................................. 10
4 Product overview ............................................................................ 11
4.1 Single wire interf ac e module (SWIM) and debug module (DM) ....... 11
4.2 Interrupt controller ........................................................................... 12
4.3 Flash program and data EEPROM memory .................................... 12
4.4 Clock controller ............................................................................... 13
4.5 Power management ........................................................................ 14
4.6 Watchdog timers ............................................................................. 14
4.7 Auto wakeup counter ...................................................................... 15
4.8 Beeper ............................................................................................ 15
4.9 TIM1 - 16-bit advanced control timer ............................................... 15
4.10 TIM2, TIM3 - 16-bit general purpose timers .................................... 15
4.11 TIM4 - 8-bit basic timer ................................................................... 16
4.12 Analog-to-digital converter (ADC1) ................................................. 16
4.13 Communication interfaces ............................................................... 17
4.13.1 UART2 .............................................................................................. 17
4.13.2 SPI .................................................................................................... 17
4.13.3 I²C ..................................................................................................... 18
5 Pinout and pin description ............................................................ 19
5.1 STM8S105 pinouts and pin description ........................................... 19
5.1.1 Alternate function remapping ........................................................... 24
6 Memory and register map .............................................................. 25
6.1 Memory map ................................................................................... 25
6.2 Register map ................................................................................... 26
6.2.1 I/O port hardware register map ........................................................ 26
6.2.2 General hardware register map ........................................................ 27
6.2.3 CPU/SWIM/debug module/interrupt controlle r registers .................. 34
7 Interrupt vector mapping ............................................................... 36
8 Option bytes .................................................................................... 37
9 Unique ID ......................................................................................... 41
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Contents
10 Electrical characteristics ............................................................... 42
10.1 Parameter conditions ...................................................................... 42
10.1.1 Minimum and maximum values ........................................................ 42
10.1.2 Typical values ................................................................................... 42
10.1.3 Typical curves ................................................................................... 42
10.1.4 Typical current consumption ............................................................ 42
10.1.5 Loading capacitor ............................................................................. 43
10.1.6 Pin input voltage ............................................................................... 43
10.2 Absolute maximum ratings .............................................................. 43
10.3 Operating conditions ....................................................................... 45
10.3.1 VCAP external capacitor .................................................................. 46
10.3.2 Supply current characteristics .......................................................... 47
10.3.3 External clock sources and timing characteristics ............................ 56
10.3.4 Internal clock sources and timing characteristics ............................. 58
10.3.5 Memory characteristics ..................................................................... 60
10.3.6 I/O port pin characteristics ................................................................ 61
10.3.7 Typical output level curves ............................................................... 64
10.3.8 Reset pin characteristics .................................................................. 68
10.3.9 SPI serial peripheral interface .......................................................... 70
10.3.10 I2C interface characteristics ............................................................. 73
10.3.11 10-bit ADC characteristics ................................................................ 74
10.3.12 EMC characteristics .......................................................................... 77
11 Package information ...................................................................... 80
11.1 48-pin LQFP package mechanical data .......................................... 80
11.2 44-pin LQFP package mechanical data .......................................... 81
11.3 32-pin LQFP package mechanical data .......................................... 82
11.4 32-lead UFQFPN package mechanical data ................................... 84
11.5 SDIP32 package mechanical data .................................................. 85
12 Thermal characteristics ................................................................. 87
12.1 Reference document ....................................................................... 87
12.2 Selecting the product temperature range ........................................ 87
13 Ordering information ...................................................................... 89
14 STM8S105 FASTROM microcontro ller option list ....................... 90
15 STM8 development tools ............................................................... 94
15.1 Emulation and in-circuit debugging tools ......................................... 94
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Contents
STM8S105xx
15.2 Software tools ................................................................................. 94
15.2.1 STM8 toolset .................................................................................... 94
15.2.2 C and assembly toolchains .............................................................. 95
15.3 Programming tools .......................................................................... 95
16 Revision history .............................................................................. 96
17 Disclaimer ....................................................................................... 99
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STM8S105xx
List of tables
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: STM8S105xx access line features ............................................................................................... 9
Table 3: Peripheral clock gating bit assignments in C LK_PCKENR1/2 registers .................................... 14
Table 4: TIM timer features ....................................................................................................................... 16
Table 5: Legend/abbreviations for pinout t ables ....................................................................................... 19
Table 6: Pin description for STM8S105 microcontrollers ......................................................................... 22
Table 7: Flash, Data EEPROM and RAM boundary addresses ............................................................... 26
Table 8: I/O port hardware register map ................................................................................................... 26
Table 9: General hardware register map .................................................................................................. 27
Table 10: CPU/SWIM/debug module/interrupt cont roller registers .......................................................... 34
Table 11: Interrupt mapping ...................................................................................................................... 36
Table 12: Option bytes .............................................................................................................................. 37
Table 13: Option byte description ............................................................................................................. 38
Table 14: Description of alternate function remapping bits [7:0] of OPT2 ................................................ 39
Table 15: Unique ID registers (96 bits) ..................................................................................................... 41
Table 16: Voltage characteristics .............................................................................................................. 43
Table 17: Current characteristics .............................................................................................................. 44
Table 18: Thermal characteristics ............................................................................................................. 45
Table 19: General operating conditions .................................................................................................... 45
Table 20: Operating conditions at power-up/power-down ........................................................................ 46
Table 21: Total current consumption with code execut ion in run mode at VDD = 5 V ............................. 47
Table 22: Total current consumption with code execut ion in run mode at VDD = 3.3 V .......................... 48
Table 23: Total current consumption in wait mode at VDD = 5 V ............................................................. 49
Table 24: Total current consumption in wait mode at V DD = 3.3 V .......................................................... 49
Table 25: Total current consumption in active halt m ode at VDD = 5 V ................................................... 50
Table 26: Total current consumption in active halt mode at VDD = 3.3 V ................................................ 51
Table 27: Total current consumption in halt mode at V DD = 5 V ............................................................. 51
Table 28: Total current consumption in halt mode at V DD = 3.3 V .......................................................... 52
Table 29: Wakeup times ........................................................................................................................... 52
Table 30: Total current consumption and timing in f orc ed reset state ...................................................... 53
Table 31: Peripheral current consumption ................................................................................................ 53
Table 32: HSE user external clock characteristic s ................................................................................... 56
Table 33: HSE oscillator characteristics ................................................................................................... 56
Table 34: HSI oscillator characteristics ..................................................................................................... 58
Table 35: LSI oscillator characteristics ..................................................................................................... 59
Table 36: RAM and hardware registers .................................................................................................... 60
Table 37: Flash program memory/data EEPROM memory ...................................................................... 60
Table 38: I/O static characteristics ............................................................................................................ 61
Table 39: Output driving current (standard ports) ..................................................................................... 63
Table 40: Output driving current (true open drain ports) .......................................................................... 63
Table 41: Output driving current (high sink ports) .................................................................................... 63
Table 42: NRST pin characteristics .......................................................................................................... 68
Table 43: SPI characteristics .................................................................................................................... 71
Table 44: I2C characteristics .................................................................................................................... 73
Table 45: ADC characteristics .................................................................................................................. 74
Table 46: ADC accuracy with RAIN < 10 kΩ , VDDA= 5 V ...................................................................... 75
Table 47: ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V .......................................................... 76
Table 48: EMS data .................................................................................................................................. 78
Table 49: EMI data .................................................................................................................................... 78
Table 50: ESD absolute maximum ratings ............................................................................................... 79
Table 51: Electrical sensitivities ................................................................................................................ 79
Table 52: 48-pin low profile quad flat package mechanical data .............................................................. 80
Table 53: 44-pin low profile quad flat package mechanical data .............................................................. 81
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List of tables
STM8S105xx
Table 54: 32-pin low profile quad flat package mechanical data .............................................................. 82
Table 55: 32-lead ultra thin fine pitch quad flat no-lead pac kage me chani cal dat a ................................. 84
Table 56: 32-lead shrink plastic DIP (400 ml) package mechanical data ................................................. 86
Table 57: Thermal characteristics (1) ....................................................................................................... 87
Table 58: Document revision history ........................................................................................................ 96
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STM8S105xx
List of figures
List of figures
Figure 1: STM8S105xx access line block diagram ................................................................................... 10
Figure 2: Flash memory organization ....................................................................................................... 13
Figure 3: LQFP 48-pin pinout ................................................................................................................... 19
Figure 4: LQFP 44-pin pinout ................................................................................................................... 20
Figure 5: LQFP/UFQFPN 32-pin pinout .................................................................................................... 21
Figure 6: SDIP 32-pin pinout .................................................................................................................... 21
Figure 7: Memory map .............................................................................................................................. 25
Figure 8: Supply current measurement conditions ................................................................................... 42
Figure 9: Pin loading conditions ................................................................................................................ 43
Figure 10: Pin input voltage ...................................................................................................................... 43
Figure 11: fCPUmax versus VDD ............................................................................................................. 46
Figure 12: External capacitor CEXT ......................................................................................................... 47
Figure 13: Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz ...................................... 54
Figure 14: Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD= 5 V .............................................. 54
Figure 15: Typ. IDD(RUN) vs. VDD, HSI RC osc, fCPU = 16 MHz .......................................................... 54
Figure 16: Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz ....................................... 55
Figure 17: Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ............................................... 55
Figure 18: Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ........................................................... 55
Figure 19: HSE external clocksource ....................................................................................................... 56
Figure 20: HSE oscillator circuit diagram.................................................................................................. 57
Figure 21: Typical HSI accuracy at VDD = 5 V vs 5 temper at ures ........................................................... 58
Figure 22: Typical HSI accuracy vs VDD @ 4 temperat ures ................................................................... 59
Figure 23: Typical LSI accuracy vs VDD @ 4 temperatures .................................................................... 59
Figure 24: Typical VIL and VIH vs VDD @ 4 temperatures ..................................................................... 62
Figure 25: Typical pull-up resistance vs VDD @ 4 t em peratures ............................................................. 62
Figure 26: Typical pull-up current vs VDD @ 4 temperatures .................................................................. 63
Figure 27: Typ. VOL @ VDD = 5 V (standard ports) ................................................................................ 64
Figure 28: Typ. VOL @ VDD = 3.3 V (standard ports) ............................................................................. 65
Figure 29: Typ. VOL @ VDD = 5 V (true open drain ports) ...................................................................... 65
Figure 30: Typ. VOL @ VDD = 3.3 V (true open drain ports) ................................................................... 66
Figure 31: Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................ 66
Figure 32: Typ. VOL @ VDD = 3.3 V (high sink ports) ............................................................................. 67
Figure 33: Typ. VDD - VOH @ VDD = 5 V (standard ports) ..................................................................... 67
Figure 34: Typ. VDD - VOH @ VDD = 3.3 V (standard ports) .................................................................. 67
Figure 35: Typ. VDD - VOH @ VDD = 5 V (high sink ports) .................................................................... 68
Figure 36: Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ................................................................. 68
Figure 37: Typical NRST VIL and VIH vs VDD @ 4 temperatures ........................................................... 69
Figure 38: Typical NRST pull-up resistance vs VDD @ 4 t em peratures .................................................. 69
Figure 39: Typical NRST pull-up current vs VDD @ 4 tem peratures ....................................................... 70
Figure 40: Recommended reset pin protection ........................................................................................ 70
Figure 41: SPI timing diagram - slave mode and CPH A = 0 .................................................................... 72
Figure 42: SPI timing diagram - slave mode and CPH A = 1(1) ................................................................ 72
Figure 43: SPI timing diagram - master mode(1) ..................................................................................... 73
Figure 44: Typical application with I2C bus and timing diagram (1) ......................................................... 74
Figure 45: ADC accuracy characteristics .................................................................................................. 76
Figure 46: Typical application with ADC ................................................................................................... 77
Figure 47: 48-pin low profile quad flat package (7 x 7) ............................................................................. 80
Figure 48: 44-pin low profile quad flat package ........................................................................................ 81
Figure 49: 32-pin low profile quad flat package (7 x 7) ............................................................................. 82
Figure 50: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) .............................................. 84
Figure 51: 32-lead shrink plastic DIP (400 ml) package ........................................................................... 85
Figure 52: STM8S105xx access line ordering information scheme ......................................................... 89
DocID14771 Rev 13 7/99
Introduction
STM8S105xx
1 Introduction
This datasheet contains the description of the device features, pinout, electrical
characteristics, mechanical data and ordering information.
• For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcont roller family reference manual
(RM0016).
• For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manu al (P M 0051).
• For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug mo dul e user manual (UM0470).
• For information on the STM8 core, please refer to the S T M 8 CP U programming
manual (PM0044).
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STM8S105xx
Description
2 Description
The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash
program memory, plus integrated true data EE PROM. They are referred to as mediumdensity devices in the STM8S microcontroller family reference manual (RM0016).
All devices of the STM8S105xx access line provide t he f ol l owing benefits: reduced system
cost, performance and robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by a 16 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, indepe ndent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to ap plication scalability across common
family product architecture with compatible pinout , memory map and modular peripherals.
Full documentation is offered with a wide choi ce of development tools.
Product longevity is ensured in the STM8S family t hanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
Table 2: STM8S105xx access line features
Device
Pin count
Maximum
number of GPIOs
Ext. Interrupt pins
Timer CAPCOM
channels
complementary
A/D Converter
channels
High sink I/Os
Medium density
Flash Program
memory (bytes)
Data EEPROM
RAM (bytes)
Peripheral set
Timer
outputs
(bytes)
STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4
48
38
35
9
3
10
16
32K
1024
2K
Advanced control t i me r (TI M1 ) , G en eral-purpose timers (TIM2 and TIM3), Basic timer (TIM4) SPI, I2C,
48
38
35
9
3
10
16
16K
1024
2K
UART, Window WDG, Independent WDG, ADC
44
34
31
8
3
9
15
32K
1024
2K
44
34
31
8
3
9
15
16K
1024
2K
32
25
23
8
3
7
12
32K
1024
2K
32
25
23
8
3
7
12
16K
1024
2K
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Block diagram
STM8S105xx
3 Block diagram
Figure 1: STM8S105xx access line block diagram
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STM8S105xx
Product overview
4 Product overview
The following section intends to give an overview of the basic features of the device
functional modules and peripherals.
For more detailed information please refer to t he corresponding family reference manual
(RM0016).
Central processing unit STM8
The 8-bit STM8 core is designed for code efficien cy and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus - single cycle fetching for most instructions
• X and Y 16-bit index registers - enabling indexed addres sing m odes with or without
offset and read-modify-write type data manipulations
• 8-bit accumulator
• 24-bit program counter - 16-Mbyte linear memory space
• 16-bit stack pointer - access to a 64 K-level stack
• 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
• 20 addressing modes
• Indexed indirect addressing mode for look-up table s located anywhere in the address
space
• Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction siz e
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
4.1 Single wire interface module (SWIM) a nd debug module (DM)
The single wire interface module and debug module permi ts non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
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Product overview
STM8S105xx
Debug module
The non-intrusive debugging module features a pe rf ormance close to a full-featured
emulator. Beside memory and peripherals, also CPU operat i on can be monitored in realtime by means of shadow registers.
• R/W to RAM and peripheral registers in real-time
• R/W access to all resources by stalling the CPU
• Breakpoints on all program-memory instructions (software breakpoi nts)
• Two advanced breakpoints, 23 predefined configurati ons
4.2 Interrupt controller
• Nested interrupts with three software priority l evels
• 32 interrupt vectors with hardware priority
• Up to 37 external interrupts on 6 vectors including TLI
• Trap and reset interrupts
4.3 Flash program and data EEPROM memory
• Up to 32 Kbytes of Flash program single voltage Flash m em ory
• Up to 1 Kbytes true data EEPROM
• Read while write: Writing in data memory possible whil e executing code in program
memory
• User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could re sult from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and prot ects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IA P), this write protection can be removed by
writing a MASS key sequence in a control register. T his all ows the application to write to
data EEPROM, modify the contents of main progr am memory or the device option bytes.
A second level of write protection, can be enabl ed to further protect a specific area of
memory known as UBC (user boot code). Refer to t he figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1
page (512 bytes) by programming the UBC option byte in I CP mode.
This divides the program memory into two areas:
• Main program memory: Up to 32 Kbytes minus UBC
• User-specific boot code (UBC): Configurable up to 32 Kbytes
The UBC area remains write-protected during in-appl i cat i on programming. This means that
the MASS keys do not unlock the UBC area. It protects the m emory used to store the boot
program, specific code libraries, reset and int errupt vectors, the reset routine and usually
the IAP and communication routines.
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Product overview
Figure 2: Flash memory organization
Read-out protection (ROP)
The read-out protection blocks reading and writing t he Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Onc e the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
4.4 Clock controller
The clock controller distributes the system clock (f
to the core and the peripherals. It also manages clo ck gating for low power modes and
ensures clock robustness.
Features
• Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
• Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock sig nal is not switched until the new clock
source is ready. The design guarantees glitch-f ree switching.
• Clock management: To reduce power consumption, t he cloc k controller can stop the
clock to the core, individual peripherals or memory .
• Master clock sources: Four different clock sour ces can be used to drive the master
clock:
− 1-16 MHz high-speed external crystal (HSE)
− Up to 16 MHz high-speed user-external clock (HSE user-ext)
− 16 MHz high-speed internal RC oscillator (HSI)
− 128 kHz low-speed internal RC (LSI)
) coming from different oscillators
MASTER
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Product overview
STM8S105xx
• Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock so urce can be changed by the
application program as soon as the code execution st art s.
• Clock security system (CSS): This feature can be e nabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is a ut om atically selected by the CSS
and an interrupt can optionally be generated.
• Configurable main clock output (CCO): This outputs an external clock for use by
the application.
Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit Peripheral
PCKEN17
PCKEN16
PCKEN15
PCKEN14
clock
TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC
TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU
TIM2 PCKEN11
TIM4 PCKEN10
Bit Peripheral
clock
4.5 Power management
For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between
lowest power consumption, fastest start-up time and available wakeup sources.
• Wait mode: In this mode, the CPU is stopped, but peripheral s are kept running. The
wakeup is performed by an internal or external interrupt or reset.
• Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at program mabl e i ntervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current
consumption is higher than in active halt mode with regulator off, but the wakeup time
is faster. Wakeup is triggered by the internal AW U interrupt, external interrupt or reset.
• Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up
time is slower.
• Halt mode :In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
Bit Peripheral
clock
SPI PCKEN25 Reserved PCKEN21 Reserved
I2C PCKEN24 Reserved PCKEN20 Reserved
Bit Peripheral
clock
4.6 Watchdog timers
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The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdo g behavior to match the application
perfectly.
STM8S105xx
Product overview
The application software must refresh the counter b efore time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed bef ore i t s value is lower than
the one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be us ed to resolve processor malfunctions due
to hardware or software failures.
It is clocked by the 128 kHz LSI internal RC clock source, an d thus stays active even in
case of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.7 Auto wakeup counter
• Used for auto wakeup from active halt mode
• Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
• LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
4.8 Beeper
The beeper function outputs a signal on the BEE P pin for so und generation. The signal is
in the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit
AFR7.
4.9 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of cont rol applications. With its
complementary outputs, dead-time control and c enter-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
• 16-bit up, down and up/down autoreload counter with 16-bit prescaler
• Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
• Synchronization module to control the timer with external signals
• Break input to force the timer outputs into a defined state
• Three complementary outputs with adjustable dead ti m e
• Encoder mode
• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.10 TIM2, TIM3 - 16-bit general purpose timers
• 16-bit autoreload (AR) up-counter
• 15-bit prescaler adjustable to fixed power of 2 ratios 1… 32768
• Timers with 3 or 2 individually configurable capture/compare channels
• PWM mode
• Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
DocID14771 Rev 13 15/99
Product overview
STM8S105xx
Additional AIN12 analog input is not selectable in A DC scan mode or with analog
4.11 TIM4 - 8-bit basic timer
• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
• Clock source: CPU clock
• Interrupt source: 1 x overflow/update
Table 4: TIM timer features
Timer Counter
size
(bits)
TIM1 16 Any
TIM2 16 Any
TIM3 16 Any
TIM4 8 Any
Prescaler Counting
mode
Up/Down 4 3 Yes No
integer
from 1 to
65536
Up 3 0 No
power of 2
from 1 to
32768
Up 2 0 No
power of 2
from 1 to
32768
Up 0 0 No
power of 2
from 1 to
128
CAPCOM
channels
4.12 Analog-to-digital converter (ADC1)
The STM8S105xx products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 10 multiplexed input channels and the following main features:
Complem.
outputs
Ext.
trigger
Timer
synchronization/
chaining
• Input voltage range: 0 to V
• Input voltage range: 0 to V
DD
DDA
• Conversion time: 14 clock cycles
• Single and continuous and buffered continuous conver sion m odes
• Buffer size (n x 10 bits) where n = number of input channels
• Scan mode for single and continuous conversion of a sequence of channels
• Analog watchdog capability with programmable uppe r and l ower thresholds
• Analog watchdog interrupt
• External trigger input
• Trigger from TIM1 TRGO
• End of conversion (EOC) interrupt
watchdog. Values converted from AIN12 are stored only into the
ADC_DRH/ADC_DRL registers.
16/99 DocID14771 Rev 13
STM8S105xx
Product overview
4.13 Communication interfaces
The following communication interfaces are implem ented:
• UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, LIN2.1 master/slave capability
• SPI : Full and half-duplex, 8 Mbit/s
• I²C: Up to 400 Kbit/s
4.13.1 UART2
Main features
• One Mbit/s full duplex SCI
• SPI emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• LIN master mode
• LIN slave mode
Asynchronous communication (UART mode)
• Full duplex communication - NRZ standard format (mark/space)
• Programmable transmit and receive baud rates up to 1 M bi t/s (f
following any standard baud rate regardless of t he i nput frequency
• Separate enable bits for transmitter and receiver
• Two receiver wakeup modes:
− Address bit (MSB)
− Idle line (interrupt)
• Transmission error detection with interrupt generation
• Parity control
/16) and capable of
CPU
Synchronous communication
• Full duplex synchronous transfers
• SPI master operation
• 8-bit data communication
• Maximum speed: 1 Mbit/s at 16 MHz (f
LIN master mode
• Emission: Generates 13-bit synch break frame
• Reception: Detects 11-bit break frame
LIN slave mode
• Autonomous header handling - one single interrupt per valid message header
• Automatic baud rate synchronization - maximum toler ated initial clock deviation ±15 %
• Synch delimiter checking
• 11-bit LIN synch break detection - break detection always active
• Parity check on the LIN identifier field
• LIN error management
• Hot plugging support
4.13.2 SPI
• Maximum speed: 8 Mbit/s (f
• Full duplex synchronous transfers
/16)
CPU
/2) both for master and slave
MASTER
DocID14771 Rev 13 17/99
Product overview
STM8S105xx
• Simplex synchronous transfers on two lines with a possibl e bi directional data line
• Master or slave operation - selectable by hardware or software
• CRC calculation
• 1 byte Tx and Rx buffer
• Slave/master selection input pin
4.13.3 I²C
• I²C master features:
• I²C slave features:
• Generation and detection of 7-bit/10-bit addressing and general call
• Supports different communication speeds:
− Clock generation
− Start and stop generation
− Programmable I2C address detection
− Stop bit detection
− Standard speed (up to 100 kHz)
− Fast speed (up to 400 kHz)
18/99 DocID14771 Rev 13
STM8S105xx
Pinout and pin description
5 Pinout and pin description
Table 5: Legend/abbreviations for pinout tables
Type I= Input, O = Output, S = Power supply
Level
Output speed
Port and control
configuration
Reset state Bold X (pin state after internal res et release).
5.1 STM8S105 pinouts and pin descripti on
Input CM = CMOS
Output HS = High sink
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmabilit y with slow as default state after reset
O4 = Fast/slow programmabilit y with fast as default state after reset
Input float = floating, wpu = weak pull-up
Output T = True open drain, OD = Open drain, PP = Push pull
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset r elease.
Figure 3: LQFP 48-pin pinout
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V
not implemented).
DD
3. [ ] alternate function remapping option (If the same al ternate function is shown twice, it
indicates an exclusive choice not a duplication of t he function).
DocID14771 Rev 13 19/99
Pinout and pin description
STM8S105xx
Figure 4: LQFP 44-pin pinout
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V
not implemented).
DD
3. [ ] alternate function remapping option (If the same al ternate function is shown twice, it
indicates an exclusive choice not a duplication of t he function).
20/99 DocID14771 Rev 13
STM8S105xx
Pinout and pin description
Figure 5: LQFP/UFQFPN 32-pin pinout
1. (HS) high sink capability.
2. [ ] alternate function remapping option (If the same al ternate function is shown twice, it
indicates an exclusive choice not a duplication of t he function).
Figure 6: SDIP 32-pin pinout
1. (HS) high sink capability.
2. (T) True open drain (P-buffer and protection diode to V
not implemented).
DD
3. [ ] alternate function remapping option (If the same al ternate function is shown twice, it
indicates an exclusive choice not a duplication of t he function).
DocID14771 Rev 13 21/99
Pinout and pin description
STM8S105xx
LQFP32/
UFQFPN32
PP
Table 6: Pin description for STM8S105 microcontrollers
Pin number
LQFP48 LQFP44
1 1 1 6
2 2 2 7 PA1/ OSC IN I/O
3 3 3 8 PA2/ OSC OUT I/O
4 4 - 5 5 4 9
6 6 5 10
7 7 6 11
8 8 7 12
9 - - - PA3/ TIM2 _CH3
10 9 - 11 10 - 12 11 - -
- - 8 13 PF4/ AIN1 2
13 12 9 14
14 13 10 15
15 14 - - PB7/ AIN7 I/O
16 15 - - PB6/ AIN6 I/O
17 16 11 16 PB5/ AIN5
18 17 12 17 PB4/ AIN4
19 18 13 18 PB3/ AIN3
20 19 14 19 PB2/ AIN2
21 20 15 20 PB1/ AIN1
22 21 16 21 PB0/ AIN0
23 - - - PE7/ AIN8 I/O
24 22 - - PE6/ AIN9 I/O
25 23 17 22 PE5/SPI_NSS I/O
26 24 18 23 PC1/ TIM1_CH1
SDIP32
Pin name
NRST
V
SSIO_1
VSS
VCAP
VDD
V
DDIO_1
[TIM3 _CH1]
PA4
PA5
PA6
(1)
V
DDA
V
SSA
2
[I
C_ SDA]
2
[I
C_ SCL]
[TIM1_ ETR]
[TIM1_CH3N]
[TIM1_CH2N]
[TIM1_CH1N]
UART2_CK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Type
S
S
S
S
S
S
S
Input
floating
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
wpu
Ext. interrupt
X
X
X X
X X
X X HS O3 X X
X X HS O3 X X
X X HS O3 X X
X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X
X X HS O3 X X
Output
High sink
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
O1 X X
Speed
OD
Main
function
(after
reset)
Port A1
Port A2
I/O ground
Digital ground
1.8 V regulator capacitor
Digital power supply
I/O power supply
Port A3
Port A4
Port A5
Port A6
Port F4
Analog power supply
Analog ground
Port B7
Port B6
Port B5
Port B4
Port B3
Port B2
Port B1
Port B0
Port E7
Port E6
Port E5
SPI master/slave select
Port C1
Alternate function
Default alternate
function
Reset
Resonator crystal in
Resonator crystal out
Timer 2 - channel 3 TIM3_CH1 [AFR1]
clock
(2)
(3)
Analog input 12
Analog input 7
Analog input 6
Analog input 5
Analog input 4
Analog input 3
Analog input 2
Analog input 1
Analog input 0
Analog input 8
Analog input 9
Timer 1 – channel 1/
UART2 synchronous
after remap
[option bit]
I2C_SDA [AFR6]
I2C_SCL [AFR6]
TIM1_ETR [AFR5]
TIM1_CH3N [AFR5]
TIM1_ CH2N [AFR5]
TIM1_CH1N [AFR5]
22/99 DocID14771 Rev 13
STM8S105xx
Pinout and pin description
LQFP32/
UFQFPN32
PP
Pin number
LQFP48 LQFP44
27 25 19 24 PC2/ TIM1_CH2 I/O
28 26 20 25 PC3/ TIM1_CH3 I/O
29 - 21 26 PC4/ TIM1_CH4 I/O
30 27 22 27 PC5/ SPI_SCK I/O
31 28 - 32 29 - 33 30 23 28 PC6/ SPI_MOSI I/O
34 31 24 29 PC7/ SPI_MISO I/O
35 32 - 36 33 - 37 - - - PE3/ TIM1_BKIN I/O
38 34 - - PE2/ I2C_SDA I/O
39 35 - - PE1/ I2C_ SCL I/O
40 36 - - PE0/ CLK_ CCO I/O
41 37 25 30 PD0/ TIM3_CH2
SDIP32
Pin name
Type
V
S
S
SSIO_2
V
DDIO_2
PG0
I/O
PG1
I/O
I/O
Input
floating
X
X
X
X
X
X
X
X
X
X
X
X
X
wpu
Ext. interrupt
X X HS O3 X X
X X HS O3 X X
X X HS O3 X
X X HS O3 X X
X X HS O3 X X
X X HS O3 X X
X
X
X X
X
X
X X HS O3 X X
X X HS O3 X X
Output
High sink
O1 X X
O1 X X
O1 X X
O1 T
O1 T
Speed
OD
(4)
(4)
[TIM1_BKIN]
[CLK_CCO]
42 38 26 31 PD1/ SWIM
(5)
43 39 27 32 PD2/ TIM3_CH1
[TIM2_CH3]
44 40 28 1
PD3/
I/O
I/O
I/O
X
X X HS O4 X X
X
X X HS O3 X X
X
X X HS O3 X X
TIM2_CH2
[ADC_ETR]
X
45 41 29 2
PD4/
I/O
X X HS O3 X X
TIM2_CH1
[BEEP]
X
46 42 30 3
47 43 31 4
48 44 32 5
PD5/
UART2_TX
PD6/
UART2_RX
PD7/ TLI
I/O
I/O
I/O
X
X
X X
X X
X X
O1 X X
O1 X X
O1 X X
[TIM1_CH4]
Notes:
(1)
A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.
(2)
AIN12 is not selectable in ADC scan mode or with analog watchdog.
(3)
In 44-pin package, AIN9 cannot be used by ADC scan mode.
(4)
In the open-drain out put column, ‘T’ defines a true op en -drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented).
(5)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Main
function
(after
reset)
Port C2
Port C3
Port C4
Port C5
Port C6
Port C7
Port G0
Port G1
Port E3
Port E2
Port E1
Port E0
Port D0
Port D1
Port D2
Port D3
Port D4
Port D5
Port D6
Port D7
Alternate function
Default alternate
function
SPI clock
Timer 1- channel 2
Timer 1 - channel 3
Timer 1 - channel 4
I/O ground
I/O power supply
SPI master out/slave in
SPI master in/ slave out
Timer 1 - break input
I2C data
I2C clock
Configurable clock
output
Timer 3 - channel 2 TIM1_BKIN [AFR3]/
SWIM data interface
Timer 3 - channel 1 TIM2_CH3 [AFR1]
Timer 2 - channel 2 ADC_ETR [AFR0]
Timer 2 - channel 1 BEEP output [AFR7]
UART2 data transmit
UART2 data receive
Top level interrupt TIM1_CH4 [AFR4]
after remap
[option bit]
CLK_CCO [AFR2]
DocID14771 Rev 13 23/99
Pinout and pin description
STM8S105xx
5.1.1 Alternate function remapping
As shown in the rightmost column of the pin descripti on table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is act i ve, the default alternate function is no
longer available.
To use an alternate function, the corresponding peri pheral must be enabled in the
peripheral registers.
Alternate function remapping does not aff ect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0 016).
24/99 DocID14771 Rev 13
STM8S105xx
Memory and register map
6 Memory and register map
6.1 Memory map
Figure 7: Memory map
The following table lists the boundary addresses for each memory size. The top of the
stack is at the RAM end address in each case.
DocID14771 Rev 13 25/99
Memory and register map
STM8S105xx
Table 7: Flash, Data EEPROM and RAM boundary addresses
Memory area Size (bytes) Start address End address
Flash program memory 32K 0x00 8000 0x00 FFFF
RAM 2K 0x00 0000 0x00 07FF
Data EEPROM 1024 0x00 4000 0x00 43FF
6.2 Register map
6.2.1 I/O port hardware register map
Table 8: I/O port hardware register map
Address Block Register label Register name Reset status
0x00 5000 Port A PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR P ort A input pin value register 0xXX
0x00 5002 PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 Port B PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR P ort B input pin value register 0xXX
0x00 5007 PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A Port C PC_ODR Port C data output latch register 0x00
0x00 500B PC_IDR Port C input pin value register 0xXX
0x00 500C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F Port D PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 PD_DDR Port D data direction re gister 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014 Port E PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR P ort E input pin value register 0xXX
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019 Port F PF_ODR Port F data output latch register 0x00
16K 0x00 8000 0x00 BFFF
26/99 DocID14771 Rev 13
STM8S105xx
Memory and register map
Address Block Register label Register name Reset status
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B PF_DDR Port F data direction re gister 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
0x00 501E Port G PG_ODR Port G data output latch register 0x00
0x00 501F PG_IDR Port G input pin value register 0xXX
0x00 5020 PG_DDR Port G data direction register 0x00
0x00 5021 PG_CR1 Port G control register 1 0x00
0x00 5022 PG_CR2 Port G control register 2 0x00
0x00 5023 Port H PH_ODR Port H data output latch regis ter 0x00
0x00 5024 PH_IDR Port H input pin value register 0xXX
0x00 5025 PH_DDR Port H data direction re gister 0x00
0x00 5026 PH_CR1 Port H control register 1 0x00
0x00 5027 PH_CR2 Port H control register 2 0x00
0x00 5028 Port I PI_ODR Port I data output latch register 0x00
0x00 5029 PI_IDR Port I input pin value register 0xXX
0x00 502A PI_DDR Port I data direction register 0x00
0x00 502B PI_CR1 Port I control register 1 0x00
0x00 502C PI_CR2 Port I control register 2 0x00
6.2.2 General hardware register map
Table 9: General hardware register m ap
Address Block Register label Register name Reset
0x00 5050 to
0x00 5059
0x00 505A Flash FLASH_CR1 Flash control r egister 1 0x00
0x00 505B FLASH_CR2 Flash control register 2 0x00
0x00 505C FLASH_NCR2 Flash complementary control
0x00 505D FLASH _FPR Flash protection register 0x00
0x00 505E FLASH _NFPR Flash complementary protection
0x00 505F FLASH _IAPSR Flash in-application programming
0x00 5060 to
0x00 5061
0x00 5062 Flash FLASH _PUKR Flash program memory
status
Reserved area (10 bytes)
0xFF
register 2
0xFF
register
0x00
status register
Reserved area (2 bytes)
0x00
unprotection register
DocID14771 Rev 13 27/99
Memory and register map
STM8S105xx
(2)
Address Block Register label Register name Reset
0x00 5063 Reserved area (1 byte)
0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection
register
0x00 5065 to
Reserved area (59 bytes)
0x00 509F
0x00 50A0 ITC EXTI_CR1 External interru pt control register 1 0x00
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 to
Reserved area (17 bytes)
0x00 50B2
0x00 50B3 RST RST_SR Reset status register 0xXX
0x00 50B4 to
Reserved area (12 bytes)
0x00 50BF
0x00 50C0 CLK CLK_ICKR Internal clock control register 0x01
0x00 50C1 CLK_ECKR External clock control register 0x00
0x00 50C2 Reserved area (1 byte)
0x00 50C3 CLK CLK_CMSR Clock master status register 0xE1
0x00 50C4 CLK_SWR Clock master switch register 0xE1
0x00 50C5 CLK_SWCR Clock switch control register 0xXX
0x00 50C6 CLK_CKDIVR Clock divider regist er 0x18
0x00 50C7 CLK_PCKENR1 Peripher al clock gating register 1 0xFF
0x00 50C8 CLK_CSSR Clock security system register 0x00
0x00 50C9 CLK_CCOR Configurable clock control register 0x00
0x00 50CA CLK_PCKENR2 Peripheral clock gating registe r 2 0xFF
0x00 50CB CLK_CANCCR CAN clock control register 0x00
0x00 50CC CLK_HSITRIMR HSI clock calibration trimming
register
0x00 50CD CLK_SWIMCCR
0x00 50CE to
SWIM clock control register 0bXXXX
Reserved area (3 bytes)
0x00 50D0
0x00 50D1 WWDG WWDG_CR WWDG control regist er 0x7F
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3 to
Reserved area (13 bytes)
0x00 50DF
0x00 50E0 IWDG IWDG_KR IWDG key register 0xXX
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3 to
Reserved area (13 bytes)
0x00 50EF
0x00 50F0 AWU AWU_CSR1 AWU control/ status register 1 0x00
status
0x00
(1)
0x00
XXX0
28/99 DocID14771 Rev 13
STM8S105xx
Memory and register map
Address Block Register label Register name Reset
0x00 50F1 AWU_APR AWU asynchronous prescaler
buffer register
0x00 50F2 AWU_TBR AWU timebase selection register 0x00
0x00 50F3 BEEP BEEP_CSR BEEP control/ status register 0x1F
0x00 50F4 to
Reserved area (12 bytes)
0x00 50FF
0x00 5200 SPI SPI_CR1 SPI control register 1 0x00
0x00 5201 SPI_CR2 SPI control register 2 0x00
0x00 5202 SPI_ICR SPI interrupt control register 0x00
0x00 5203 SPI_SR SPI status register 0x02
0x00 5204 SPI_DR SPI data register 0x00
0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07
0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF
0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF
0x00 5208 to
Reserved area (8 bytes)
0x00 520F
0x00 5210 I2C I2C_CR1 I2C control register 1 0x00
0x00 5211 I2C_CR2 I2C control register 2 0x00
0x00 5212 I2C_FREQR I2C frequency register 0x00
0x00 5213 I2C_OARL I2C Own address register low 0x00
0x00 5214 I2C_OARH I2C own address register high 0x00
0x00 5215 Reserved
0x00 5216 I2C_DR I2C data register 0x00
0x00 5217 I2C_SR1 I2C status register 1 0x00
0x00 5218 I2C_SR2 I2C status register 2 0x00
0x00 5219 I2C_SR3 I2C status register 3 0x00
0x00 521A I2C_ITR I2C interrupt control register 0x00
0x00 521B I2C_CCRL I2C clock control register low 0x00
0x00 521C I2C_CCRH I2C clock control register high 0x00
0x00 521D I2C_TRISER I2C TRISE register 0x02
0x00 521E I2C_PECR I2C packet error checking register 0x00
0x00 521F to
Reserved area (17 bytes)
0x00 522F
0x00 5230 to
Reserved area (6 bytes)
0x00 523F
0x00 5240 UART2 UART2_SR UART2 status register 0xC0
0x00 5241 UART2_DR UART2 data register 0xXX
0x00 5242 UART2_BRR1 UART2 baud rate regist er 1 0x00
status
0x3F
DocID14771 Rev 13 29/99
Memory and register map
STM8S105xx
Address Block Register label Register name Reset
0x00 5243 UART2_BRR2 UART2 baud rate regist er 2 0x00
0x00 5244 UART2_CR1 UART2 control register 1 0x00
0x00 5245 UART2_CR2 UART2 control register 2 0x00
0x00 5246 UART2_CR3 UART2 control register 3 0x00
0x00 5247 UART2_CR4 UART2 control register 4 0x00
0x00 5248 UART2_CR5 UART2 control register 5 0x00
0x00 5249 UART2_CR6 UART2 control register 6 0x00
0x00 524A UART2_GTR UART2 guard ti me register 0x00
0x00 524B UART2_PSCR UART2 prescaler register 0x00
0x00 524C to
Reserved area (4 bytes)
0x00 524F
0x00 5250 TIM1
0x00 5251 TIM1_CR2 TIM1 control register 2 0x00
TIM1_CR1 TIM1 control register 1 0x00
0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00
0x00 5253 TIM1_ETR TIM1 external trigger register 0x00
0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00
0x00 5255 TIM1_SR1 TIM1 status register 1 0x00
0x00 5256 TIM1_SR2 TIM1 status register 2 0x00
0x00 5257 TIM1_EGR TIM1 event generation register 0x00
0x00 5258 TIM1_CCMR1 TIM1 capture/ compare mode
register 1
0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode
register 2
0x00 525A TIM1_CCMR3 TIM1 capture/ compare mode
register 3
0x00 525B TIM1_CCMR4 TIM1 capture/compare mode
register 4
0x00 525C TIM1_CCER1 TIM1 capture/ compare enable
register 1
0x00 525D TIM1_CCER2 TIM1 capture/compare enable
register 2
0x00 525E TIM1_CNTRH TIM1 counter high 0x00
0x00 525F TIM1_CNTRL TIM1 counter low 0x00
0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF
0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF
0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00
status
0x00
0x00
0x00
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