ST MICROELECTRONICS STM8S001J3M3 Datasheet

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STM8S001J3

SO8N

4.9x6 mm or 150 mils width

16 MHz STM8S 8-bit MCU, 8-Kbyte Flash memory, 128-byte data

EEPROM, 10-bit ADC, 3 timers, UART, SPI, I2C

Datasheet - production data

Features

Core

• 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline

• Extended instruction set

Memories

• Program memory: 8 Kbytes Flash memory; data retention 20 years at 55 °C after 100 cycles

• RAM: 1 Kbyte

• Data memory: 128-byte true data EEPROM;

endurance up to 100 k write/erase cycles

Clock, reset and supply management

Timers

• Advanced control timer: 16-bit, 2 CAPCOM channels, 2 outputs, dead-time insertion and flexible synchronization

• 16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)

• 8-bit basic timer with 8-bit prescaler

• Auto wakeup timer

• Window and independent watchdog timers

• 2.95 V to 5.5 V operating voltage

• Flexible clock control, 3 master clock sources

– External clock input – Internal, user-trimmable 16 MHz RC – Internal low-power 128 kHz RC

• Clock security system with clock monitor

• Power management

– Low-power modes (wait, active-halt, halt) – Switch-off peripheral clocks individually – Permanently active, low-consumption

power-on and power-down reset

Interrupt management

• Nested interrupt controller with 32 interrupts

• Up to 5 external interrupts

Communications interfaces

• UART, SmartCard, IrDA, LIN master mode

• SPI unidirectional interface up to 8 Mbit/s

(master simplex mode, slave receiver only)

• I2C interface up to 400 Kbit/s

Analog to digital converter (ADC)

• 10-bit ADC, ± 1 LSB ADC with up to 3 multiplexed channels, scan mode and analog watchdog

• Internal reference voltage measurement

I/Os

• Up to 5 I/Os including 4 high-sink outputs

• Highly robust I/O design, immune against

current injection

Development support

• Embedded single-wire interface module (SWIM) or fast on-chip programming and nonintrusive debugging

June 2018 DS12129 Rev 3 1/85

This is information on a product in full production.

www.st.com

Contents STM8S001J3

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 12

4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . 12

4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.9 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.10 TIM2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.11 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.12 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.13 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.13.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.13.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.13.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 STM8S001J3 SO8N pinout and pin description . . . . . . . . . . . . . . . . . . . . 21

5.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.2.1 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.2.2 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/85 DS12129 Rev 3

STM8S001J3 Contents

6.2.3 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . 34

7 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.1 Alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 54

9.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 54

9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9.3.7 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

9.3.8 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

9.3.9 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

10.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 80

11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 82

DS12129 Rev 3 3/85

Contents STM8S001J3

12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4/85 DS12129 Rev 3

STM8S001J3 List of tables

List of tables

Table 1. STM8S001J3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15

Table 3. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Legend/abbreviations for STM8S001J3 pin description tables. . . . . . . . . . . . . . . . . . . . . . 21

Table 5. STM8S001J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7. I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 9. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 11. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 12. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices . . . . . . . . . . . . . . . . . . . 39

Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 18. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 19. Total current consumption with code execution in run mode at V Table 20. Total current consumption with code execution in run mode at V Table 21. Total current consumption in wait mode at V Table 22. Total current consumption in wait mode at V Table 23. Total current consumption in active halt mode at V Table 24. Total current consumption in active halt mode at V Table 25. Total current consumption in halt mode at V Table 26. Total current consumption in halt mode at V

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 47

= 5 V . . . . . . . . . . . . . . . . . . . . . . . 48

= 3.3 V . . . . . . . . . . . . . . . . . . . . . 48

= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27. Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 28. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 29. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 30. HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 31. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 32. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 33. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 34. Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 36. Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 37. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 38. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 39. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 40. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 41. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 42. ADC accuracy with R Table 43. ADC accuracy with R

< 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

AIN

< 10 kΩ R

AIN

, V

= 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 44. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 45. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 46. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 47. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 48. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

= 5 V . . . . . . . . . . . . 45

= 3.3 V . . . . . . . . . . . 46

DS12129 Rev 3 5/85

List of tables STM8S001J3

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 49. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6/85 DS12129 Rev 3

STM8S001J3 List of figures

List of figures

Figure 1. STM8S001J3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. STM8S001J3 SO8N pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 7. f

CPUmax

Figure 8. External capacitor C Figure 9. Typ. I Figure 10. Typ. I Figure 11. Typ. I Figure 12. Typ. I Figure 13. Typ. I Figure 14. Typ. I

Figure 15. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 16. Typical HSI frequency variation vs V Figure 17. Typical LSI frequency variation vs V Figure 18. Typical V Figure 19. Typical pull-up resistance vs V Figure 20. Typical pull-up current vs V Figure 21. Typ. V Figure 22. Typ. V Figure 23. Typ. V Figure 24. Typ. V Figure 25. Typ. V Figure 26. Typ. V Figure 27. Typ. V Figure 28. Typ. V Figure 29. Typ. V Figure 30. Typ. V

Figure 31. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 32. SPI timing diagram - slave mode and CPHA = 1 Figure 33. SPI timing diagram - master mode

Figure 34. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 35. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 36. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 37. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 77 Figure 38. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 39. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 40. STM8S001J3 ordering information scheme

versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DD(RUN)

DD(WFI)

vs VDD, HSE user external clock, f vs f

vs VDD, HSI RC osc, f vs. VDD HSE user external clock, f vs. f vs VDD, HSI RC osc, f

and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

@ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

@ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

@ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

@ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

@ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

- V

EXT

, HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 51

CPU

, HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 53

CPU

@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

CPU

= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

CPU

at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 55

@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 56

@ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

= 16 MHz . . . . . . . . . . . . . . . . . . . . 51

CPU

= 16 MHz . . . . . . . . . . . . . . . . . . . . . 52

CPU

@ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

@ VDD = 3.3 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

@ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

@ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

DS12129 Rev 3 7/85

Introduction STM8S001J3

1 Introduction

This datasheet contains the description of the STM8S001J3 features, pinout, electrical characteristics, mechanical data and ordering information.

• For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).

• For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM).

• For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).

• For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).

8/85 DS12129 Rev 3

STM8S001J3 Description

2 Description

The STM8S001J3 8-bit microcontrollers offer 8 Kbytes of Flash program memory, plus integrated true data EEPROM. It is referred to as low-density device in the STM8S microcontroller family reference manual (RM0016).

The STM8S001J3 device provides the following benefits: performance, robustness and reduced system cost.

Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the-art technology at 16 clock source, and a clock security system.

The system cost is reduced thanks to a high system integration level with internal clock oscillators, watchdog, and brown-out reset.

Full documentation is offered as well as a wide choice of development tools.

Pin count 8

MHz clock frequency, robust I/Os, independent watchdogs with separate

Table 1. STM8S001J3 features

Features STM8S001J3

Max. number of GPIOs (I/O) 5

External interrupt pins 5

Timer CAPCOM channels 3

Timer complementary outputs 1

A/D converter channels 3

High-sink I/Os 4

Low-density Flash program memory (byte)

RAM (byte) 1 K

True data EEPROM (byte) 128

Multi purpose timer (TIM1), SPI unidirectional, I2C, UART,

Peripheral set

1. Without read-while-write capability.

independent WDG, ADC, PWM timer (TIM2), 8-bit timer

Window WDG,

(TIM4)

8 K

(1)

DS12129 Rev 3 9/85

Block diagram STM8S001J3

MSv44651V1

Reset block

Reset

POR BOR

Clock controller

Detector

RC int. 16 MHz

RC int. 128 kHz

Ext. Clock input

1 – 16 MHz

STM8 core

Debug / SWIM

I2C

Unidirectional SPI

UART1

ADC1

Window WDG

Independent WDG

8 Kbyte

program Flash

128 byte

data EEPROM

1 Kbyte RAM

16-bit advanced

control timer (TM1)

16-bit general purpose timer

(TIM2)

8-bit basic timer

(TIM4)

AWU timer

Address and data bus

Clock to peripherals and core

Up to 3

channels

LIN master

8 Mbit/s

400 Kbit/s

Single wire

debug

interface

Up to 3 CAPCPOM channels

Up to 2 CAPCPOM channels

3 Block diagram

Figure 1. STM8S001J3 block diagram

10/85 DS12129 Rev 3

STM8S001J3 Functional overview

4 Functional overview

The following section intends to give an overview of the basic features of the STM8S001J3 functional modules and peripherals.

For more detailed information please refer to the corresponding family reference manual (RM0016).

4.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

• Harvard architecture

• 3-stage pipeline

• 32-bit wide program memory bus - single cycle fetching for most instructions

• X and Y 16-bit index registers - enabling indexed addressing modes with or without

offset and read-modify-write type data manipulations

• 8-bit accumulator

• 24-bit program counter - 16-Mbyte linear memory space

• 16-bit stack pointer - access to a 64 K-level stack

• 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

• 20 addressing modes

• Indexed indirect addressing mode for look-up tables located anywhere in the address

space

• Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

• 80 instructions with 2-byte average instruction size

• Standard data movement and logic/arithmetic functions

• 8-bit by 8-bit multiplication

• 16-bit by 8-bit and 16-bit by 16-bit division

• Bit manipulation

• Data transfer between stack and accumulator (push/pop) with direct stack access

• Data transfer using the X and Y registers or direct memory-to-memory transfers

DS12129 Rev 3 11/85

Functional overview STM8S001J3

4.2 Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.

SWIM

Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms.

Debug module

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

• R/W to RAM and peripheral registers in real-time

• R/W access to all resources by stalling the CPU

• Breakpoints on all program-memory instructions (software breakpoints)

• Two advanced breakpoints, 23 predefined configurations

Recommendation for SWIM pin (pin #8) sharing

As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever. This initial delay can be removed in the final (locked) code.

If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for device debug/programming.

4.3 Interrupt controller

• Nested interrupts with three software priority levels

• 32 interrupt vectors with hardware priority

• Up to 5 external interrupts including TLI

• Trap and reset interrupts

4.4 Flash program memory and data EEPROM

• 8 Kbytes of Flash program single voltage Flash memory

• 128 byte true data EEPROM

• User option byte area

12/85 DS12129 Rev 3

STM8S001J3 Functional overview

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.

There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes.

A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to

The size of the UBC is programmable through the UBC option byte (Ta b le 12), in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

• Main program memory: 8 Kbyte minus UBC

• User-specific boot code (UBC): Configurable up to 8 Kbyte

The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.

Figure 2.

Low density Flash program memory (8 Kbytes)

Figure 2. Flash memory organization

Option bytes

Data EEPROM (128 bytes)

UBC area

Remains write protected during IAP

Program memory area

Write access possible for IAP

Programmable area from 64 bytes (1 page) up to 8 Kbytes (in 1 page steps)

MS36408V1

DS12129 Rev 3 13/85

Functional overview STM8S001J3

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

Recommendation for the device's programming:

The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space).

If the device's program memory is empty (0x00 content), it displays the behavior described below:

• After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG (0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF). It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz HSI clock.

• Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed. The reading of non-existing memory is a random content which can lead to the execution of invalid instructions. The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more.

Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device.

The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop.

14/85 DS12129 Rev 3

STM8S001J3 Functional overview

4.5 Clock controller

The clock controller distributes the system clock (f

MASTER)

coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.

Features

• Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.

• Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• Master clock sources: Three different clock sources can be used to drive the master

clock:

– Up to 16 MHz high-speed user-external clock (HSE user-ext)

– 16 MHz high-speed internal RC oscillator (HSI)

– 128 kHz low-speed internal RC (LSI)

• Startup clock: After reset, the microcontroller restarts by default with an internal

2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): This feature can be enabled by software. If an HSE

clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.

• Configurable main clock output (CCO): This outputs an external clock for use by the

application.

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit

PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC

PCKEN16 Reserved PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU

PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved

PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved

Peripheral

clock

Bit

Peripheral

clock

DS12129 Rev 3 15/85

Bit

Peripheral

clock

Bit

Peripheral

clock

Functional overview STM8S001J3

4.6 Power management

For efficient power management, the application can be put in one of four different lowpower modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources.

• Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

wakeup is performed by an internal or external interrupt or reset.

• Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are

stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

• Active halt mode with regulator off: This mode is the same as active halt with

regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.

• Halt mode: In this mode the microcontroller uses the least power. The CPU and

peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.

4.7 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to the applications.

Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application perfectly.

The application software must refresh the counter before time-out and during a limited time window.

A reset is generated in two situations:

1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up

to 64

ms.

2. Refresh out of window: the down-counter is refreshed before its value is lower than the

one stored in the window register.

16/85 DS12129 Rev 3

STM8S001J3 Functional overview

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

4.8 Auto wakeup counter

• Used for auto wakeup from active halt mode

• Clock source: internal 128 kHz internal low frequency RC oscillator or external clock

• LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

4.9 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to lighting and half-bridge driver.

• 16-bit up, down and up/down autoreload counter with 16-bit prescaler

• Four independent capture/compare channels (CAPCOM) configurable as input

capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output

• Synchronization module to control the timer with external signals

• Break input to force the timer outputs into a defined state

• One complementary output (CH1 with CH1N option) with adjustable dead time

• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.10 TIM2 - 16-bit general purpose timer

• 16-bit autoreload (AR) up-counter

• 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

• 3 individually configurable capture/compare channels

• PWM mode

• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update

4.11 TIM4 - 8-bit basic timer

• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

• Clock source: CPU clock

• Interrupt source: 1 x overflow/update

DS12129 Rev 3 17/85

Functional overview STM8S001J3

Counter

Timer

TIM1 16 Any integer from 1 to 65536 Up/down 2 1

TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No

TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No

1. TIM1_CH2N with TIM1_CH1

size

(bits)

Prescaler

Table 3. TIM timer features

Counting

mode

CAPCOM

channels

Complem.

outputs

(1)

4.12 Analog-to-digital converter (ADC1)

STM8S001J3 contains a 10-bit successive approximation A/D converter (ADC1) with up to three external and one internal multiplexed input channels and the following main features:

• Input voltage range: 0 to V

• Conversion time: 14 clock cycles

• Single and continuous, buffered continuous conversion modes

• Buffer size (10 x 10 bits)

• Scan mode for single and continuous conversion of a sequence of channels

• Analog watchdog capability with programmable upper and lower thresholds

• Analog watchdog interrupt

• Internal reference voltage on channel AIN7

• External trigger input

• Trigger from TIM1 TRGO

• End of conversion (EOC) interrupt

DDA

Ext.

trigger

Timer

synchr-

onization/

chaining

next paragraph :

Internal bandgap reference voltage

Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal bandgap reference is constant and can be used, for example, to monitor V determine the absolute voltage on external input channels. It is independent of variations in V

and ambient temperature TA.

4.13 Communication interfaces

The following communication interfaces are implemented:

• UART1: full feature UART, synchronous mode, SmartCard mode, IrDA mode, LIN2.1

master capability

• SPI: master mode transmit/receive only, slave mode receive only, 8 Mbit/s

• I²C: up to 400 Kbit/s

18/85 DS12129 Rev 3

or to

STM8S001J3 Functional overview

4.13.1 UART1

Main features

• 1 Mbit/s full duplex SCI

• High precision baud rate generator

• Smartcard reader emulation

• IrDA SIR encoder decoder

• LIN master mode

• Single wire half duplex mode

Asynchronous communication (UART mode)

• Full duplex communication - NRZ standard format (mark/space)

• Programmable transmit and receive baud rates up to 1 Mbit/s (f

following any standard baud rate regardless of the input frequency

• Separate enable bits for transmitter and receiver

• Two receiver wakeup modes:

– Address bit (MSB)

– Idle line (interrupt)

• Transmission error detection with interrupt generation

• Parity control

/16) and capable of

CPU

LIN master mode

• Emission: generates 13-bit synch. break frame

• Reception: detects 11-bit break frame

4.13.2 SPI

• Maximum speed: 8 Mbit/s (f

• Unidirectional transfer: SPI master mode transmit/receive only, SPI slave mode receive

• Simplex master synchronous transfers on two lines with a possible bidirectional data

• Master or slave operation - selectable by software

• CRC calculation

• 1 byte Tx and Rx buffer

only

line

MASTER

/2) both for master and slave

DS12129 Rev 3 19/85

Functional overview STM8S001J3

4.13.3 I2C

• I2C master features

– Clock generation

– Start and stop generation

• I2C slave features

– Programmable I2C address detection

– Stop bit detection

• Generation and detection of 7-bit/10-bit addressing and general call

• Supports different communication speeds

– Standard speed (up to 100 kHz)

– Fast speed (up to 400 kHz)

20/85 DS12129 Rev 3

STM8S001J3 Pinouts and pin descriptions

MSv44652V2

STM8S

PD5/AIN5/UART1_TX/ PD3/AIN4/TIM2_CH2/ADC_ETR/ PD1/SWIM/ PC6/SPI_MOSI/[TIM1_CH1]

PC5/SPI_SCK/[TIM2_CH1]/ PC4/CLK_CCO/TIM1_CH4/[AIN2]/[TIM1_CH2N] PC3/TIM1_CH3/[TLI]/[TIM1_CH1N]

PB4/I2C_SCL/[ADC_ETR]

PB5/I2C_SDA/[TIM1_BKIN]/ PA3/TIM2_CH3/[SPI_NSS]/[UART1_TX]

PD6/AIN6/UART1_RX/

PA1/OSCIN

VSS/VSSA

VCAP

VDD/VDDA

5 Pinouts and pin descriptions

This section presents the pinouts and pin descriptions for STM8S001J3. Tab le 4 introduces the legends and abbreviations that are used in the upcoming subsections.

Type I = input, O = output, S = power supply

Level

Output speed

Port and control configuration

Reset state

Table 4. Legend/abbreviations for STM8S001J3 pin description tables

Input CM = CMOS

Output HS = high sink

O1 = slow (up to 2 MHz) O2 = fast (up to 10 MHz) O3 = fast/slow programmability with slow as default state after reset O4 = fast/slow programmability with fast as default state after reset

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold x

(pin state after internal reset release)

Unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release.

5.1 STM8S001J3 SO8N pinout and pin description

Figure 3 presents the STM8S001J3 pinout image and Tab le 5 below presents the device’s

pins description.

Figure 3. STM8S001J3 SO8N pinout

1. [ ] Alternative function option (if the same alternate function is shown twice, it indicated an exclusive choice

and not a duplication of the function).

DS12129 Rev 3 21/85

Pinouts and pin descriptions STM8S001J3

Pin no.

SO8N

Pin name Type

PD6/ AIN6/ UART1 _RX

(2)

Table 5. STM8S001J3 pin description

Input Output

High

(1)

sink

Speed

Ext. interr.

I/O X

wpu

floating

XX HS O3 XX Port D6

OD PP

Main

function

(after

reset)

Default

alternate

function

Analog input 6/ UART1 data receive

External clock input

PA1/ OSCIN

(3)

I/O X X X - O1 X X Port A1

(HSE clock)

2 VSS/VSSA S - - - - - - - Ground -

3VCAP S - -- - ---

1.8 V regulator capacitor

4 VDD/VDDA S - - - - - - - Power supply -

PA3/ TIM2_ CH3 [SPI_ NSS]\ [UART1_TX]

(2)

I/O X X X HS O3 X X Port A3

Timer 2 channel 3

PB5/ I2C_ SDA [TIM1_ BKIN]

PB4/ I2C_ SCL

/[ADC_ETR]

PC3/ TIM1_CH3 [TLI] [TIM1_ CH1N]

PC4/ CLK_CCO/ TIM1_ CH4/[AIN2]/ [TIM1_ CH2N]

PC5/ SPI_SCK [TIM2_ CH1]

I/O X

- X - O1 T

I/O X - X - O1 T

I/O X

X X HS O3 X X Port C3

X X HS O3 X X Port C4

X X HS O3 X X Port C5 SPI clock

(4)

- Port B5 I2C data

(4)

- Port B4 I2C clock

Timer 1 channel 3

Configurable clock output/Timer 1 - channel 4

Alternate

function

after remap

[option bit]

SPI master/ slave select [AFR1] UART1 data transmit [AFR1 and AFR0]

Timer 1 break input [AFR4]

ADC external trigger [AFR4]

To p le v e l interrupt [AFR3] Timer 1 inverted channel 1 [AFR7]

Analog input 2 [AFR2], Timer 1 inverted channel 2 [AFR7]

Timer 2 channel 1 [AFR0]

22/85 DS12129 Rev 3

STM8S001J3 Pinouts and pin descriptions

Table 5. STM8S001J3 pin description (continued)

Pin no.

SO8N

Pin name Type

PC6/ SPI_MOSI [TIM1_ CH1]

PD1/ SWIM

(5)

I/O X

I/O X X

Input Output

High

(1)

wpu

floating

(5)

X X HS O3 X X Port C6

(5)

sink

Ext. interr.

X HS O4 X X Port D1

OD PP

Speed

Main

function

(after

reset)

Default

alternate

function

SPI master out/slave in

SWIM data

interface

Alternate

function

after remap

[option bit]

Timer 1 channel 1 [AFR0]

Analog input

PD3/ AIN4/ TIM2_ CH2/ ADC_ ETR

I/O X

(5)

X X HS O3 X X Port D3

4/ Timer 2 channel 2/ADC external

trigger

PD5/ AIN5/ UART1 _TX

1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings.

2. By remapping UART1_TX (AFR0=1 and AFR1=1) to PA3 the UART1_RX alternate function on PD6 becomes unavailable. UART1 can be then used only in Single wire half-duplex mode or in Smartcard-reader emulation mode.

3. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is recommended d to use PA1 only in input mode if halt/active-halt is used in the application.

4. In the open-drain output column, “T” defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented). Although PB5 itself is a true open drain GPIO with its respective internal circuitry and characteristics, V maximum of the pin number 5 is limited by the standard GPIO PA3 which is also bonded to pin number 5.

5. The PD1 pin is in input pull-up during the reset phase and after internal reset release. This PD1 default state influences all GPIOs connected in parallel on pin# 8 (PC6, PD3, PD5).

I/O X

(5)

XX HS O3 XX Port D5

Analog input 5/ UART1 data transmit

Note: The PA2, PB0, PB1, PB2, PB3, PB6, PB7, PC1, PC2, PC7, PD0, PD2, PD4, PD7, PE5 and

PF4 GPIOs should be configured after device reset in output push-pull mode with output low-state to reduce the device’s consumption and to improve its EMC immunity. The GPIOs mentioned above are not connected to pins, and they are in input-floating mode after a device reset.

Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those

GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PD1 is also seen on PC6, PD3 and PD5. Push-pull configuration of PC3 is also seen on PC4 and PC5, etc.

DS12129 Rev 3 23/85

Pinouts and pin descriptions STM8S001J3

5.2 Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to the default alternate function is no longer available.

To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).

Section 8: Option bytes. When the remapping option is active,

24/85 DS12129 Rev 3

STM8S001J3 Memory and register map

6 Memory and register map

6.1 Memory map

Figure 4. Memory map

0x00 0000

0x00 03FF

0x00 0800

0x00 4000

0x00 407F

0x00 47FF

0x00 4800

0x00 480A 0x00 480B

0x00 4FFF

0x00 5000

0x00 57FF

0x00 5800

RAM

(1 Kbyte)

513 byte stack

Reserved

Data EEPROM

Reserved

Option bytes

Reserved

GPIO and periph. reg.

Reserved

0x00 7EFF

0x00 7F00

0x00 7FFF

0x00 8000

0x00 807F 0x00 8080

0x00 9FFF

0x00 A000

CPU/SWIM/debug/ITC

registers

32 interrupt vectors

Flash program memory

(8 Kbyte)

Reserved

0x02 7FFF

DS12129 Rev 3 25/85

MS36410V1

Memory and register map STM8S001J3

Tabl e 6 lists the boundary addresses for each memory size. The top of the stack is at the

RAM end address in each case.

Flash program memory 8 K 0x00 8000 0x00 9FFF

Data EEPROM 128 0x00 4000 0x00 407F

Table 6. Flash, Data EEPROM and RAM boundary addresses

Memory area Size (byte) Start address End address

RAM 1 K 0x00 0000 0x00 03FF

6.2 Register map

6.2.1 I/O port hardware register map

Address Block Register label Register name

0x00 5000

Table 7. I/O port hardware register map

Reset

status

PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xXX

0x00 5002 PA_DDR Port A data direction register 0x00

Port A

0x00 5003 PA_CR1 Port A control register 1 0x00

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0xXX

0x00 5007 PB_DDR Port B data direction register 0x00

Port B

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PB_IDR Port C input pin value register 0xXX

0x00 500C PC_DDR Port C data direction register 0x00

Port C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xXX

0x00 5011 PD_DDR Port D data direction register 0x00

Port D

0x00 5012 PD_CR1 Port D control register 1 0x02

(1)

0x00 5013 PD_CR2 Port D control register 2 0x00

26/85 DS12129 Rev 3

STM8S001J3 Memory and register map

Table 7. I/O port hardware register map (continued)

Address Block Register label Register name

0x00 5014

PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0xXX

0x00 5016 PE_DDR Port E data direction register 0x00

Port E

0x00 5017 PE_CR1 Port E control register 1 0x00

0x00 5018 PE_CR2 Port E control register 2 0x00

0x00 5019

PF_ODR Port F data output latch register 0x00

0x00 501A PF_IDR Port F input pin value register 0xXX

0x00 501B PF_DDR Port F data direction register 0x00

Port F

0x00 501C PF_CR1 Port F control register 1 0x00

0x00 501D PF_CR2 Port F control register 2 0x00

1. Depends on the external circuitry.

6.2.2 General hardware register map

Reset

status

(1)

DS12129 Rev 3 27/85

Memory and register map STM8S001J3

Address Block Register label Register name

0x00 501E to

0x00 5059

0x00 505A

Table 8. General hardware register map

Reset

status

Reserved area (60 byte)

FLASH_CR1 Flash control register 1 0x00

0x00 505B FLASH_CR2 Flash control register 2 0x00

0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF

0x00 505D FLASH _FPR Flash protection register 0x00

Flash

0x00 505E FLASH _NFPR Flash complementary protection register 0xFF

0x00 505F FLASH _IAPSR

0x00 5060 to

0x00 5061

0x00 5062 Flash FLASH _PUKR

Flash in-application programming status

Reserved area (2 byte)

Flash Program memory unprotection

0x00

0x00 5063 Reserved area (1 byte)

0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00

0x00 5065 to

0x00 509F

0x00 50A0

EXTI_CR1 External interrupt control register 1 0x00

Reserved area (59 byte)

ITC

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 to

0x00 50B2

Reserved area (17 byte)

0x00 50B3 RST RST_SR Reset status register 0xXX

0x00 50B4 to

0x00 50BF

0x00 50C0

CLK_ICKR Internal clock control register 0x01

Reserved area (12 byte)

CLK

0x00 50C1 CLK_ECKR External clock control register 0x00

0x00 50C2 Reserved area (1 byte)

0x00 50C3

CLK_CMSR Clock master status register 0xE1

0x00 50C4 CLK_SWR Clock master switch register 0xE1

0x00 50C5 CLK_SWCR Clock switch control register 0xXX

0x00 50C6 CLK_CKDIVR Clock divider register 0x18

CLK

0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF

0x00 50C8 CLK_CSSR Clock security system register 0x00

0x00 50C9 CLK_CCOR Configurable clock control register 0x00

0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF

0x00 50CB Reserved area (1 byte)

(1)

28/85 DS12129 Rev 3

STM8S001J3 Memory and register map

Table 8. General hardware register map (continued)

Address Block Register label Register name

0x00 50CC

CLK_HSITRIMR HSI clock calibration trimming register 0x00

CLK

0x00 50CD CLK_SWIMCCR SWIM clock control register

0x00 50CE to

0x00 50D0

0x00 50D1

WWDG_CR WWDG control register 0x7F

Reserved area (3 byte)

Reset

status

0bXXXX

XXX0

WWDG

0x00 50D2 WWDG_WR WWDR window register 0x7F

0x00 50D3 to

0x00 50DF

0x00 50E0

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

IWDG

IWDG_KR IWDG key register 0xXX

Reserved area (13 byte)

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3 to

0x00 50EF

0x00 50F0

0x00 50F1 AWU_APR AWU asynchronous prescaler buffer register 0x3F

AWU

AWU_CSR1 AWU control/status register 1 0x00

Reserved area (13 byte)

0x00 50F2 AWU_TBR AWU timebase selection register 0x00

(2)

0x00 50F3 to

0x00 50FF

0x00 5200

SPI_CR1 SPI control register 1 0x00

Reserved area (13 byte)

0x00 5201 SPI_CR2 SPI control register 2 0x00

0x00 5202 SPI_ICR SPI interrupt control register 0x00

0x00 5203 SPI_SR SPI status register 0x02

SPI

0x00 5204 SPI_DR SPI data register 0x00

0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07

0x00 5206 SPI_RXCRCR SPI Rx CRC register 0x00

0x00 5207 SPI_TXCRCR SPI Tx CRC register 0x00

0x00 5208 to

0x00 520F

0x00 5210

I2C_CR1 I2C control register 1 0x00

Reserved area (8 byte)

0x00 5211 I2C_CR2 I2C control register 2 0x00

0x00 5212 I2C_FREQR I2C frequency register 0x00

I2C

0x00 5213 I2C_OARL I2C own address register low 0x00

0x00 5214 I2C_OARH I2C own address register high 0x00

0x00 5215 Reserved

DS12129 Rev 3 29/85

Memory and register map STM8S001J3

Table 8. General hardware register map (continued)

Address Block Register label Register name

0x00 5216

0x00 5217 I2C_SR1 I2C status register 1 0x00

0x00 5218 I2C_SR2 I2C status register 2 0x00

0x00 5219 I2C_SR3 I2C status register 3 0x00

0x00 521A I2C_ITR I2C interrupt control register 0x00

0x00 521B I2C_CCRL I2C clock control register low 0x00

0x00 521C I2C_CCRH I2C clock control register high 0x00

0x00 521D I2C_TRISER I2C TRISE register 0x02

0x00 521E I2C_PECR I2C packet error checking register 0x00

0x00 521F to

0x00 522F

0x00 5230

0x00 5231 UART1_DR UART1 data register 0xXX

0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00

0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00

0x00 5234 UART1_CR1 UART1 control register 1 0x00

0x00 5235 UART1_CR2 UART1 control register 2 0x00

I2C

UART1

I2C_DR I2C data register 0x00

Reserved area (17 byte)

UART1_SR UART1 status register 0xC0

Reset

status

0x00 5236 UART1_CR3 UART1 control register 3 0x00

0x00 5237 UART1_CR4 UART1 control register 4 0x00

0x00 5238 UART1_CR5 UART1 control register 5 0x00

0x00 5239 UART1_GTR UART1 guard time register 0x00

0x00 523A UART1_PSCR UART1 prescaler register 0x00

0x00 523B to

0x00 523F

0x00 523B to

0x00523F

Reserved area (5 bytes)

Reserved area (21 byte)

30/85 DS12129 Rev 3

STM8S001J3 Memory and register map

Table 8. General hardware register map (continued)

Address Block Register label Register name

0x00 5250

TIM1_CR1 TIM1 control register 1 0x00

Reset

status

0x00 5251 TIM1_CR2 TIM1 control register 2 0x00

0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00

0x00 5253 TIM1_ETR TIM1 external trigger register 0x00

0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00

0x00 5255 TIM1_SR1 TIM1 status register 1 0x00

0x00 5256 TIM1_SR2 TIM1 status register 2 0x00

0x00 5257 TIM1_EGR TIM1 event generation register 0x00

0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00

0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00

0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00

0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00

0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0x00

0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0x00

0x00 525E TIM1_CNTRH TIM1 counter high 0x00

0x00 525F TIM1_CNTRL TIM1 counter low 0x00

TIM1

0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00

0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00

0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF

0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF

0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00

0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00

0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00

0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00

0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00

0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00

0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00

0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00

0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00

0x00 526D TIM1_BKR TIM1 break register 0x00

0x00 526E TIM1_DTR TIM1 dead-time register 0x00

0x00 526F TIM1_OISR TIM1 output idle state register 0x00

0x00 5270 to

0x00 52FF

Reserved area (147 byte)

DS12129 Rev 3 31/85

Memory and register map STM8S001J3

Table 8. General hardware register map (continued)

Address Block Register label Register name

0x00 5300

0x00 5301 Reserved

0x00 5302 Reserved

0x00 5303 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5304 TIM2_SR1 TIM2 status register 1 0x00

0x00 5305 TIM2_SR2 TIM2 status register 2 0x00

0x00 5306 TIM2_EGR TIM2 event generation register 0x00

0x00 5307 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 5308 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 5309 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00

0x00 530A TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

0x00 530B TIM2_CCER2 TIM2 capture/compare enable register 2 0x00

0x00 530C TIM2_CNTRH TIM2 counter high 0x00

0x00 530D TIM2_CNTRL TIM2 counter low 0x00

0x00 530E TIM2_PSCR TIM2 prescaler register 0x00

0x00 530F TIM2_ARRH TIM2 auto-reload register high 0xFF

0x00 5310 TIM2_ARRL TIM2 auto-reload register low 0xFF

TIM2

TIM2_CR1 TIM2 control register 1 0x00

Reset

status

0x00 5311 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5312 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5313 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0x00

0x00 5314 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5315 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00

0x00 5316 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00

0x00 5317 to

0x00 533F

0x00 5340

0x00 5341 Reserved

0x00 5342 Reserved

0x00 5343 TIM4_IER TIM4 interrupt enable register 0x00

0x00 5344 TIM4_SR TIM4 status register 0x00

0x00 5345 TIM4_EGR TIM4 event generation register 0x00

0x00 5346 TIM4_CNTR TIM4 counter 0x00

0x00 5347 TIM4_PSCR TIM4 prescaler register 0x00

0x00 5348 TIM4_ARR TIM4 auto-reload register 0xFF

TIM4

TIM4_CR1 TIM4 control register 1 0x00

Reserved area (43 byte)

32/85 DS12129 Rev 3

STM8S001J3 Memory and register map

Table 8. General hardware register map (continued)

Address Block Register label Register name

0x00 5349 to

0x00 53DF

0x00 53E0 to

0x00 53F3

0x00 53F4 to

0x00 53FF

0x00 5400

ADC1 ADC_DBxR ADC data buffer registers 0x00

ADC _CSR ADC control/status register 0x00

Reserved area (153 byte)

Reserved area (12 byte)

Reset

status

0x00 5401 ADC_CR1 ADC configuration register 1 0x00

0x00 5402 ADC_CR2 ADC configuration register 2 0x00

0x00 5403 ADC_CR3 ADC configuration register 3 0x00

0x00 5404 ADC_DRH ADC data register high 0xXX

0x00 5405 ADC_DRL ADC data register low 0xXX

0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00

0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00

ADC1

0x00 5408 ADC_HTRH ADC high threshold register high 0x03

0x00 5409 ADC_HTRL ADC high threshold register low 0xFF

0x00 540A ADC_LTRH ADC low threshold register high 0x00

0x00 540B ADC_LTRL ADC low threshold register low 0x00

0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00

0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00

0x00 540E ADC_AWCRH ADC analog watchdog control register high 0x00

0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00

0x00 5410 to

0x00 57FF

1. Depends on the previous reset source.

2. Write only register.

Reserved area (1008 byte)

DS12129 Rev 3 33/85

Memory and register map STM8S001J3

6.2.3 CPU/SWIM/debug module/interrupt controller registers

Table 9. CPU/SWIM/debug module/interrupt controller registers

Address Block Register Label Register Name

0x00 7F00

A Accumulator 0x00

Reset

Status

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x00

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

(1)

0x00 7F05 XL X index register low 0x00

CPU

0x00 7F06 YH Y index register high 0x00

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CCR Condition code register 0x28

0x00 7F0B to

0x00 7F5F

Reserved area (85 byte)

0x00 7F60 CPU CFG_GCR Global configuration register 0x00

0x00 7F70

ITC_SPR1 Interrupt software priority register 1 0xFF

0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF

0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF

ITC

0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF

0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF

0x00 7F78 to

0x00 7F79

Reserved area (2 byte)

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81 to

0x00 7F8F

Reserved area (15 byte)

34/85 DS12129 Rev 3

STM8S001J3 Memory and register map

Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Register Label Register Name

0x00 7F90

DM_BK1RE DM breakpoint 1 register extended byte 0xFF

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF

0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF

0x00 7F96 DM_CR1 DM debug module control register 1 0x00

0x00 7F97 DM_CR2 DM debug module control register 2 0x00

0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B to

0x00 7F9F

1. Accessible by debug module only

Reserved area (5 byte)

Reset

Status

DS12129 Rev 3 35/85

Interrupt vector mapping STM8S001J3

7 Interrupt vector mapping

IRQ

no.

Source

block

Description

Table 10. Interrupt mapping

Wakeup from

Halt mode

Wakeup from

Active-halt mode

Vector address

- RESET Reset Yes Yes 0x00 8000

- TRAP Software interrupt - - 0x00 8004

0 TLI External top level interrupt - - 0x00 8008

1 AWU Auto wake up from halt - Yes 0x00 800C

2 CLK Clock controller - - 0x00 8010

3 EXTI0 Port A external interrupts Yes

(1)

Yes

(1)

0x00 8014

4 EXTI1 Port B external interrupts Yes Yes 0x00 8018

5 EXTI2 Port C external interrupts Yes Yes 0x00 801C

6 EXTI3 Port D external interrupts Yes Yes 0x00 8020

7 EXTI4 Port E external interrupts Yes Yes 0x00 8024

8 - Reserved 0x00 8028

9 - Reserved 0x00 802C

10 SPI End of transfer Yes Yes 0x00 8030

11 TI M1

TIM1 update/overflow/underflow/ trigger/break

- - 0x00 8034

12 TIM1 TIM1 capture/compare - - 0x00 8038

13 TIM2 TIM2 update /overflow - - 0x00 803C

14 TIM2 TIM2 capture/compare - - 0x00 8040

15 - Reserved 0x00 8044

16 - Reserved 0x00 8048

17 UART1 Tx complete - - 0x00 804C

18 UART1 Receive register DATA FULL - - 0x00 8050

19 I2C I2C interrupt Yes Yes 0x00 8054

20 - Reserved 0x00 8058

21 - Reserved 0x00 805C

22 ADC1

ADC1 end of conversion/analog watchdog interrupt

- - 0x00 8060

23 TIM4 TIM4 update/overflow - - 0x00 8064

24 Flash EOP/WR_PG_DIS - - 0x00 8068

Reserved

1. Except PA1

0x00 806C to

0x00 807C

36/85 DS12129 Rev 3

STM8S001J3 Option bytes

8 Option bytes

Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures.

Table 11: Option bytes below. Option bytes can also be modified ‘on the fly’ by the

Table 11. Option bytes

Addr.

0x4800

0x4801

0x4802 NOPT1 NUBC[7:0] 0xFF

0x4803 Alternate

0x4804 NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF

0x4805

0x4806 NOPT3 Reserved

0x4807

0x4808 NOPT4 Reserved

0x4809

0x480A NOPT5 NHSECNT[7:0] 0xFF

Option

name

Read-out protection (ROP)

User boot code (UBC)

function remapping (AFR)

Misc. option

Clock option

HSE clock startup

Option

byte no.

OPT0 ROP[7:0] 0x00

OPT1 UBC[7:0] 0x00

OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00

OPT3 Reserved HSITRIM

OPT4 Reserved

OPT5 HSECNT[7:0] 0x00

76543210

Table 12. Option byte description

Option bits Factory

default setting

NHSI TRIM

LSI

_EN

NLSI

_EN

EXT CLK

CLK

IWDG

_HW

NIWDG

_HW

CKAWU

SEL

NCKAW

USEL

WWDG

_HW

NWWDG

_HW

PRS

NPR SC1

WWDG

_HALT

NWWDG

_HALT

PRS

NPR

SC0

0x00

0xFF

0x00

0xFF

Option byte no. Description

ROP[7:0] Memory readout protection (ROP)

OPT0

0xAA: Enable readout protection (write access via SWIM protocol)

Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details.

DS12129 Rev 3 37/85

Option bytes STM8S001J3

Table 12. Option byte description (continued)

Option byte no. Description

UBC[7:0] User boot code area

0x00: no UBC, no write-protection 0x01: Pages 0 defined as UBC, memory write-protected 0x02: Pages 0 to 1 defined as UBC, memory write-protected

OPT1

OPT2

OPT3

Page 0 and page 1 contain the interrupt vectors. ... 0x7F: Pages 0 to 126 defined as UBC, memory write-protected Other values: Pages 0 to 127 defined as UBC, memory-write protected.

Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details.

AFR[7:0]

Refer to the following section for alternate function remapping descriptions of bits [7:2] and [1:0] respectively.

HSITRIM: high-speed internal clock trimming register size

0: 3-bit trimming supported in CLK_HSITRIMR register 1: 4-bit trimming supported in CLK_HSITRIMR register

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware

OPT4

OPT5

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN

CKAWUSEL: Auto wakeup unit/clock

0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU

PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilization time. 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles

38/85 DS12129 Rev 3

STM8S001J3 Option bytes

8.1 Alternate function remapping bits

Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices

Option byte number Description

AFR7Alternate function remapping option 7

0: AFR7 remapping option inactive: default alternate function 1: Port C3 alternate function = TIM1_CH1N; port C4 alternate function = TIM1_CH2N.

AFR6 Alternate function remapping option 6

Reserved.

AFR5 Alternate function remapping option 5

Reserved.

AFR4 Alternate function remapping option 4

0: AFR4 remapping option inactive: default alternate function 1: Port B4 alternate function = ADC_ETR; port B5 alternate function = TIM1_BKIN.

AFR3 Alternate function remapping option 3

OPT2

0: AFR3 remapping option inactive: default alternate function 1: Port C3 alternate function = TLI.

AFR2 Alternate function remapping option 2

0: AFR2 remapping option inactive: default alternate function 1: Port C4 alternate function = AIN2.

AFR1 Alternate function remapping option 1

0: AFR1 remapping option inactive: default alternate function 1: If AFR0=0: Port A3 alternate function = SPI_NSS.

If AFR0=1: Port A3 alternate function = UART_TX; port D6 alternate function UART_RX unavailable.

AFR0 Alternate function remapping option 0

0: AFR0 remapping option inactive: Default alternate functions 1: Port C5 alternate function = TIM2_CH1; port C6 alternate function = TIM1_CH1.

1. Refer to the pinout description.

2. Do not use more than one remapping option in the same port.

(2)

(1)

DS12129 Rev 3 39/85

Electrical characteristics STM8S001J3

50 pF

STM8 pin

9 Electrical characteristics

9.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

9.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3

9.1.2 Typical values

= 25 °C and TA = T

Σ).

Amax

(given by

Unless otherwise specified, typical data are based on TA = 25 °C, V only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

9.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

9.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

(mean ± 2 Σ).

Figure 5. Pin loading conditions

= 5 V. They are given

9.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

40/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

STM8 pin

Figure 6. Pin input voltage

9.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Tab le 14: Voltage characteristics,

Tabl e 15: Current characteristics, and Tab le 16: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 14. Voltage characteristics

Symbol Ratings Min Max Unit

- VSSSupply voltage

DDx

Input voltage on true open drain pins

Input voltage on any other pin

(1)

(2)

-0.3 6.5

- 0.3 6.5

- 0.3 V

+ 0.3

see Absolute maximum

ESD

Electrostatic discharge voltage

ratings (electrical

sensitivity) on page 75

1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply

2. I

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I injection is induced by V there is no positive injection current, and the corresponding V

while a negative injection is induced by VIN<VSS. For true open-drain pads,

IN>VDD

maximum must always be respected

value. A positive

INJ(PIN)

DS12129 Rev 3 41/85

Electrical characteristics STM8S001J3

Symbol Ratings Max.

VDD

VSS

Total current into V

Total current out of V

Table 15. Current characteristics

power lines (source)

ground lines (sink)

(2)

(1)

100

Output current sunk by any I/O and control pin 20

(3)(4)

INJ(PIN)

ΣI

INJ(PIN)

1. Guaranteed by characterization results.

2. All power (VDD) and ground (VSS) pins must always be connected to the external supply.

3. I

4. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins

5. When several inputs are submitted to a current injection, the maximum ΣI

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I injection is induced by V there is no positive injection current, and the corresponding VIN maximum must always be respected

should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I

ΣI

INJ(PIN)

positive and negative injected currents (instantaneous values). These results are based on characterization with

INJ(PIN)

Output current source by any I/Os and control pin -20

Injected current on OSCIN pin ±4

Injected current on any other pin

(3)

Total injected current (sum of all I/O and control pins)

while a negative injection is induced by VIN<VSS. For true open-drain pads,

IN>VDD

in the I/O port pin characteristics section does not affect the ADC accuracy.

maximum current injection on four I/O port pins of the device.

(5)

INJ(PIN)

is the absolute sum of the

INJ(PIN)

±4

±20

value. A positive

INJ(PIN)

Unit

and

Table 16. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range -65 to 150

Maximum junction temperature 150

°C

42/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

2.95

4.0

5.0

5.5

CPU (MHz)

Functionality guaranteed

A -40 to 125 °C

Supply voltage

MSv46305V1

Functionality not guaranteed in this area

9.3 Operating conditions

The device must be used in operating conditions that respect the parameters in Tab le 17. In addition, full account must be taken of all physical capacitor characteristics and tolerances.

Symbol Parameter Conditions Min Max Unit

Table 17. General operating conditions

CPU

CAP

Internal CPU clock frequency - 0 16 MHz

Standard operating voltage - 2.95 5.5 V

: capacitance of external

EXT

capacitor

(1)

ESR of external capacitor

At 1 MHz

- 470 3300 nF

(2)

-0.3ohm

ESL of external capacitor - 15 nH

Power dissipation at

(3)

TA = 125° C

Ambient temperature Maximum power dissipation -40 125

Junction temperature range - -40 130

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter must be respected for the full application range.

2. This frequency of 1 MHz as a condition for V

3. To calculate P

characteristics on page 79) with the value for T Table 49: Thermal characteristics.

), use the formula P

Dmax(TA

Figure 7. f

SO8N - 49 mW

parameters is given by the design of the internal regulator.

CAP

= (T

Dmax

- TA)/Θ

Jmax

given in Table 17 above and the value for Θ

Jmax

CPUmax

versus VDD

(see Section 10.2: Thermal

given in

°C

DS12129 Rev 3 43/85

Electrical characteristics STM8S001J3

Table 18. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ

VDD rise time rate - 2 - ∞

VDD

TEMP

IT+

IT-

HYS(BOR)

1. Reset is always generated after a t minimum operating voltage (V

fall time rate

Reset release delay

Power-on reset threshold

Brown-out reset threshold

Brown-out reset hysteresis

(1)

delay. The application must ensure that VDD is still above the

TEMP

min) when the t

-2-∞

rising - - 1.7 ms

-2.62.72.85V

- 2.5 2.65 2.8 V

--70-mV

delay has elapsed.

TEMP

Max Unit

µs/V

44/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

MSv36488V1

ESR

RLeak

ESL

9.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor C V

CAP

pin. C

is specified in Table 17. Care should be taken to limit the series inductance

EXT

to less than 15 nH.

Figure 8. External capacitor C

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

9.3.2 Supply current characteristics

The current consumption is measured as described in Section 9.1.5: Pin input voltage.

Total current consumption in run mode

The MCU is placed under the following conditions:

• All I/O pins in input mode with a static value at VDD or VSS (no load)

• All peripherals are disabled (clock stopped by Peripheral Clock Gating registers)

except if explicitly mentioned.

EXT

to the

Subject to general operating conditions for VDD and TA.

Table 19. Total current consumption with code execution in run mode at VDD = 5 V

Symbol Parameter Conditions Typ Max

= f

CPU

MASTER

Supply current in run mode,

CPU

= f

MASTER

code

DD(RUN)

executed from RAM

= f

CPU

MASTER

15.625 kHz

= f

CPU

MASTER

= f

CPU

MASTER

Supply current in run mode, code executed from Flash

1. Guaranteed by characterization results.

= f

CPU

MASTER

= f

CPU

MASTER

= f

CPU

MASTER

15.625 kHz

= f

CPU

MASTER

= 16 MHz

/128 = 125 kHz

/128 =

= 128 kHz LSI RC osc. (128 kHz) 0.41 0.55

= 16 MHz

= 2 MHz HSI RC osc. (16 MHz/8)

/128 = 125 kHz HSI RC osc. (16 MHz) 0.72 0.9

/128 =

= 128 kHz LSI RC osc. (128 kHz) 0.42 0.57

HSE user ext. clock (16 MHz) 2 2.35

HSI RC osc. (16 MHz) 1.7 2

HSE user ext. clock (16 MHz) 0.86 -

HSI RC osc. (16 MHz) 0.7 0.87

HSI RC osc. (16 MHz/8) 0.46 0.58

HSE user ext. clock (16 MHz) 4.3 4.75

HSI RC osc.(16 MHz) 3.7 4.5

(2)

0.84 1.05

HSI RC osc. (16 MHz/8) 0.46 0.58

(1)

Unit

DS12129 Rev 3 45/85

Electrical characteristics STM8S001J3

2. Default clock configuration measured with all peripherals off.

Table 20. Total current consumption with code execution in run mode at VDD = 3.3 V

Symbol Parameter Conditions Typ Max

(1)

Unit

CPU

= f

MASTER

= 16 MHz Supply current in

run mode,

CPU

= f

MASTER

/128 = 125 kHz

code

DD(RUN)

executed from RAM

= f

CPU

MASTER

15.625 kHz

= f

CPU

MASTER

= f

CPU

MASTER

/128 =

= 128 kHz LSI RC osc. (128 kHz) 0.41 0.55

= 16 MHz

Supply current in run mode, code executed from Flash

1. Guaranteed by characterization results.

2. Default clock configuration, measured with all peripherals off.

= f

CPU

MASTER

= f

CPU

MASTER

= f

CPU

MASTER

15.625 kHz

= f

CPU

MASTER

= 2 MHz HSI RC osc. (16 MHz/8)

/128 = 125 kHz HSI RC osc. (16 MHz) 0.72 0.9

/128 =

= 128 kHz LSI RC osc. (128 kHz) 0.42 0.57

HSE user ext. clock (16 MHz) 2 2.3

HSI RC osc. (16 MHz) 1.5 2

HSE user ext. clock (16 MHz) 0.81 -

HSI RC osc. (16 MHz) 0.7 0.87

HSI RC osc. (16MHz/8) 0.46 0.58

HSE user ext. clock (16 MHz) 3.9 4.7

HSI RC osc. (16 MHz) 3.7 4.5

(2)

0.84 1.05

HSI RC osc. (16 MHz/8) 0.46 0.58

46/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Total current consumption in wait mode

Table 21. Total current consumption in wait mode at VDD = 5 V

Symbol Parameter Conditions Typ Max

(1)

Unit

= f

CPU

MASTER

DD(WFI)

Supply current in wait mode

CPU

= f

MASTER

15.625 kHz

= f

CPU

MASTER

1. Guaranteed by characterization results.

2. Default clock configuration measured with all peripherals off.

Table 22. Total current consumption in wait mode at VDD = 3.3 V

= 16 MHz

HSI RC osc. (16 MHz) 0.89 1.1

/128 = 125 kHz HSI RC osc. (16 MHz) 0.7 0.88

/128 =

HSI RC osc. (16 MHz/8)

(2)

0.45 0.57

= 128 kHz LSI RC osc. (128 kHz) 0.4 0.54

Symbol Parameter Conditions Typ Max

HSE user ext. clock (16 MHz) 1.1 1.3

= f

CPU

MASTER

DD(WFI)

Supply current in wait mode

= f

CPU

MASTER

= f

CPU

MASTER

15.625 kHz

= f

CPU

MASTER

15.625 kHz

1. Guaranteed by characterization results.

2. Default clock configuration measured with all peripherals off.

= 16 MHz

HSI RC osc. (16 MHz) 0.89 1.1

/128 = 125 kHz HSI RC osc. (16 MHz) 0.7 0.88

/128 =

HSI RC osc. (16 MHz/8)

LSI RC osc. (128 kHz) 0.4 0.54

(2)

0.45 0.57

(1)

Unit

DS12129 Rev 3 47/85

Electrical characteristics STM8S001J3

Total current consumption in active halt mode

Table 23. Total current consumption in active halt mode at VDD = 5 V

Conditions

Symbol Parameter

Supply current

DD(AH)

in active halt mode

Main

voltage

regulator

(2)

(MVR)

Flash mode

(3)

Operating mode

Power-down mode

Clock source

HSE user external clock (16 MHz)

LSI RC oscillator (128 kHz)

HSE user external clock (16 MHz)

LSI RC oscillator (128 kHz)

Max at

Typ

85°C

1030 - -

200 260 300

970 - -

150 200 230

(1)

Max at

125°C

(1)

Unit

µA

Operating mode

Off

Power-down mode

1. Guaranteed by characterization results.

2. Configured by the REGAH bit in the CLK_ICKR register.

3. Configured by the AHALT bit in the FLASH_CR1 register.

Table 24. Total current consumption in active halt mode at VDD = 3.3 V

Conditions

Symbol Parameter

Main voltage

regulator

(2)

(MVR)

Flash mode

Operating mode

Power-down mode

DD(AH)

Supply current in active halt mode

Operating mode

Off

Power-down mode

1. Guaranteed by characterization results.

2. Configured by the REGAH bit in the CLK_ICKR register.

3. Configured by the AHALT bit in the FLASH_CR1 register.

LSI RC oscillator

66 85 110

(128 kHz)

(3)

Clock source

HSE user external clock (16 MHz)

10 20 40

Typ

550 - -

LSI RC osc. (128 kHz) 200 260 290

HSE user external clock(16 MHz)

970 - -

LSI RC osc. (128 kHz) 150 200 230

66 80 105

LSI RC osc. (128 kHz)

10 18 35

Max

85°

(1)

Max

125°

(1)

Unit

µA

48/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Total current consumption in halt mode

Table 25. Total current consumption in halt mode at VDD = 5 V

Max at

(1)

Max at

125°C

Max at

125°

Symbol Parameter Conditions Typ

DD(H)

1. Guaranteed by characterization results.

Supply current in halt mode

Table 26. Total current consumption in halt mode at VDD = 3.3 V

Flash in operating mode, HSI clock after wakeup

Flash in power-down mode, HSI clock after wakeup

63 75 105

6.0 20 55

Symbol Parameter Conditions Typ

Flash in operating mode, HSI clock after wakeup

DD(H)

Supply current in halt mode

Flash in power-down mode, HSI clock after wakeup

1. Guaranteed by characterization results.

Max at

(1)

85°C

85° C

60 75 100

4.5 17 30

Low-power mode wakeup times

Symbol Parameter Conditions Typ Max

WU(WFI)

WU(AH)

WU(H)

1. Guaranteed by design.

2. t

WU(WFI)

3. Measured from interrupt event to interrupt vector fetch.

4. Configured by the REGAH bit in the CLK_ICKR register.

5. Configured by the AHALT bit in the FLASH_CR1 register.

6. Plus 1 LSI clock depending on synchronization.

Wakeup time from wait mode to run mode

Wakeup time active halt mode to run mode.

Wakeup time from halt mode to run mode

= 2 x 1/f

master

+ 7 x 1/f

(3)

CPU

Table 27. Wakeup times

0 to 16 MHz - -

= f

CPU

MASTER

MVR voltage

regulator on

MVR voltage

regulator off

Flash in operating mode

Flash in power-down mode

= 16 MHz. 0.56 -

Flash in operating

(5)

mode

(4)

Flash in power-down

(5)

mode

Flash in operating

(5)

mode

(4)

Flash in power-down

(5)

mode

(5)

HSI (after wakeup)

(6)

52 -

54 -

(1)

(2)

(6)

Unit

µA

Unit

µA

Unit

µs

DS12129 Rev 3 49/85

Electrical characteristics STM8S001J3

Total current consumption and timing in forced reset state

Table 28. Total current consumption and timing in forced reset state

Symbol Parameter Conditions Typ Max

(1)

Unit

DD(R)

RESETBL

1. Guaranteed by design.

2. Characterized with all I/Os tied to V

Supply current in reset state

Reset release to vector fetch - - 150 µs

Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.

HSI internal RC/f

Symbol Parameter Typ. Unit

DD(TIM1)

DD(TIM2)

DD(TIM4)

DD(UART1)

DD(SPI)

DD(I2C)

DD(ADC1)

1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

TIM1 supply current

TIM2 supply current

TIM4 timer supply current

UART1 supply current

SPI supply current

I2C supply current

ADC1 supply current when converting

VDD = 5 V 400 -

= 3.3 V 300 -

= 16 MHz, VDD = 5 V.

CPU

= f

(2)

MASTER

Table 29. Peripheral current consumption

(1)

130

(1)

120

(1)

µA

210

µA

1000

50/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Current consumption curves

The following figures show the typical current consumption measured with code executing in RAM.

Figure 9. Typ. I

Figure 10. Typ. I

DD(RUN)

vs VDD, HSE user external clock, f

vs f

, HSE user external clock, VDD = 5 V

CPU

= 16 MHz

CPU

DS12129 Rev 3 51/85

Electrical characteristics STM8S001J3

Figure 11. Typ. I

DD(RUN)

vs VDD, HSI RC osc, f

= 16 MHz

CPU

Figure 12. Typ. I

DD(WFI)

vs. VDD HSE user external clock, f

= 16 MHz

CPU

52/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Figure 13. Typ. I

Figure 14. Typ. I

DD(WFI)

vs. f

, HSE user external clock, VDD = 5 V

CPU

vs VDD, HSI RC osc, f

CPU

= 16 MHz

DS12129 Rev 3 53/85

Electrical characteristics STM8S001J3

HSEH

HSEL

External clock source

OSCIN

HSE

STM8

MS36489V2

9.3.3 External clock sources and timing characteristics

HSE user external clock

Subject to general operating conditions for VDD and TA.

Symbol Parameter Conditions Min Typ Max Unit

Table 30. HSE user external clock characteristics

HSE_ext

HSEH

HSEL

LEAK_HSE

1. Guaranteed by characterization results.

User external clock source frequency

OSCIN input pin high level

(1)

voltage

OSCIN input pin low level

(1)

voltage

OSCIN input leakage current

Figure 15. HSE external clock source

0-16MHz

0.7 x V

-V

+ 0.3 V

< V

-1 - +1 µA

- 0.3 x V

9.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA.

54/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

High speed internal RC oscillator (HSI)

Symbol Parameter Conditions Min Typ Max Unit

Table 31. HSI oscillator characteristics

Frequency - - 16 - MHz

HSI

Accuracy of HSI oscillator

ACC

HSI

Accuracy of HSI oscillator (factory calibrated)

su(HSI)

DD(HSI)

1. See the application note.

2. Guaranteed by design.

3. Guaranteed by characterization results.

HSI oscillator wakeup time including calibration

HSI oscillator power consumption

Figure 16. Typical HSI frequency variation vs VDD at 4 temperatures

User-trimmed with the CLK_HSITRIMR register for given V conditions

= 5 V, TA = 25 °C -2.5 - 1.5

= 5 V,

(1)

and TA

-40 °C ≤ TA ≤ 125 °C

--1.0

-5 - 5

- - - 1.0

- - 170 250

(2)

(3)

µs

µA

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDD and TA.

Symbol Parameter Conditions Min Typ Max Unit

Frequency - - 128 - kHz

LSI

Table 32. LSI oscillator characteristics

DS12129 Rev 3 55/85

Electrical characteristics STM8S001J3

Table 32. LSI oscillator characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

su(LSI)

DD(LSI)

1. Guaranteed by design.

LSI oscillator wakeup time - - - 7

LSI oscillator power consumption - - 5 - µA

(1)

µs

Figure 17. Typical LSI frequency variation vs VDD @ 4 temperatures

56/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

9.3.5 Memory characteristics

RAM and hardware registers

Symbol Parameter Conditions Min Unit

1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design.

2. Refer to Table 18 on page 44 for the value of V

Flash program memory and data EEPROM

General conditions: TA = -40 to 85 °C.

Symbol Parameter Conditions Min

Table 34. Flash program memory and data EEPROM

Table 33. RAM and hardware registers

Data retention mode

(1)

IT-max

Halt mode (or reset) V

(2)

IT-max

(1)

Typ Max Unit

Operating voltage

(all modes, execution/write/erase)

≤ 16 MHz 2.95 - 5.5 V

CPU

Standard programming time (including

prog

erase

erase) for byte/word/block (1 byte/4 bytes/64 bytes)

Fast programming time for 1 block (64 bytes)

Erase time for 1 block (64 bytes) - - 3.0 3.3 ms

Erase/write cycles

(2)

(program memory)

(2)

Erase/write cycles (data memory)

--6.06.6ms

--3.03.3ms

100 - -

TA = 85 °C

100 k - -

Data retention (program memory)

RET

after 100 erase/write cycles at T

= 85 °C

Data retention (data memory) after 10 k erase/write cycles at TA = 85 °C

RET

= 55° C

20 - -

Data retention (data memory) after

= 85° C 1.0 - -

100 k erase/write cycles at

= 125 °C

Supply current (Flash programming or

erasing for 1 to 128 bytes)

1. Guaranteed by characterization results.

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.

RET

--2.0-mA

cycles

years

DS12129 Rev 3 57/85

Electrical characteristics STM8S001J3

9.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor.

Symbol Parameter Conditions Min Typ Max Unit

Input low level

voltage

Input high level

voltage

tR, t

Hysteresis

hys

Pull-up resistor VDD = 5 V, V

Rise and fall time

(10% - 90%)

(1)

Input leakage

current,

lkg

analog and digital

lkg ana

lkg(inj)

Analog input leakage current

Leakage current in adjacent I/O

Table 35. I/O static characteristics

-0.3 - 0.3 x V

= 5 V

0.7 x V

-700- mV

= V

Fast I/Os Load = 50 pF

Standard and high sink I/Os Load = 50 pF

≤ V

30 55 80 kΩ

--20

- - 125

--±1µA

--±250

Injection current ±4 mA - - ±1

-VDD + 0.3 V V

(2)

(3)

µA

1. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

2. Guaranteed by design.

3. Guaranteed by characterization results.

58/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Figure 18. Typical VIL and VIH vs VDD @ 4 temperatures

Figure 19. Typical pull-up resistance vs V

@ 4 temperatures

DS12129 Rev 3 59/85

Electrical characteristics STM8S001J3

Figure 20. Typical pull-up current vs VDD @ 4 temperatures

1. The pull-up is a pure resistor (slope goes through 0).

Table 36. Output driving current (standard ports)

Symbol Parameter Conditions Min Max Unit

Output low level with 4 pins sunk I

Output high level with 8 pins sourced IIO = 10 mA, V

Output high level with 4 pins sourced I

1. Guaranteed by characterization results.

Output low level with 8 pins sunk I

Table 37. Output driving current (true open drain ports)

= 10 mA, V

= 4 mA, V

= 5 V - 2

= 3.3 V - 1

= 5 V 2.8 -

= 3.3 V 2.1

(1)

Symbol Parameter Conditions Max Unit

1. Guaranteed by characterization results.

Output low level with 2 pins sunk

= 10 mA, V

IIO = 20 mA, V

= 5 V 1

= 3.3 V 1.5

= 5 V 2

(1)

60/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Table 38. Output driving current (high sink ports)

Symbol Parameter Conditions Min Max Unit

Output low level with 8 pins sunk IIO = 10 mA, V

Output low level with 4 pins sunk I

Output low level with 4 pins sunk IIO = 20 mA, V

Output high level with 8 pins sourced IIO = 10 mA, V

Output high level with 4 pins sourced I

1. Guaranteed by characterization results.

= 10 mA, V

= 20 mA, V

= 5 V - 0.8

= 3.3 V - 1.0

= 5 V - 1.5

= 5 V 4.0 -

= 3.3 V 2.1

= 5 V 3.3

(1)

Typical output level curves

Figure 22 to Figure 29 show typical output level curves measured with output on a single

pin.

Figure 21. Typ. VOL @ VDD = 5 V (standard ports)

DS12129 Rev 3 61/85

Electrical characteristics STM8S001J3

Figure 22. Typ. VOL @ VDD = 3.3 V (standard ports)

Figure 23. Typ. V

@ VDD = 5 V (true open drain ports)

62/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Figure 24. Typ. VOL @ VDD = 3.3 V (true open drain ports)

Figure 25. Typ. V

@ VDD = 5 V (high sink ports)

DS12129 Rev 3 63/85

Electrical characteristics STM8S001J3

Figure 26. Typ. VOL @ VDD = 3.3 V (high sink ports)

Figure 27. Typ. V

DD - VOH

@ VDD = 5 V (standard ports)

64/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Figure 28. Typ. V

Figure 29. Typ. V

DD - VOH

@ VDD = 3.3 V (standard ports)

@ VDD = 5 V (high sink ports)

DS12129 Rev 3 65/85

Electrical characteristics STM8S001J3

9.3.7

Figure 30. Typ. V

DD - VOH

@ VDD = 3.3 V (high sink ports)

SPI serial peripheral interface

Unless otherwise specified, the parameters given in Tab le 39 are derived from tests performed under ambient temperature, f conditions. t

MASTER

= 1/f

MASTER

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 39. SPI characteristics

frequency and VDD supply voltage

Symbol Parameter Conditions Min Max Unit

Master mode 0 8

MHz

Slave mode 0 7

1/t

SCK

c(SCK)

SPI clock frequency

66/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Table 39. SPI characteristics (continued)

Symbol Parameter Conditions Min Max Unit

r(SCK)

f(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

1. Values based on design simulation and/or characterization results, and not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

SPI clock rise and fall time Capacitive load: C = 30 pF - 25

(1)

NSS setup time Slave mode 4 x t

(1)

NSS hold time Slave mode 70 -

(1)

SCK high and low time Master mode t

(1)

Data input setup time

(1)

Data input hold time

(1)

(1)(2)

Data output access time Slave mode - 3 x t

(1)(3)

Data output disable time Slave mode 25 -

(1)

Data output valid time Slave mode (after enable edge) - 65

(1)

Data output valid time Master mode (after enable edge) - 30

(1)

Data output hold time

(1)

Master mode 5 -

Slave mode 5 -

Master mode 7 -

Slave mode 10 -

Slave mode (after enable edge) 27 -

Master mode (after enable edge) 11 -

MASTER

/2 - 15 t

SCK

/2 + 15

MASTER

Figure 31. SPI timing diagram - slave mode and CPHA = 0

DS12129 Rev 3 67/85

Electrical characteristics STM8S001J3

Figure 32. SPI timing diagram - slave mode and CPHA = 1

NSS input

SU(NSS)

CPHA=1 CPOL=0

CPHA=1

SCK input

CPOL=1

MISO

OUTPUT

MOSI

INPUT

w(SCKH)

t tw(SCKL)

ta(SO)

su(SI)

tv(SO)

MSB OUT

th(SI)

MSB IN

1. Measurement points are done at CMOS levels: 0.3 V

Figure 33. SPI timing diagram - master mode

High

NSS input

c(SCK)

CPHA=0 CPOL=0

CPHA=0 CPOL=1

SCK Output

tc(SCK)

and 0.7 V

DD.

BIT6 OUT

BIT 1 IN

th(SO)

(1)

th(NSS)

tr(SCK) tf(SCK)

LSB IN

(1)

tdis(SO)

LSB OUT

ai14135b

CPHA=1 CPOL=0

CPHA=1 CPOL=1

SCK Output

MISO

INP UT

MOSI

OUTPUT

su(MI)

1. Measurement points are done at CMOS levels: 0.3 V

w(SCKH)

w(SCKL)

MSB IN

MSB OUT

v(MO)

h(MI)

and 0.7 V

BIT6 IN

B I T1 OUT

DD.

68/85 DS12129 Rev 3

h(MO)

r(SCK)

f(SCK)

LSB IN

LSB OUT

ai14136c

STM8S001J3 Electrical characteristics

9.3.8 I2C interface characteristics

Symbol Parameter

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

h(STA)

su(STA)

su(STO)

w(STO:STA)

1. f

MASTER

Data based on standard I2C protocol requirement, not tested in production

The maximum hold time of the start condition has only to be met if the interface does not stretch the low

3. time

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

4. undefined region of the falling edge of SCL

SCL clock low time 4.7 - 1.3 -

SCL clock high time 4.0 - 0.6 -

SDA setup time 250 - 100 -

SDA data hold time 0

SDA and SCL rise time - 1000 - 300

SDA and SCL fall time - 300 - 300

START condition hold time 4.0 - 0.6 -

Repeated START condition setup time 4.7 - 0.6 -

STOP condition setup time 4.0 - 0.6 - µs

STOP to START condition time (bus free)

Capacitive load for each bus line - 400 - 400 pF

, must be at least 8 MHz to achieve max fast I2C speed (400 kHz)

Table 40. I2C characteristics

Standard mode I2C

(2)

Min

(3)

4.7 - 1.3 - µs

Fast mode

(2)

Max

-0

Min

(4)

I2C

(2)

(1)

Max

900

Unit

(2)

µs

(3)

µs

DS12129 Rev 3 69/85

Electrical characteristics STM8S001J3

Figure 34.

Typical application with I2C bus and timing diagram

4.7 kΩ 4.7 kΩ 100 Ω

SDA

I²C bus

SCL

100 Ω

START

SD A

f(SDA)

SCL

w(SCLH)

h(STA)

r(SDA)

r(SCL)

w(SCLL)

su(SDA)

h(SDA)

f(SCL)

1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x V

su(STA)

STM8

S TART REPEATED

STOP

su(STO)

START

su(STA:STO)

ai17490V2

70/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

9.3.9 10-bit ADC characteristics

Subject to general operating conditions for V

DDA

, f

MASTER

, and TA unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Unit

ADC

BGREF

STAB

CONV

1. During the sample time the input capacitance C source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within t the conversion result. Values for the sample clock tS depend on programming.

ADC clock frequency

Conversion voltage range

AIN

Internal bandgap reference voltage

Internal sample and hold

ADC

capacitor

(1)

Sampling time

Wakeup time from standby - - 7 - µs

Total conversion time (including sampling time, 10-bit resolution)

After the end of the sample time tS, changes of the analog input voltage have no effect on

Table 41. ADC characteristics

(1)

DDA=

AIN

3 to 5.5 V 1 - 4

DDA =

4.5 to 5.5 V 1 - 6

DDA =

-V

2.95 to 5.5 V 1.19 1.22 1.25 V

--3-pF

= 4 MHz - 0.75 -

ADC

= 6 MHz - 0.5 -

ADC

= 4 MHz 3.5 µs

ADC

= 6 MHz 2.33 µs

ADC

-141/f

(3 pF max) can be charged/discharged by the external

MHz

-VDDV

µs

ADC

DS12129 Rev 3 71/85

Electrical characteristics STM8S001J3

Symbol Parameter Conditions Typ Max

|ET| Total unadjusted error

|EO| Offset error

|EG| Gain error

|ED| Differential linearity error

| Integral linearity error

1. Guaranteed by characterization results.

2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I ΣI

in Section 9.3.6 does not affect the ADC accuracy.

INJ(PIN)

Table 42. ADC accuracy with R

ADC

(2)

ADC

< 10 kΩ , V

AIN

= 5 V

= 2 MHz 1.6 3.5

= 4 MHz 2.2 4

= 6 MHz 2.4 4.5

= 2 MHz 1.1 2.5

= 4 MHz 1.5 3

= 6 MHz 1.8 3

= 2 MHz 1.5 3

= 4 MHz 2.1 3

= 6 MHz 2.2 4

= 2 MHz 0.7 1.5

= 4 MHz 0.7 1.5

= 6 MHz 0.7 1.5

= 2 MHz 0.6 1.5

= 4 MHz 0.8 2

= 6 MHz 0.8 2

(1)

INJ(PIN)

and

Unit

LSB

Symbol Parameter Conditions Typ Max

| Total unadjusted error

| Offset error

| Gain error

| Differential linearity error

| Integral linearity error

1. Guaranteed by characterization results.

INJ(PIN)

Table 43. ADC accuracy with R

(2)

in Section 9.3.6 does not affect the ADC accuracy.

AIN

ADC

< 10 kΩ R

AIN

, V

= 3.3 V

= 2 MHz 1.6 3.5

= 4 MHz 1.9 4

= 2 MHz 1 2.5

= 4 MHz 1.5 2.5

= 2 MHz 1.3 3

= 4 MHz 2 3

= 2 MHz 0.7 1.0

= 4 MHz 0.7 1.5

= 2 MHz 0.6 1.5

= 4 MHz 0.8 2

(1)

INJ(PIN)

and

Unit

LSB

72/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

1LSB

IDEAL

1LSB

IDEAL

DDAVSSA

–

1024

----------------------------- ------------=

1023

1022 1021

1234567

1021102210231024

(1)

(2)

(3)

DDA

SSA

AINx

STM8

±1µA

0.6V

ADC

AIN

10-bit A/D

conversion

AIN

Figure 35. ADC accuracy characteristics

1. Example of an actual transfer curve.

2. The ideal transfer curve

3. End point correlation line

= Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

= Offset error: deviation between the first actual transition and the first ideal one.

EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. E

= Integral linearity error: maximum deviation between any actual transition and the end point correlation

line.

Figure 36. Typical application with ADC

DS12129 Rev 3 73/85

Electrical characteristics STM8S001J3

9.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

• ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.

• FTB: A burst of fast transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

and VSS

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

Prequalification trials

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Symbol Parameter Conditions Level/class

Voltage limits to be applied on any I/O pin to

FESD

induce a functional disturbance

Fast transient voltage burst limits to be applied through 100pF on VDD and V

EFTB

to induce a functional disturbance

Table 44. EMS data

MASTER

conforming to IEC 61000-4-2

MASTER

conforming to IEC 61000-4-4

pins

= 3.3 V, TA = 25 °C,

= 16 MHz,

= 3.3 V, TA = 25 °C,

= 16 MHz,

TBD

(1)

1. Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 EMC guidelines for STM8Smicrocontrollers.

74/85 DS12129 Rev 3

STM8S001J3 Electrical characteristics

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. Emission tests conform to the IEC 61967-2 standard for test software, board layout and pin loading.

Table 45. EMI data

Conditions

Symbol Parameter

General conditions

= 5 V

= 25 °C

Peak level

EMI

SO8N package conforming to IEC

EMI level - TBD TBD -

1. Guaranteed by characterization results.

61967-2

Max f

HSE/fCPU

Monitored

frequency band

16 MHz/

8 MHz

0.1 MHz to 30 MHz TBD TBD

130 MHz to 1 GHz TBD TBD

(1)

Unit

16 MHz/

16 MHz

dBµV30 MHz to 130 MHz TBD TBD

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (one positive then one negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: the Human Body Model (HBM). This test conforms to the JESD22A114A/A115A standard. For more details, refer to the application note AN1181.

Table 46. ESD absolute maximum ratings

Symbol Ratings Conditions Class

ESD(HBM)

ESD(CDM)

1. Guaranteed by characterization results.

Electrostatic discharge voltage (Human body model)

Electrostatic discharge voltage (Charge device model)

TA = 25°C, conforming to JESD22-A114

TA= 25°C, conforming to JESD22-C101

DS12129 Rev 3 75/85

Maximum

value

(1)

Unit

ATBDV

IV TBD V

Electrical characteristics STM8S001J3

Static latch-up

Two complementary static tests are required on 10 parts to assess the latch-up performance:

• A supply overvoltage (applied to each power supply pin)

• A current injection (applied to each input, output and configurable I/O pin) is performed

on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.

Symbol Parameter Conditions Class

Table 47. Electrical sensitivities

(1)

LU Static latch-up class

TA = 25 °C TBD

= 85 °C TBD

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).

76/85 DS12129 Rev 3

STM8S001J3 Package information

10 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Failure analysis and guarantee

The small number of pins available induces limitations on failure analysis depth in case of isolated symptoms, typically with an impact lower than 0.1%. Please contact your sales office for additional information for any failure analysis. STMicroelectronics will make a feasibility study for investigation based on failure rate and symptom description prior to responsibility endorsement.

10.1 SO8N package information

Figure 37. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width,

package outline

1. Drawing not to scale.

Table 48. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

package mechanical data

millimeters inches

Symbol

Min. Typ. Max. Min. Typ. Max.

A - - 1.750 - - 0.0689

A1 0.100 - 0.250 0.0039 - 0.0098

A2 1.250 - - 0.0492 - -

b 0.280 - 0.480 0.0110 - 0.0189

c 0.170 - 0.230 0.0067 - 0.0091

DS12129 Rev 3 77/85

(1)

Package information STM8S001J3

O7_FP_V1

1.27

0.6 (x8)

3.9

6.7

Table 48. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

package mechanical data

millimeters inches

Symbol

Min. Typ. Max. Min. Typ. Max.

D 4.800 4.900 5.000 0.1890 0.1929 0.1969

E 5.800 6.000 6.200 0.2283 0.2362 0.2441

E1 3.800 3.900 4.000 0.1496 0.1535 0.1575

e - 1.270 - - 0.0500 -

h 0.250 - 0.500 0.0098 - 0.0197

k 0° - 8° 0° - 8°

L 0.400 - 1.270 0.0157 - 0.0500

L1 - 1.040 - - 0.0409 -

ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.

(1)

Figure 38. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

package recommended footprint

Device marking for SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body

width

The following figure gives an example of topside marking orientation versus pin 1/ball A1 identifier location.

Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below.

78/85 DS12129 Rev 3

STM8S001J3 Package information

MSv17033v1

8S001J3

R Y WW

Product identification

Additional information

Date code

Unmarkable surface

PIN1 reference

Figure 39. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

marking example

10.2 Thermal characteristics

1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

The maximum chip junction temperature (T

) must never exceed the values given in

Jmax

Tabl e 17: General operating conditions.

The maximum chip-junction temperature, T

, in degrees Celsius, may be calculated

Jmax

using the following equation:

Jmax

= T

Amax

+ (P

Dmax

x ΘJA)

Where:

• T

•Θ

• P

is the maximum ambient temperature in ° C

Amax

is the package junction-to-ambient thermal resistance in ° C/W

is the sum of P

Dmax

is the product of I

INTmax

and P

I/Omax (PDmax

= P

INTmax

+ P

and VDD, expressed in Watts. This is the maximum chip

I/Omax

)

internal power.

• P

P VOH/I

represents the maximum power dissipation on output pins, where:

I/Omax

I/Omax =

Σ (VOL*IOL) + Σ((VDD-V

of the I/Os at low and high level in the application.

OH)*IOH

), and taking account of the actual VOL/I

and

DS12129 Rev 3 79/85

Package information STM8S001J3

Symbol Parameter Value Unit

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.

Thermal resistance junction-ambient SO8N

Table 49. Thermal characteristics

10.2.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.

10.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see

Figure 40: STM8S001J3 ordering information scheme(1)).

The following example shows how to calculate the temperature range needed for a given application.

Assuming the following application conditions:

• Maximum ambient temperature T

• I

= 8 mA, VDD = 5.0 V

DDmax

• Maximum 4 I/Os used at the same time in output at low level with

= 8 mA, VOL= 0.4 V

INTmax =

Dmax

Thus: P

8 mA x 5.0 V = 40 mW

= 40 mW + (8 x 0.4 x 4) mW

= 52.8 mW

Dmax

= 75 °C (measured according to JESD51-2)

Amax

(1)

102 °C/W

Using the values obtained in Section Table 49.: Thermal characteristics T as follows for SO8N package 102 °C/W :

= 75 °C + (102 °C/W x 52.8 mW) = 75 °C + 5.4 °C = 80.4 °C.

Jmax

Above information is within the range (-40 < TJ < 130 °C)

80/85 DS12129 Rev 3

is calculated

Jmax

STM8S001J3 Ordering information

STM8 S 001 J 3 M 3 TR

Product class

STM8 microcontroller

Pin count

J = 8 pins

Package type

M =SO8N

Example:

Sub-family type

001 = low density

Family type

S = standard

Temperature range

3 = -40°C to 125°C

Program memory size

3 = 8 Kbyte

Packing

No character = tube

TR = Tape and reel

11 Ordering information

Figure 40. STM8S001J3 ordering information scheme

(1)

1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com to you.

or contact the ST Sales Office nearest

DS12129 Rev 3 81/85

STM8 development tools STM8S001J3

12 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.

12.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers.

STice key features

• Occurrence and time profiling and code coverage (new features)

• Advanced breakpoints with up to 4 levels of conditions

• Data breakpoints

• Program and data trace recording up to 128 KB records

• Read/write on the fly of memory during emulation

• In-circuit debugging/programming via SWIM protocol

• 8-bit probe analyzer

• 1 input and 2 output triggers

• Power supply follower managing application voltages between 1.62 to 5.5 V

• Modularity that allows users to specify the components users need to meet their

development requirements and adapt to future requirements

• Supported by free software tools that include integrated development environment

(IDE), programming software interface and assembler for STM8.

82/85 DS12129 Rev 3

STM8S001J3 STM8 development tools

12.2 Software tools

STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to available.

12.2.1 STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes:

ST Visual Develop – Full-featured integrated development environment from ST, featuring

• Seamless integration of C and ASM toolsets

• Full-featured debugger

• Project management

• Syntax highlighting editor

• Integrated programming interface

• Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify the user STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.

Kbytes of code is

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface.

Available toolchains include:

• Cosmic C compiler for STM8 – One free version that outputs up to Kbytes of code is

available. For more information, see www.cosmic-software.com.

• Raisonance C compiler for STM8 – One free version that outputs up to Kbytes of

code. For more information, see www.raisonance.com.

• STM8 assembler linker – Free assembly toolchain included in the STVD toolset,

which allows users to assemble and link the user application source code.

12.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8.

For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.

DS12129 Rev 3 83/85

Revision history STM8S001J3

13 Revision history

Date Revision Changes

24-May-2017 1 Initial release.

29-Jun-2017 2

28-Jun-2018 3

Table 50. Document revision history

Updated:

Section 10: Package information Figure 3: STM8S001J3 SO8N pinout Table 5: STM8S001J3 pin description Table 13: STM8S001J3 alternate function remapping

bits for 8-pin devices

Added:

Section : Device marking for SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width

Updated:

Analog to digital converter (ADC) on cover page Recommendation for SWIM pin (pin #8) sharing on

Section 4.2 Section 4.12: Analog-to-digital converter (ADC1) Table 5: STM8S001J3 pin description Table 13: STM8S001J3 alternate function remapping

bits for 8-pin devices Table 41: ADC characteristics

84/85 DS12129 Rev 3

STM8S001J3

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DS12129 Rev 3 85/85

ST MICROELECTRONICS STM8S001J3M3 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

2 Description

Table 1. STM8S001J3 features

3 Block diagram

Figure 1. STM8S001J3 block diagram

4 Functional overview

4.1 Central processing unit STM8

4.2 Single wire interface module (SWIM) and debug module (DM)

4.3 Interrupt controller

4.4 Flash program memory and data EEPROM

Figure 2. Flash memory organization

4.5 Clock controller

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

4.6 Power management

4.7 Watchdog timers

4.8 Auto wakeup counter

4.9 TIM1 - 16-bit advanced control timer

4.10 TIM2 - 16-bit general purpose timer

4.11 TIM4 - 8-bit basic timer

Table 3. TIM timer features

4.12 Analog-to-digital converter (ADC1)

4.13 Communication interfaces

4.13.1 UART1

4.13.2 SPI

4.13.3 I2C

5 Pinouts and pin descriptions

Table 4. Legend/abbreviations for STM8S001J3 pin description tables

5.1 STM8S001J3 SO8N pinout and pin description

Figure 3. STM8S001J3 SO8N pinout

Table 5. STM8S001J3 pin description

5.2 Alternate function remapping

6 Memory and register map

6.1 Memory map

Figure 4. Memory map

Table 6. Flash, Data EEPROM and RAM boundary addresses

6.2 Register map

6.2.1 I/O port hardware register map

Table 7. I/O port hardware register map

6.2.2 General hardware register map

Table 8. General hardware register map

6.2.3 CPU/SWIM/debug module/interrupt controller registers

Table 9. CPU/SWIM/debug module/interrupt controller registers

7 Interrupt vector mapping

Table 10. Interrupt mapping

8 Option bytes

Table 11. Option bytes

Table 12. Option byte description

8.1 Alternate function remapping bits

Table 13. STM8S001J3 alternate function remapping bits for 8-pin devices

9 Electrical characteristics

9.1 Parameter conditions

9.1.1 Minimum and maximum values

9.1.2 Typical values

9.1.3 Typical curves

9.1.4 Loading capacitor

Figure 5. Pin loading conditions

9.1.5 Pin input voltage

Figure 6. Pin input voltage

9.2 Absolute maximum ratings

Table 14. Voltage characteristics

Table 15. Current characteristics

Table 16. Thermal characteristics

9.3 Operating conditions

Table 17. General operating conditions

Table 18. Operating conditions at power-up/power-down

9.3.1 VCAP external capacitor

9.3.2 Supply current characteristics

Table 19. Total current consumption with code execution in run mode at VDD = 5 V

Table 20. Total current consumption with code execution in run mode at VDD = 3.3 V

Table 21. Total current consumption in wait mode at VDD = 5 V

Table 22. Total current consumption in wait mode at VDD = 3.3 V

Table 23. Total current consumption in active halt mode at VDD = 5 V

Table 24. Total current consumption in active halt mode at VDD = 3.3 V

Table 25. Total current consumption in halt mode at VDD = 5 V

Table 26. Total current consumption in halt mode at VDD = 3.3 V

Table 27. Wakeup times