STM8L001J3
8-bit ultra-low-power microcontroller with up to 8-Kbyte Flash memory, multifunction timers, comparators, UART, SPI, I2C
Features
•Main microcontroller features
–Supply voltage range 1.8 V to 3.6 V
–Low power consumption (Halt: 0.3 µA, Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz)
–STM8 Core with up to 16 CISC MIPS throughput
–Temp. range: -40 to 125 °C
•Memories
–8 Kbytes of Flash program including up to
2 Kbytes of data EEPROM
–Error correction code (ECC)
–Flexible write and read protection modes
–In-application and in-circuit programming
–Data EEPROM capability
–1.5 Kbytes of static RAM
•Clock management
–Internal 16 MHz RC with fast wakeup time (typ. 4 µs)
–Internal low consumption 38 kHz RC driving both the IWDG and the AWU
•Reset and supply management
–Ultra-low power POR/PDR
–Three low-power modes: Wait, Active-halt, Halt
•Interrupt management
–Nested interrupt controller with software priority control
–Up to 6 external interrupt sources
•I/Os
Datasheet - production data
SO8N
4.9x6 mm or 150 mils body width
•Peripherals
–Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 1 channel (used as IC, OC, PWM)
–One 8-bit timer (TIM4) with 7-bit prescaler
–Infrared remote control (IR)
–Independent watchdog
–Auto-wakeup unit
–Beeper timer with 1, 2 or 4 kHz frequencies
–SPI synchronous serial interface
–Fast I2C Multimaster/slave 400 kHz
–UART with fractional baud rate generator
–2 comparators with 1 input each
•Development support
–Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging
–Up to 6 I/Os, all mappable on external interrupt vectors
–I/Os with programmable input pull-ups, high sink/source capability and one LED driver infrared output
September 2020 |
DS12153 Rev 4 |
1/58 |
This is information on a product in full production. |
www.st.com |
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STM8L001J3 |
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1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 6 |
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2 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 7 |
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3 |
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 8 |
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3.1 |
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 9 |
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3.2 |
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 9 |
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3.3 |
Single wire data interface (SWIM) and debug module . . . . . . . . |
. . . . . . . . 9 |
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3.4 |
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 9 |
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3.5 |
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 10 |
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3.6 |
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . .11 |
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3.7 |
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . .11 |
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3.8 |
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . .11 |
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3.9 |
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . .11 |
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3.10 |
Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . .11 |
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3.11 |
General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . .11 |
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3.12 |
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 12 |
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3.13 |
Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 12 |
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3.14 |
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 12 |
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3.15 |
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 12 |
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3.16 |
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.17 |
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5 |
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6 |
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 26 |
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7 |
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 28 |
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8 |
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8.1 |
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 34 8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.8 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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9.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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10 |
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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11 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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List of tables |
STM8L001J3 |
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List of tables
Table 1. STM8L001J3 device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. STM8L001J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 17. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 18. Total current consumption and timing in Halt and Active-halt mode at
VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 20. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 21. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 22. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 23. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 25. Output driving current (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 26. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 27. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 43 Table 28. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 29. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 30. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 31. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 32. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 34. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 35. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 36. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 37. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 38. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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List of figures |
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List of figures
Figure 1. STM8L001J3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. STM8L001J3 SO8N pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 5. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6. IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 8. IDD(WAIT) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 9. IDD(WAIT) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 10. Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 11. Typical LSI RC frequency vs. VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. Typical VIL and VIH vs. VDD (High sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 13. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 15. Typical pull-up current IPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 16. Typ. VOL at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17. Typ. VOL at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18. Typ. VOL at VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19. Typ. VOL at VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 20. Typ. VDD - VOH at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 21. Typ. VDD - VOH at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 24. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 25. Typical application with I2C bus and timing diagram (1). . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 26. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 53 Figure 27. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 28. Example of SO8N marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DS12153 Rev 4 |
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Introduction |
STM8L001J3 |
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This datasheet provides the STM8L001J3 pinout, ordering information, mechanical and electrical device characteristics.
For complete information on the STM8L001J3 microcontroller memory, registers and peripherals, please refer to the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013).
The STM8L001J3 devices are members of the STM8L low-power 8-bit family. They are referred to as low-density devices in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) and in the How to program STM8L and STM8AL Flash program memory and data EEPROM programming manual (PM0054).
All devices of the SM8L Series provide the following benefits:
•Reduced system cost
–8 Kbytes of low-density embedded Flash program memory including up to 2 Kbytes of data EEPROM
–High system integration level with internal clock oscillators and watchdogs.
–Smaller battery and cheaper power supplies.
•Low power consumption and advanced features
–Up to 16 MIPS at 16 MHz CPU clock frequency
–Less than 150 µA/MHz, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode
–Clock gated system and optimized power management
•Short development cycles
–Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.
–Full documentation and a wide choice of development tools
•Product longevity
–Advanced core and peripherals made in a state-of-the art technology
–Product family operating from 1.8 V to 3.6 V supply.
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Description |
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The STM8L001J3 low-power microcontroller features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultra fast Flash programming.
All STM8L001J3 microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM.
The STM8L001J3 low power microcontroller is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.
All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout.
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Table 1. STM8L001J3 device feature summary |
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Features |
STM8L001J3 |
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Flash |
8 Kbytes of Flash program memory including up to |
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2 Kbytes of Data EEPROM |
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RAM |
1.5 Kbytes |
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Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, |
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Peripheral functions |
Serial peripheral interface (SPI), Inter-integrated circuit (I2C), |
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Universal synchronous / asynchronous receiver / transmitter (USART), |
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2 comparators, Infrared (IR) interface |
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Timers |
Two 16-bit timers, one 8-bit timer |
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Operating voltage |
1.8 to 3.6 V |
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Operating temperature |
-40 to +125 °C |
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Packages |
SO8N |
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DS12153 Rev 4 |
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Product overview |
STM8L001J3 |
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16 MHz int RC
38 kHz int RC
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STM8 |
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Core |
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up to 16 MHz |
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Nested interrupt |
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controller |
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up to 6 external |
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SWIM |
Debug module |
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IR_TIM |
Infrared interface |
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PA |
Port A |
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PB |
Port B |
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PC |
Port C |
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PD |
Port D |
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@ VDD |
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VDD18 |
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Power |
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Clock |
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Volt. reg. |
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controller |
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Clocks
to core and Reset
peripherals
POR/PDR
Up to 8 Kbytes Flash memory (including up to 2 Kbytes data EEPROM)
1.5 Kbytes
SRAM
VDD = 1.8V to 3.6V
VSS
<![endif]>bus data and Address
USART |
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RX, TX |
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I²C1 |
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SDA, SCL |
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multimaster |
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SPI |
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SCK |
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16-bit Timer 2 |
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IR_TIM |
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16-bit Timer 3 |
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TIM3_CH2 |
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8-bit Timer 4 |
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COMP1_CH3 |
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COMP1 |
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IWDG |
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COMP_REF |
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AWU |
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BEEP |
COMP2_CH2 |
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COMP2 |
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Beeper |
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MS32610V1
Legend:
AWU: Auto-wakeup unit
Int. RC: internal RC oscillator
I2C: Inter-integrated circuit multimaster interface
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous / asynchronous receiver / transmitter
IWDG: Independent watchdog
8/58 |
DS12153 Rev 4 |
STM8L001J3 |
Product overview |
|
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The 8-bit STM8 core is designed for code efficiency and performance.
It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions.
Development tools for the STM8 microcontrollers include:
•The STVD high-level language debugger including C compiler, assembler and integrated development environment
•The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
Recommendations for SWIM pin (pin#1)
As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever. This initial delay can be removed in the final (locked) code.
If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for the device debug/programming.
The STM8L001J3 features a nested vectored interrupt controller:
•Nested interrupts with 3 software priority levels
•26 interrupt vectors with hardware priority
•Up to 6 external interrupt sources on 6 vectors
•Trap and reset interrupts.
DS12153 Rev 4 |
9/58 |
Product overview |
STM8L001J3 |
|
|
The STM8L001J3 devices have the following main features:
•1.5 Kbytes of RAM
•The EEPROM is divided into two memory arrays (see the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013) for details on the memory mapping):
–8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS).
–64 option bytes (one block) of which 5 bytes are already used for the device.
Error correction code is implemented on the EEPROM.
Recommendation for the device's programming:
The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space).
If the device's program memory is empty (0x00 content), it displays the behavior described below:
•After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG (0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF).
It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz HSI clock.
•Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed.
The reading of non-existing memory is a random content which can lead to the execution of invalid instructions.
The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more.
Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device.
The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop.
10/58 |
DS12153 Rev 4 |
STM8L001J3 |
Product overview |
|
|
To minimize power consumption, the product features three low power modes:
•Wait mode: CPU clock stopped, selected peripherals at full clock speed.
•Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit.
•Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. Wakeup is triggered by an external interrupt.
The STM8L001J3 embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.
This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.
The STM8L001J3 embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.
In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU).
The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures.
It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.
3.10Auto-wakeup counter
The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.
STM8L001J3 devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).
DS12153 Rev 4 |
11/58 |
Product overview |
STM8L001J3 |
|
|
16-bit general purpose timers
The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:
•Time base generation
•Measuring the pulse lengths of input signals (input capture)
•Generating output waveforms (output compare, PWM and One pulse mode)
•Interrupt capability on various events (capture, compare, overflow, break, trigger)
8-bit basic timer
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.
The STM8L001J3 devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz.
The STM8L001J3 devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.
The STM8L001J3 features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage).
Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted.
The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.
3.16SPI
The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration.
12/58 |
DS12153 Rev 4 |
STM8L001J3 |
Product overview |
|
|
3.17I2C
The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I2Cbus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes.
DS12153 Rev 4 |
13/58 |
Pin description |
STM8L001J3 |
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PA0/SWIM/BEEP/IR_TIM/ |
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PC1/I2C_SCL/ |
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PC3/USART_TX/ |
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1 |
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8 |
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PC4/USART_CK/CCO |
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PC2/USART_RX |
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PA2/ |
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PB7/SPI_MISO/ |
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2 |
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7 |
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PA4/TIM2_BKIN/ |
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PA6/COMP_REF |
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STM8L |
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PC0/I2C_SDA |
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VSS |
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3 |
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6 |
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PB6/SPI_MOSI |
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PB3/TIM2_ETR/COMP2_CH2/ |
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VDD |
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4 |
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5 |
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PB5/SPI_SCK/ |
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PD0/TIM3_CH2/COMP1_CH3 |
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MSv46315V1 |
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Table 2. Legend/abbreviation for table 4 |
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Type |
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I= input, O = output, S = power supply |
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Level |
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Input |
CM = CMOS |
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Output |
HS = high sink/source (20 mA) |
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Port and control |
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Input |
float = floating, wpu = weak pull-up |
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configuration |
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Output |
T = true open drain, OD = open drain, PP = push pull |
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Reset state |
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Bold X (pin state after reset release). |
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Unless otherwise specified, the pin state is the same during the reset phase (i.e. |
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“under reset”) and after internal reset release (i.e. at reset state). |
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14/58 |
DS12153 Rev 4 |
STM8L001J3 |
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Pin description |
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Table 3. STM8L001J3 pin description |
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Pin |
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Input |
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Output |
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number |
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<![if ! IE]> <![endif]>Type |
<![if ! IE]> <![endif]>Floating |
<![if ! IE]> <![endif]>WPU |
<![if ! IE]> <![endif]>interruptExt. |
<![if ! IE]> <![endif]>source/sinkHigh |
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<![if ! IE]> <![endif]>OD |
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<![if ! IE]> <![endif]>PP |
Main |
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Pin name |
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function |
Alternate function |
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SO8N |
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(after |
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reset) |
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PA0(1)/SWIM/BEEP/ |
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SWIM input and |
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I/O |
X |
X(1) |
C |
HS |
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X |
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X |
Port A0 |
output / Beep |
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IR_TIM |
(2) |
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(2) |
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output/ Timer |
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infrared output |
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1 |
PC3/USART_TX |
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I/O |
X(1) |
X |
X |
HS |
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X |
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X |
Port C3 |
USART transmit |
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USART |
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PC4/USART_CK/ |
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I/O |
X(1) |
X |
X |
HS |
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X |
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X |
Port C4 |
synchronous clock / |
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CCO |
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Configurable clock |
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output |
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PA2 |
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I/O |
X |
X |
X |
HS |
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X |
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X |
Port A2 |
- |
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PA4/TIM2_BKIN |
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I/O |
X |
X |
X |
HS |
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X |
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X |
Port A4 |
Timer 2 - break |
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2 |
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input |
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PA6/COMP_REF |
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I/O |
X |
X |
X |
HS |
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X |
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Port A6 |
Comparator |
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external reference |
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3 |
VSS |
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S |
- |
- |
- |
- |
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- |
Ground |
4 |
VDD |
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S |
- |
- |
- |
- |
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- |
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- |
- |
Power supply |
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PD0/TIM3_CH2/ |
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X |
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Timer 3 - Channel 2 |
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I/O |
X |
X |
HS |
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X |
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X |
Port D0 |
/ Comparator 1 - |
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COMP1_CH3 |
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5 |
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PB3/TIM2_ETR/ |
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Timer 2 - trigger / |
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I/O |
X |
X |
HS |
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X |
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X |
Port B3 |
Comparator 2 - |
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COMP2_CH2 |
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PB5/SPI_SCK |
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I/O |
X |
X |
X |
HS |
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X |
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X |
Port B5 |
SPI clock |
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6 |
PB6/SPI_MOSI |
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I/O |
X |
X |
X |
HS |
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X |
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X |
Port B6 |
SPI master out / |
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slave in |
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PB7/SPI_MISO |
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I/O |
X |
X |
X |
HS |
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X |
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X |
Port B7 |
SPI master in / |
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7 |
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slave out |
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PC0/I2C_SDA |
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I/O |
X |
- |
X |
- |
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T(3) |
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- |
Port C0 |
I2C data |
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8 |
PC1/I2C_SCL |
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I/O |
X |
- |
X |
- |
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T(3) |
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- |
Port C1 |
I2C clock |
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PC2/USART_RX |
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I/O |
X |
X |
X |
HS |
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X |
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X |
Port C2 |
USART receive |
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DS12153 Rev 4 |
15/58 |
Pin description |
STM8L001J3 |
|
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1.The PA0 pin is in input pull-up during the reset phase and after internal reset release. This PA0 default state influences all the GPIOs connected in parallel on pin number 1 (PC3, PC4).
2.High sink LED driver capability available on PA0.
3.In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented). Although PC0/PC1 itself is a true open drain GPIO with its respective internal circuitry and characteristics, VIN maximum of the pin number 7 and pin number 8 is limited by the standard GPIO (PB7 or PC2) which is also bonded to the same pin number.
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Slope control of all GPIO pins can be programmed except true open drain pins which by |
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default is limited to 2 MHz. |
Note: |
The PA1, PA3, PA5, PB0, PB1, PB2, PB4, PC5, PC6, PD1, PD2, PD3, PD4, PD5, PD6 and |
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PD7 GPIOs should be configured after device reset, by user software into the in output |
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push-pull mode with output-low state to reduce device consumption and to improve EMC |
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immunity. Those GPIOs are not connected to pins and after device reset are in input floating |
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mode. To configure PA1 pin in output push-pull mode refer to Section “Configuring |
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NRST/PA1 pin as general purpose output” in the STM8L001xx, STM8L101xx |
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microcontroller family reference manual (RM0013). |
Note: |
As several pins provide a connection to multiple GPIOs, the mode selection for any of those |
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GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for |
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the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to |
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the same pin (including their alternate functions). For example, pull-up enabled on PA0 is |
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also seen on PC3 and PC4. Push-pull configuration of PA2 is also seen on PA4 and PA6, |
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etc. |
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DS12153 Rev 4 |
STM8L001J3 |
Memory and register map |
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0x00 0000
0x00 05FF
0x00 0600
0x00 47FF
0x00 4800
0x00 48FF
0x 004900
0x 004924
0x 004925
0x 004930
0x 004931
0x00 49FF
0x00 5000
0x00 57FF
0x00 5800
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
0x00 8080
0x00 9FFF
RAM
(1.5 Kbytes) (1) including
Stack
(up to 513 bytes) (1)
Reserved
Option bytes
Reserved
Unique ID
Reserved
GPIO and peripheral registers(2)
Reserved
CPU/SWIM/Debug/ITC
Registers
Interrupt vectors
Low-density
Flash program memory (up to 8 Kbytes) (1)
including Data EEPROM (up to 2 Kbytes)
MS32621V1
1.Table 4 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.
2.Refer to Table 6 for an overview of hardware register mapping, to Table 5 for details on I/O port hardware registers, and to Table 7 for information on CPU/SWIM/debug module controller registers.
DS12153 Rev 4 |
17/58 |
Memory and register map |
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STM8L001J3 |
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Table 4. Flash and RAM boundary addresses |
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Memory area |
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Size |
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Start address |
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End address |
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RAM |
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1.5 Kbytes |
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0x00 0000 |
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0x00 05FF |
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Flash program memory |
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8 Kbytes |
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0x00 8000 |
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0x00 9FFF |
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Table 5. I/O Port hardware register map |
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Address |
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Block |
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Register label |
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Register name |
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Reset |
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status |
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0x00 5000 |
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PA_ODR |
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Port A data output latch register |
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0x00 |
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0x00 5001 |
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PA_IDR |
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Port A input pin value register |
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0xxx |
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0x00 5002 |
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Port A |
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PA_DDR |
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Port A data direction register |
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0x00 |
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0x00 5003 |
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PA_CR1 |
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Port A control register 1 |
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0x00 |
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0x00 5004 |
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PA_CR2 |
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Port A control register 2 |
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0x00 |
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0x00 5005 |
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PB_ODR |
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Port B data output latch register |
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0x00 |
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0x00 5006 |
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PB_IDR |
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Port B input pin value register |
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0xxx |
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0x00 5007 |
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Port B |
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PB_DDR |
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Port B data direction register |
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0x00 |
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0x00 5008 |
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PB_CR1 |
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Port B control register 1 |
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0x00 |
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0x00 5009 |
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PB_CR2 |
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Port B control register 2 |
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0x00 |
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0x00 500A |
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PC_ODR |
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Port C data output latch register |
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0x00 |
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0x00 500B |
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PC_IDR |
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Port C input pin value register |
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0xxx |
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Port C |
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0x00 500C |
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PC_DDR |
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Port C data direction register |
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0x00 |
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0x00 500D |
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PC_CR1 |
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Port C control register 1 |
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0x00 |
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0x00 500E |
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PC_CR2 |
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Port C control register 2 |
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0x00 |
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0x00 500F |
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PD_ODR |
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Port D data output latch register |
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0x00 |
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0x00 5010 |
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PD_IDR |
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Port D input pin value register |
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0xxx |
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0x00 5011 |
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Port D |
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PD_DDR |
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Port D data direction register |
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0x00 |
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0x00 5012 |
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PD_CR1 |
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Port D control register 1 |
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0x00 |
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0x00 5013 |
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PD_CR2 |
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Port D control register 2 |
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0x00 |
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18/58 |
DS12153 Rev 4 |