STMicroelectronics STM8L001J3 Datasheet

STM8L001J3

SO8N

4.9x6 mm or 150 mils body width

8-bit ultra-low-power microcontroller with up to 8-Kbyte

Flash memory, multifunction timers, comparators, UART, SPI, I2C

Datasheet - production data

Features

• Main microcontroller features – Supply voltage range 1.8 V to 3.6 V – Low power consumption (Halt: 0.3 µA,

Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz)

– STM8 Core with up to 16 CISC MIPS

throughput

– Temp. range: -40 to 125 °C

• Memories – 8 Kbytes of Flash program including up to

2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM

• Clock management – Internal 16 MHz RC with fast wakeup time

(typ. 4 µs)

– Internal low consumption 38 kHz RC

driving both the IWDG and the AWU

• Reset and supply management – Ultra-low power POR/PDR – Three low-power modes: Wait, Active-halt,

Halt

• Interrupt management – Nested interrupt controller with software

priority control

– Up to 6 external interrupt sources

• I/Os – Up to 6 I/Os, all mappable on external

interrupt vectors

– I/Os with programmable input pull-ups, high

sink/source capability and one LED driver infrared output

• Peripherals – Two 16-bit general purpose timers (TIM2

and TIM3) with up and down counter and 1

channel (used as IC, OC, PWM) – One 8-bit timer (TIM4) with 7-bit prescaler – Infrared remote control (IR) – Independent watchdog – Auto-wakeup unit – Beeper timer with 1, 2 or 4 kHz frequencies – SPI synchronous serial interface – Fast I2C Multimaster/slave 400 kHz – UART with fractional baud rate generator – 2 comparators with 1 input each

• Development support – Hardware single wire interface module

(SWIM) for fast on-chip programming and non intrusive debugging

September 2020 DS12153 Rev 4 1/58

This is information on a product in full production.

www.st.com

STM8L001J3

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . . 9

3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.7 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.8 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.9 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.10 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.11 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.13 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.14 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.15 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.16 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.17 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/58 DS12153 Rev 4

STM8L001J3

8.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 34

8.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.3.8 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

9.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

DS12153 Rev 4 3/58

List of tables STM8L001J3

List of tables

Table 1. STM8L001J3 device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. STM8L001J3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 17. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18. Total current consumption and timing in Halt and Active-halt mode at

VDD = 1.8 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 20. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 25. Output driving current (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 26. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 27. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 43

Table 28. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 29. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 31. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 32. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 34. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 35. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 36. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 37. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 38. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4/58 DS12153 Rev 4

STM8L001J3 List of figures

List of figures

Figure 1. STM8L001J3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. STM8L001J3 SO8N pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 5. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 6. IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7. IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. IDD(WAIT) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 9. IDD(WAIT) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10. Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. Typical LSI RC frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 12. Typical VIL and VIH vs. VDD (High sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 14. Typical pull-up resistance R Figure 15. Typical pull-up current I

Figure 16. Typ. VOL at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17. Typ. VOL at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 18. Typ. VOL at VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 19. Typ. VOL at VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20. Typ. VDD - VOH at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 21. Typ. VDD - VOH at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 23. SPI timing diagram - slave mode and CPHA = 1 Figure 24. SPI timing diagram - master mode

Figure 25. Typical application with I2C bus and timing diagram (1). . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 26. SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 53 Figure 27. SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width,

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 28. Example of SO8N marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DS12153 Rev 4 5/58

Introduction STM8L001J3

1 Introduction

This datasheet provides the STM8L001J3 pinout, ordering information, mechanical and

electrical device characteristics.

For complete information on the STM8L001J3 microcontroller memory, registers and

peripherals, please refer to the STM8L001xx, STM8L101xx microcontroller family reference

manual (RM0013).

The STM8L001J3 devices are members of the STM8L low-power 8-bit family. They are

referred to as low-density devices in the STM8L001xx, STM8L101xx microcontroller family

reference manual (RM0013) and in the How to program STM8L and STM8AL Flash

program memory and data EEPROM programming manual (PM0054).

All devices of the SM8L Series provide the following benefits:

• Reduced system cost

– 8 Kbytes of low-density embedded Flash program memory including up to

2 Kbytes of data EEPROM

– High system integration level with internal clock oscillators and watchdogs.

– Smaller battery and cheaper power supplies.

• Low power consumption and advanced features

– Up to 16 MIPS at 16 MHz CPU clock frequency

– Less than 150 µA/MHz, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode

– Clock gated system and optimized power management

•

Short development cycles

– Application scalability across a common family product architecture with

compatible pinout, memory map and modular peripherals.

– Full documentation and a wide choice of development tools

•

Product longevity

– Advanced core and peripherals made in a state-of-the art technology

– Product family operating from 1.8 V to 3.6 V supply.

6/58 DS12153 Rev 4

STM8L001J3 Description

2 Description

The STM8L001J3 low-power microcontroller features the enhanced STM8 CPU core

providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the

advantages of a CISC architecture with improved code density, a 24-bit linear addressing

space and an optimized architecture for low power operations.

The family includes an integrated debug module with a hardware interface (SWIM) which

allows non-intrusive in-application debugging and ultra fast Flash programming.

All STM8L001J3 microcontrollers feature low power low-voltage single-supply program

Flash memory. The 8-Kbyte devices embed data EEPROM.

The STM8L001J3 low power microcontroller is based on a generic set of state-of-the-art

peripherals. The modular design of the peripheral set allows the same peripherals to be

found in different ST microcontroller families including 32-bit families. This makes any

transition to a different family very easy, and simplified even more by the use of a common

set of development tools.

All STM8L low power products are based on the same architecture with the same memory

mapping and a coherent pinout.

Table 1. STM8L001J3 device feature summary

Features STM8L001J3

Flash

RAM 1.5 Kbytes

Peripheral functions

Timers Two 16-bit timers, one 8-bit timer

Operating voltage 1.8 to 3.6 V

Operating temperature -40 to +125 °C

Packages SO8N

Universal synchronous / asynchronous receiver / transmitter (USART),

8 Kbytes of Flash program memory including up to

2 Kbytes of Data EEPROM

Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep,

Serial peripheral interface (SPI), Inter-integrated circuit (I2C),

2 comparators, Infrared (IR) interface

DS12153 Rev 4 7/58

Product overview STM8L001J3

MS32610V1

16 MHz int RC

Clock

controller

Clocks

AWU

Beeper

Address and data bus

38 kHz int RC

Debug module

I²C1

SPI

USART

Up to 8 Kbytes

Flash memory

controller

1.5 Kbytes

to core and peripherals

IWDG

16-bit Timer 2

(SWIM)

Nested interrupt

up to 6 external

multimaster

8-bit Timer 4

SRAM

interrupts

(including up to 2 Kbytes data EEPROM)

Power

Volt. reg.

POR/PDR

Reset

COMP1

COMP2

Port A

Port B

Port C

Port D

RX, TX

SDA, SCL

MOSI, MISO, SCK

BEEP

SWIM

COMP1_CH3

COMP_REF

Infrared interface

IR_TIM

16-bit Timer 3

IR_TIM

TIM3_CH2

COMP2_CH2

DD18

@ V

STM8

Core

up to 16 MHz

= 1.8V to 3.6V

3 Product overview

Figure 1. STM8L001J3 device block diagram

Legend:

AWU: Auto-wakeup unit Int. RC: internal RC oscillator I2C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog

8/58 DS12153 Rev 4

STM8L001J3 Product overview

3.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.

It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions.

3.2 Development tools

Development tools for the STM8 microcontrollers include:

• The STVD high-level language debugger including C compiler, assembler and integrated development environment

• The STVP Flash programming software

The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.

3.3 Single wire data interface (SWIM) and debug module

The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming.

The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes.

The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.

Recommendations for SWIM pin (pin#1)

As the NRST pin is not available on this device, if the SWIM pin should be used with the I/O pin functionality, it is recommended to add a ~5 seconds delay in the firmware before changing the functionality on the pin with SWIM functions. This action allows the user to set the device into SWIM mode after the device power on and to be able to reprogram the device. If the pin with SWIM functionality is set to I/O mode immediately after the device reset, the device is unable to connect through the SWIM interface and it gets locked forever. This initial delay can be removed in the final (locked) code.

If the initial delay is not acceptable for the application there is the option that the firmware reenables the SWIM pin functionality under specific conditions such as during firmware startup or during application run. Once that this procedure is done, the SWIM interface can be used for the device debug/programming.

3.4 Interrupt controller

The STM8L001J3 features a nested vectored interrupt controller:

• Nested interrupts with 3 software priority levels

• 26 interrupt vectors with hardware priority

• Up to 6 external interrupt sources on 6 vectors

• Trap and reset interrupts.

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Product overview STM8L001J3

3.5 Memory

The STM8L001J3 devices have the following main features:

• 1.5 Kbytes of RAM

• The EEPROM is divided into two memory arrays (see the STM8L001xx, STM8L101xx

microcontroller family reference manual (RM0013) for details on the memory mapping):

– 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data

EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS).

– 64 option bytes (one block) of which 5 bytes are already used for the device.

Error correction code is implemented on the EEPROM.

Recommendation for the device's programming:

The device's 8 Kbytes program memory is not empty on virgin devices; there is code loop implemented on the reset vector. It is recommended to keep valid code loop in the device to avoid the program execution from an invalid memory address (which would be any memory address out of 8 Kbytes program memory space).

If the device's program memory is empty (0x00 content), it displays the behavior described below:

• After the power on, the “empty” code is executed (0x0000 opcodes = instructions: NEG (0x00, SP)) until the device reaches the end of the 8 Kbytes program memory (the end address = 0x9FFF). It takes around 4 milliseconds to reach the end of the 8 Kbytes memory space @2 MHz HSI clock.

• Once the device reaches the end of the 8 Kbytes program memory, the program continues and code from a non-existing memory is fetched and executed.

The reading of non-existing memory is a random content which can lead to the execution of invalid instructions.

The execution of invalid instructions generates a software reset and the program starts again. A reset can be generated every 4 milliseconds or more.

Only the “connect on-the-fly” method can be used to program the device through the SWIM interface. The “connect under-reset” method cannot be used because the NRST pin is not available on this device.

The “connect on-the-fly” mode can be used while the device is executing code, but if there is a device reset (by software reset) during the SWIM connection, this connection is aborted and it must be performed again from the debug tool. Note that the software reset occurrence can be of every 4 milliseconds, making it difficult to successfully connect to the device's debug tool (there is practically only one successful connection trial for every 10 attempts). Once that a successful connection is reached, the device can be programmed with a valid firmware without problems; therefore it is recommended that device is never erased and that is contains always a valid code loop.

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STM8L001J3 Product overview

3.6 Low power modes

To minimize power consumption, the product features three low power modes:

• Wait mode: CPU clock stopped, selected peripherals at full clock speed.

• Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup

time is controlled by the AWU unit.

• Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. Wakeup is triggered by an external interrupt.

3.7 Voltage regulators

The STM8L001J3 embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals.

This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption.

3.8 Clock control

The STM8L001J3 embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler.

In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU).

3.9 Independent watchdog

The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures.

It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure.

3.10 Auto-wakeup counter

The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode.

3.11 General purpose and basic timers

STM8L001J3 devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4).

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Product overview STM8L001J3

16-bit general purpose timers

The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including:

• Time base generation

• Measuring the pulse lengths of input signals (input capture)

• Generating output waveforms (output compare, PWM and One pulse mode)

• Interrupt capability on various events (capture, compare, overflow, break, trigger)

8-bit basic timer

The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow.

3.12 Beeper

The STM8L001J3 devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38

kHz.

3.13 Infrared (IR) interface

The STM8L001J3 devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals.

3.14 Comparators

The STM8L001J3 features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage).

Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted.

3.15 USART

The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates.

3.16 SPI

The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration.

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STM8L001J3 Product overview

3.17 I2C

The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I2C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes.

I2Cbus. It provides multi-master capability, and controls all

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Pin description STM8L001J3

MSv46315V1

PC1/I2C_SCL/ PC2/USART_RX

PB7/SPI_MISO/ PC0/I2C_SDA

PB6/SPI_MOSI

PB3/TIM2_ETR/COMP2_CH2/ PB5/SPI_SCK/ PD0/TIM3_CH2/COMP1_CH3

PA0/SWIM/BEEP/IR_TIM/

PC3/USART_TX/

PC4/USART_CK/CCO

PA2/ PA4/TIM2_BKIN/ PA6/COMP_REF

VSS

VDD

STM8L

4 Pin description

Figure 2. STM8L001J3 SO8N pinout

Table 2. Legend/abbreviation for table 4

Type I= input, O = output, S = power supply

Input CM = CMOS

Level

Output HS = high sink/source (20 mA)

Port and control configuration

Input float = floating, wpu = weak pull-up

Output T = true open drain, OD = open drain, PP = push pull

Bold X (pin state after reset release).

Reset state

Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state).

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STM8L001J3 Pin description

number

SO8N

Table 3. STM8L001J3 pin description

Input Output

Main

Pin name

Type

Floating

WPU

function

(after

reset)

Alternate function

Ext. interrupt

High sink / source

(1)

PA0 IR_TIM

/SWIM/BEEP/

(2)

I/O X X

(1)

XXPort A0

(2)

SWIM input and output / Beep output/ Timer infrared output

(1)

PC3/USART_TX I/O X

X X HS X X Port C3 USART transmit

USART PC4/USART_CK/ CCO

I/O X

(1)

XXHSXXPort C4

synchronous clock /

Configurable clock

output

PA2 I/O X XXHSXXPort A2-

PA4/TIM2_BKIN I/O X XXHSXXPort A4

PA6/COMP_REF I/O X XXHSXXPort A6

PD0/TIM3_CH2/ COMP1_CH3

PB3/TIM2_ETR/ COMP2_CH2

S - ----- -Ground

S - ----- -Power supply

I/O X XXHSXXPort D0

I/O X XXHSXXPort B3

Timer 2 - break

input

Comparator

external reference

Timer 3 - Channel 2

/ Comparator 1 -

Channel 3

Timer 2 - trigger /

Comparator 2 -

Channel 2

PB5/SPI_SCK I/O X X X HS X X Port B5 SPI clock

6 PB6/SPI_MOSI I/O X XXHSXXPort B6

PB7/SPI_MISO I/O X XXHSXXPort B7

(3)

PC0/I2C_SDA I/O X -X-T

PC1/I2C_SCL I/O X -X-T

- Port C0 I2C data

(3)

- Port C1 I2C clock

SPI master out /

slave in

SPI master in /

slave out

PC2/USART_RX I/O X X X HS X X Port C2 USART receive

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Pin description STM8L001J3

1. The PA0 pin is in input pull-up during the reset phase and after internal reset release. This PA0 default state influences all the GPIOs connected in parallel on pin number 1 (PC3, PC4).

2. High sink LED driver capability available on PA0.

3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to V not implemented). Although PC0/PC1 itself is a true open drain GPIO with its respective internal circuitry and characteristics, V also bonded to the same pin number.

maximum of the pin number 7 and pin number 8 is limited by the standard GPIO (PB7 or PC2) which is

are

Slope control of all GPIO pins can be programmed except true open drain pins which by default is limited to 2 MHz.

Note: The PA1, PA3, PA5, PB0, PB1, PB2, PB4, PC5, PC6, PD1, PD2, PD3, PD4, PD5, PD6 and

PD7 GPIOs should be configured after device reset, by user software into the in output push-pull mode with output-low state to reduce device consumption and to improve EMC immunity. Those GPIOs are not connected to pins and after device reset are in input floating mode. To configure PA1 pin in output push-pull mode refer to Section “Configuring NRST/PA1 pin as general purpose output” in the STM8L001xx, STM8L101xx microcontroller family reference manual (RM0013).

Note: As several pins provide a connection to multiple GPIOs, the mode selection for any of those

GPIOs impacts all the other GPIOs connected to the same pin. The user is responsible for the proper setting of the GPIO modes in order to avoid conflicts between GPIOs bonded to the same pin (including their alternate functions). For example, pull-up enabled on PA0 is also seen on PC3 and PC4. Push-pull configuration of PA2 is also seen on PA4 and PA6, etc.

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STM8L001J3 Memory and register map

GPIO and peripheral registers

(2)

0x00 0000

Reserved

Flash program memory

(up to 8 Kbytes)

(1)

Interrupt vectors

0x00 4800

0x00 48FF

RAM

0x00 05FF

(1.5 Kbytes)

(1)

(up to 513 bytes)

(1)

0x 004900

Option bytes

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 8000

0x00 9FFF

0x00 0600

0x00 47FF

0x00 49FF

0x00 7EFF

0x00 8080

0x00 807F

CPU/SWIM/Debug/ITC

Registers

0x00 7F00

Reserved

including

Stack

including

Data EEPROM

(up to 2 Kbytes)

0x 004925

0x 004931

0x 004924

0x 004930

Unique ID

Reserved

Low-density

MS32621V1

5 Memory and register map

Figure 3. Memory map

1. Table 4 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address.

2. Refer to Table 6 for an overview of hardware register mapping, to Table 5 for details on I/O port hardware registers, and to Table 7 for information on CPU/SWIM/debug module controller registers.

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Memory and register map STM8L001J3

Table 4. Flash and RAM boundary addresses

Memory area Size Start address End address

RAM 1.5 Kbytes 0x00 0000 0x00 05FF

Flash program memory 8 Kbytes 0x00 8000 0x00 9FFF

Address Block Register label Register name

0x00 5000

Table 5. I/O Port hardware register map

Reset

status

PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0xxx

0x00 5002 PA_DDR Port A data direction register 0x00

Port A

0x00 5003 PA_CR1 Port A control register 1 0x00

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0xxx

0x00 5007 PB_DDR Port B data direction register 0x00

Port B

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

PC_ODR Port C data output latch register 0x00

0x00 500B PC_IDR Port C input pin value register 0xxx

0x00 500C PC_DDR Port C data direction register 0x00

Port C

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

0x00 500F

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_IDR Port D input pin value register 0xxx

0x00 5011 PD_DDR Port D data direction register 0x00

Port D

0x00 5012 PD_CR1 Port D control register 1 0x00

0x00 5013 PD_CR2 Port D control register 2 0x00

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