STMicroelectronics STM8AF6366 User manual

STM8AF6366

Errata sheet

Device limitations for STM8AF6366 automotive MCUs featuring up

to 32 Kbytes of Flash program memory

Applicability

This document applies to the STM8AF6366 devices.

It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0016.

Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation erratum. The term “errata” applies both to limitations and documentation errata.

Reference

Table 1. Device variants

silicon revision codes

Device marking

STM8AF6366 V

August 2020 ES0536 Rev 1 1/21

www.st.com

Contents STM8AF6366

Contents

1 Summary of device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Description of device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 STM8A core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 Activation level (AL) bit not functional in Halt mode . . . . . . . . . . . . . . . . . 8

2.1.2 JRIL and JRIH instructions not available . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.3 Main CPU execution is not resumed after an ISR resets the AL bit . . . . . 8

2.1.4 Unexpected DIV/DIVW instruction result in ISR . . . . . . . . . . . . . . . . . . . 9

2.1.5 Wait for event instruction (WFE) not available . . . . . . . . . . . . . . . . . . . . . 9

2.1.6 Interrupt service routine (ISR) executed with priority of main process . 10

2.2 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 HSI RC oscillator cannot be switched off in run mode . . . . . . . . . . . . . . 10

2.2.2 LSI oscillator remains on in Active-halt mode when the AWU unit uses

the HSE as input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.3 RAM content at address 0x000 not preserved after RESET . . . . . . . . . 10

2.2.4 RAM modified after reset by embedded bootloader . . . . . . . . . . . . . . . 11

2.2.5 Flash/EEPROM memory is read incorrectly after wakeup from power

down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.6 V

rise-time rate for 100mV < VDD < 1V . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Timer peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.1 Corruption of read sequence for the 16-bit counter registers . . . . . . . . 12

2.4 LINUART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.1 PE flag cannot be cleared during the reception of the first half

of Stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.2 PE testing issue in UART mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.3 LIN mode: LIN header error when automatic resynchronization

is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.4 LIN mode: framing error with data byte 0x00 . . . . . . . . . . . . . . . . . . . . . 14

2.4.5 LIN mode: framing error when receiving an identifier (ID) . . . . . . . . . . . 14

2.4.6 LIN mode: parity error when receiving an identifier (ID) . . . . . . . . . . . . 14

2.4.7 LIN mode: OR flag not correctly set in LIN Master mode . . . . . . . . . . . 14

2.5 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.1 I2C event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.2 Corrupted last received data in I2C Master Receiver mode . . . . . . . . . 15

2/21 ES0536 Rev 1

STM8AF6366 Contents

2.5.3 Wrong behavior of I2C peripheral in Master mode after

misplaced STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5.4 Violation of I2C “setup time for repeated START condition” parameter . 16

2.5.5 In I2C slave “NOSTRETCH” mode, underrun errors may not be

detected and may generate bus errors . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5.6 I2C pulse missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.1 Last bit too short if SPI is disabled during communication . . . . . . . . . . 18

2.6.2 Busy flag is not reliable when the SPI is a master simplex receiver . . . 19

2.7 ADC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.1 EOC interrupt triggered when AWDIE and EOCIE set to 1 . . . . . . . . . . 19

3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

ES0536 Rev 1 3/21

List of tables STM8AF6366

List of tables

Table 1. Device variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. V

Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

rise-time and fall-time rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4/21 ES0536 Rev 1

STM8AF6366 List of figures

List of figures

Figure 1. 16-bit read sequence for the counter (TIMx_CNTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ES0536 Rev 1 5/21

Summary of device errata STM8AF6366

1 Summary of device errata

The following table gives a quick reference to the STM8AF6366 device limitations and their status:

A = limitation present, workaround available

N = limitation present, no workaround available

P = limitation present, partial workaround available

“-” = limitation absent

Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on the device or in only a subset of operating modes, of the function concerned.

Function Section Limitation Rev V

2.1.1 Activation level (AL) bit not functional in Halt mode N

Table 2. Summary of device limitations

STM8A core

System limitations

Timer peripheral limitations

LINUART peripheral limitations

2.1.2 JRIL and JRIH instructions not available N

2.1.3 Main CPU execution is not resumed after an ISR resets the AL bit A

2.1.4 Unexpected DIV/DIVW instruction result in ISR A

2.1.5 Wait for event instruction (WFE) not available N

2.1.6 Interrupt service routine (ISR) executed with priority of main process A

2.2.1 HSI RC oscillator cannot be switched off in run mode N

2.2.2

2.2.3 RAM content at address 0x000 not preserved after RESET A

2.2.4 RAM modified after reset by embedded bootloader -

2.2.5

2.2.6 V

2.3.1 Corruption of read sequence for the 16-bit counter registers A

2.4.1 PE flag cannot be cleared during the reception of the first half of Stop bit A

2.4.2 PE testing issue in UART mode N

2.4.3 LIN mode: LIN header error when automatic resynchronization is enabled -

2.4.4 LIN mode: framing error with data byte 0x00 N

2.4.5 LIN mode: framing error when receiving an identifier (ID) N

LSI oscillator remains on in Active-halt mode when the AWU unit uses the HSE as input clock

Flash/EEPROM memory is read incorrectly after wakeup from power down mode

rise-time rate for 100mV < VDD < 1V -

2.4.6 LIN mode: parity error when receiving an identifier (ID) N

2.4.7 LIN mode: OR flag not correctly set in LIN Master mode N

6/21 ES0536 Rev 1

STM8AF6366 Summary of device errata

Table 2. Summary of device limitations (continued)

Function Section Limitation Rev V

2.5.1 I2C event management A

2.5.2 Corrupted last received data in I2C Master Receiver mode A

I2C peripheral limitations

2.5.3 Wrong behavior of I2C peripheral in Master mode after misplaced STOP A

2.5.4 Violation of I2C “setup time for repeated START condition” parameter A

2.5.5

In I2C slave “NOSTRETCH” mode, underrun errors may not be detected and may generate bus errors

2.5.6 I2C pulse missed -

SPI peripheral limitations

ADC peripheral limitation

2.6.1 Last bit too short if SPI is disabled during communication A

2.6.2 Busy flag is not reliable when the SPI is a master simplex receiver N

2.7.1 EOC interrupt triggered when AWDIE and EOCIE set to 1 N

ES0536 Rev 1 7/21

+ 14 hidden pages