STM8AF6366
Errata sheet
Device limitations for STM8AF6366 automotive MCUs featuring up
to 32 Kbytes of Flash program memory
Applicability
This document applies to the STM8AF6366 devices.
It gives a summary and a description of the device errata, with respect to the device
datasheet and reference manual RM0016.
Deviation of the real device behavior from the intended device behavior is considered to be
a device limitation. Deviation of the description in the reference manual or the datasheet
from the intended device behavior is considered to be a documentation erratum. The term
“errata” applies both to limitations and documentation errata.
Reference
Table 1. Device variants
silicon revision codes
Device marking
STM8AF6366 V
August 2020 ES0536 Rev 1 1/21
www.st.com
1
Contents STM8AF6366
Contents
1 Summary of device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description of device errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 STM8A core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Activation level (AL) bit not functional in Halt mode . . . . . . . . . . . . . . . . . 8
2.1.2 JRIL and JRIH instructions not available . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Main CPU execution is not resumed after an ISR resets the AL bit . . . . . 8
2.1.4 Unexpected DIV/DIVW instruction result in ISR . . . . . . . . . . . . . . . . . . . 9
2.1.5 Wait for event instruction (WFE) not available . . . . . . . . . . . . . . . . . . . . . 9
2.1.6 Interrupt service routine (ISR) executed with priority of main process . 10
2.2 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 HSI RC oscillator cannot be switched off in run mode . . . . . . . . . . . . . . 10
2.2.2 LSI oscillator remains on in Active-halt mode when the AWU unit uses
the HSE as input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 RAM content at address 0x000 not preserved after RESET . . . . . . . . . 10
2.2.4 RAM modified after reset by embedded bootloader . . . . . . . . . . . . . . . 11
2.2.5 Flash/EEPROM memory is read incorrectly after wakeup from power
down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.6 V
rise-time rate for 100mV < VDD < 1V . . . . . . . . . . . . . . . . . . . . . . . 12
DD
2.3 Timer peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Corruption of read sequence for the 16-bit counter registers . . . . . . . . 12
2.4 LINUART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 PE flag cannot be cleared during the reception of the first half
of Stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.2 PE testing issue in UART mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 LIN mode: LIN header error when automatic resynchronization
is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.4 LIN mode: framing error with data byte 0x00 . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 LIN mode: framing error when receiving an identifier (ID) . . . . . . . . . . . 14
2.4.6 LIN mode: parity error when receiving an identifier (ID) . . . . . . . . . . . . 14
2.4.7 LIN mode: OR flag not correctly set in LIN Master mode . . . . . . . . . . . 14
2.5 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 I2C event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.2 Corrupted last received data in I2C Master Receiver mode . . . . . . . . . 15
2/21 ES0536 Rev 1
STM8AF6366 Contents
2.5.3 Wrong behavior of I2C peripheral in Master mode after
misplaced STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.4 Violation of I2C “setup time for repeated START condition” parameter . 16
2.5.5 In I2C slave “NOSTRETCH” mode, underrun errors may not be
detected and may generate bus errors . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.6 I2C pulse missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.1 Last bit too short if SPI is disabled during communication . . . . . . . . . . 18
2.6.2 Busy flag is not reliable when the SPI is a master simplex receiver . . . 19
2.7 ADC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.1 EOC interrupt triggered when AWDIE and EOCIE set to 1 . . . . . . . . . . 19
3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ES0536 Rev 1 3/21
3
List of tables STM8AF6366
List of tables
Table 1. Device variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. V
Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
rise-time and fall-time rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DD
4/21 ES0536 Rev 1
STM8AF6366 List of figures
List of figures
Figure 1. 16-bit read sequence for the counter (TIMx_CNTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ES0536 Rev 1 5/21
5
Summary of device errata STM8AF6366
1 Summary of device errata
The following table gives a quick reference to the STM8AF6366 device limitations and their
status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application.
Adoption of a workaround may cause restrictions to target application. Workaround for a
limitation is deemed partial if it only reduces the rate of occurrence and/or consequences of
the limitation, or if it is fully effective for only a subset of instances on the device or in only a
subset of operating modes, of the function concerned.
Function Section Limitation Rev V
2.1.1 Activation level (AL) bit not functional in Halt mode N
Table 2. Summary of device limitations
STM8A core
System
limitations
Timer
peripheral
limitations
LINUART
peripheral
limitations
2.1.2 JRIL and JRIH instructions not available N
2.1.3 Main CPU execution is not resumed after an ISR resets the AL bit A
2.1.4 Unexpected DIV/DIVW instruction result in ISR A
2.1.5 Wait for event instruction (WFE) not available N
2.1.6 Interrupt service routine (ISR) executed with priority of main process A
2.2.1 HSI RC oscillator cannot be switched off in run mode N
2.2.2
2.2.3 RAM content at address 0x000 not preserved after RESET A
2.2.4 RAM modified after reset by embedded bootloader -
2.2.5
2.2.6 V
2.3.1 Corruption of read sequence for the 16-bit counter registers A
2.4.1 PE flag cannot be cleared during the reception of the first half of Stop bit A
2.4.2 PE testing issue in UART mode N
2.4.3 LIN mode: LIN header error when automatic resynchronization is enabled -
2.4.4 LIN mode: framing error with data byte 0x00 N
2.4.5 LIN mode: framing error when receiving an identifier (ID) N
LSI oscillator remains on in Active-halt mode when the AWU unit uses the
HSE as input clock
Flash/EEPROM memory is read incorrectly after wakeup from power down
mode
rise-time rate for 100mV < VDD < 1V -
DD
N
A
2.4.6 LIN mode: parity error when receiving an identifier (ID) N
2.4.7 LIN mode: OR flag not correctly set in LIN Master mode N
6/21 ES0536 Rev 1
STM8AF6366 Summary of device errata
Table 2. Summary of device limitations (continued)
Function Section Limitation Rev V
2.5.1 I2C event management A
2.5.2 Corrupted last received data in I2C Master Receiver mode A
I2C peripheral
limitations
2.5.3 Wrong behavior of I2C peripheral in Master mode after misplaced STOP A
2.5.4 Violation of I2C “setup time for repeated START condition” parameter A
2.5.5
In I2C slave “NOSTRETCH” mode, underrun errors may not be detected
and may generate bus errors
2.5.6 I2C pulse missed -
A
SPI peripheral
limitations
ADC peripheral
limitation
2.6.1 Last bit too short if SPI is disabled during communication A
2.6.2 Busy flag is not reliable when the SPI is a master simplex receiver N
2.7.1 EOC interrupt triggered when AWDIE and EOCIE set to 1 N
ES0536 Rev 1 7/21
20
Description of device errata STM8AF6366
2 Description of device errata
2.1 STM8A core
2.1.1 Activation level (AL) bit not functional in Halt mode
Description
The AL bit is not supported in Halt mode. In particular, when the AL bit of the CFG_GCR
register is set, the CPU does not return to Halt mode after exiting an interrupt service routine
(ISR). It returns to the main program and executes the next instruction after the HALT
instruction. The AL bit is supported correctly in WFI mode.
Workaround
No workaround available.
No fix is planned for this limitation.
2.1.2 JRIL and JRIH instructions not available
Description
JRIL (jump if port INT pin = 0) and JRIH (jump if port INT pin = 1) are not supported by the
devices covered by this datasheet. These instructions perform conditional jumps: JRIL and
JRIH jump if one of the external interrupt lines is low and high, respectively. JRIL is
equivalent to an unconditional jump and JRIH is equivalent to a NOP.
For further details on these instructions, refer to the STM8 CPU programming manual
(PM0044).
Workaround
No workaround available.
No fix is planned for this limitation.
2.1.3 Main CPU execution is not resumed after an ISR resets the AL bit
Description
If the CPU is in wait for interrupt state and the AL bit is set, the CPU returns to wait for
interrupt state after executing an ISR. To continue executing the main program, the AL bit
must be reset by the ISR. When AL is reset just before exiting the ISR, the CPU may remain
stalled.
Workaround
Reset the AL bit at least two instructions before the IRET instruction.
No fix is planned for this limitation.
8/21 ES0536 Rev 1
STM8AF6366 Description of device errata
2.1.4 Unexpected DIV/DIVW instruction result in ISR
Description
In very specific conditions, a DIV/DIVW instruction may return a false result when executed
inside an interrupt service routine (ISR). This error occurs when the DIV/DIVW instruction is
interrupted and a second interrupt is generated during the execution of the IRET instruction
of the first ISR. Under these conditions, the DIV/DIVW instruction executed inside the
second ISR, including function calls, may return an unexpected result.
The applications that do not use the DIV/DIVW instruction within ISRs are not impacted.
Workaround 1
If an ISR or a function called by this routine contains a division operation, the following
assembly code should be added inside the ISR before the DIV/DIVW instruction:
push cc
pop a
and a,#$BF
push a
pop cc
This sequence should be placed by C compilers at the beginning of the ISR using
DIV/DIVW. Refer to the compiler documentation for details on the implementation and
control of automatic or manual code insertion.
Workaround 2
To optimize the number of cycles added by workaround 1, the user can use this workaround
instead. Workaround 2 can be used in applications with fixed interrupt priorities, identified at
the program compilation phase:
push #value
pop cc
where bits 5 and 3 of #value have to be configured according to interrupt priority given by I1
and I0, and bit 6 kept cleared.
In this case, compiler workaround 1 has to be disabled by using compiler directives.
No fix is planned for this limitation.
2.1.5 Wait for event instruction (WFE) not available
Description
The WFE instruction is not implemented in the devices covered by this datasheet. This
instruction is used to synchronize the device with external computing resources. For further
details on this instruction, refer to the STM8 CPU programming manual (PM0044).
Workaround
No workaround available.
No fix is planned for this limitation.
ES0536 Rev 1 9/21
20
Description of device errata STM8AF6366
2.1.6 Interrupt service routine (ISR) executed with priority of main process
Description
If an interrupt is cleared or masked when the context saving has already started, the
corresponding ISR is executed with the priority of the main process. The next interrupt
request can interrupt execution of the service routine
Workaround
At the beginning of the interrupt routine, change the current priority level in the CCR register
by software.
2.2 System limitations
2.2.1 HSI RC oscillator cannot be switched off in run mode
Description
The internal 16 MHz RC oscillator cannot be switched off in run mode, even if the HSIEN bit
is programmed to 0.
Workaround
No workaround available.
No fix is planned for this limitation.
2.2.2 LSI oscillator remains on in Active-halt mode when the AWU unit uses the HSE as input clock
Description
When the auto-wakeup unit (AWU) uses the high speed external clock (HSE) divided by the
prescaler (clock source enabled by setting the CKAWUSEL option bit), the LSI RC oscillator
is not switched off when the device operates in Active-halt mode with the main voltage
regulator (MVR) on. This causes negligible extra power consumption compared to the total
consumption of the MCU in Active-halt mode with the MVR on.
Workaround
No workaround available.
No fix is planned for this limitation.
2.2.3 RAM content at address 0x000 not preserved after RESET
Description
When RESET is asserted during an ongoing write to any RAM location, memory content at
address 0x000 could be corrupted.
Workaround
Do not use location 0x000 to store critical application data.
10/21 ES0536 Rev 1
STM8AF6366 Description of device errata
No fix is planned for this limitation.
2.2.4 RAM modified after reset by embedded bootloader
Description
After each reset, the byte located at RAM address 0x95 is modified by the embedded
bootloader even if the bootloader is disabled by option byte. So the RAM content at address
0x95 is not maintained after reset. The issue is present only in device revision Y.
Workaround
No workaround available. Do not use byte in RAM at address 0x95 to store variables which
should be unchanged after device reset.
2.2.5 Flash/EEPROM memory is read incorrectly after wakeup from power down mode
Description
If Flash/EEPROM memory has been put in power down mode (I
), the first read access
DDQ
after wakeup could return incorrect content.
By default, the Flash/EEPROM memory is put in I
mode when the MCU enters Halt
DDQ
mode and depending on the FLASH_CR1 register settings made by software, the
Flash/EEPROM may be forced to I
mode during active halt mode.
DDQ
As a consequence, the following behavior may be seen on some devices:
• After wakeup from Low power mode, with Flash memory in I
mode, program
DDQ
execution gets lost due to an incorrect read of the vector table.
• Code reads an incorrect value from Flash/EEPROM memory, when forced in I
mode.
• Reset could be forced by an illegal opcode execution due to incorrect read of
instruction.
Note: The use of the watchdog helps the application to recover in case of failure.
Workaround
Keep the Flash/EEPROM in operating mode when MCU is put in Halt mode or Active-halt
mode. This is done by configuring both the HALT and AHALT bits in the FLASH_CR1
register before executing a HALT instruction to prevent the Flash/EEPROM entering I
mode.
Set HALT (bit 3) to 1:
0: Flash in power-down mode when MCU is in Halt mode
1: Flash in operating mode when MCU is in Halt mode
Keep AHALT (bit 2) at 0:
0: Flash in operating mode when MCU is in Active-halt mode
1: Flash in power-down when MCU is in Active-halt mode
DDQ
DDQ
Refer to the datasheet for details on the impact on current consumption and wakeup time.
ES0536 Rev 1 11/21
20
Description of device errata STM8AF6366
MSv41500V1
Beginning of the sequence
At t0
At t0 + Dt
Read
MS byte
LS byte
is buffered
Read
LS byte
Returns the buffered
LS byte value at t0
Other
instructions
Sequence completed
2.2.6 VDD rise-time rate for 100mV < VDD < 1V
Description
The product datasheet did not specify the VDD rise-time initial conditions as the VDD risetime was implicitly specified for a V
some very specific applications could have a V
above 0V and thus require that we explicitly specify these conditions.
starting from 0V. Nevertheless, we observed that
DD
starting from a residual voltage already
DD
The t
parameter must stay below 50µs/V when VDD is rising from 100mV to 1V.
VDD
Table 3. V
rise-time and fall-time rates
DD
Symbol Parameter Conditions Min Typ Max Unit
(1)
(1)
(1)
(1)
- ∞
-50
- ∞
- ∞
t
VDD rise-time rate
VDD
fall-time rate - 2
V
DD
1. Guaranteed by design, not tested in production.
< 100mV 2
V
DD
100mV < V
< 1V 2
DD
VDD > 1V 2
Workaround
Not applicable.
2.3 Timer peripheral limitations
2.3.1 Corruption of read sequence for the 16-bit counter registers
Description
An 8-bit buffer is implemented for reading the 16-bit counter registers. Software must read
the MS byte first, after which the LS byte value is buffered automatically (see the figure
below). This buffered value remains unchanged until the 16-bit read sequence is completed.
(1)
µs/V
When any multi-cycle instruction precedes the read of the LSB, the content of the buffer is
lost and the second read returns the immediate content of the counter directly.
Figure 1. 16-bit read sequence for the counter (TIMx_CNTR)
12/21 ES0536 Rev 1
STM8AF6366 Description of device errata
Workaround
Do not use multi-cycle instructions before reading the LSB.
No fix is planned for this limitation.
2.4 LINUART peripheral limitations
2.4.1 PE flag cannot be cleared during the reception of the first half of Stop bit
Description
The PE flag is set by hardware when the UART is in reception mode and a parity error (PE)
occurs. This flag cannot be cleared during the first half of the Stop bit period. If the software
attempts to clear the PE flag at this moment, the flag is set again by hardware, thus
generating an unwanted interrupt (assuming the PIEN bit has been set in the UART_CR1
register.
Workaround
1. Disable PE interrupts by setting PIEN to 0.
2. After the RXNE bit is set (received data ready to be read), poll the PE flag to check if it
a parity error occurred. For example, this could be done in the RXNE interrupt service
routine.
No fix is planned for this limitation.
2.4.2 PE testing issue in UART mode
Description
When the RXNE flag is not polled, the device is in overrun condition and the PE flag does
not rise in case of a parity error. The flag rises only for the last data which have been
correctly received.
Workaround
No workaround available.
No fix is planned for this limitation.
2.4.3 LIN mode: LIN header error when automatic resynchronization is enabled
Description
If UART2 is configured in LIN slave mode (LSLV bit set in UART2_CR6 register) and the
automatic resynchronization is enabled (LASE bit set in UART2_CR6), the LHE flag may be
set instead of LHDF flag when receiving a valid header.
This limitation is fixed in silicon revision X.
ES0536 Rev 1 13/21
20
Description of device errata STM8AF6366
Workaround
No workaround available.
2.4.4 LIN mode: framing error with data byte 0x00
Description
If the UART2 interface is configured in LIN slave mode, and the active mode with break
detection length is set to 11 (LBDL bit of UART2_CR4 register set to 1), FE and RXNE flags
are not set when receiving a 0x00 data byte with a framing error, followed by a recessive
state. This occurs only if the dominant state length is between 9.56 and 10.56 times the
baud rate.
Workaround
The LIN software driver can handle this exceptional case by implementing frame timeouts to
comply with the LIN standard. This method has been implemented in ST LIN 2.1 driver
package which passed the LIN compliance tests.
2.4.5 LIN mode: framing error when receiving an identifier (ID)
Description
If an ID framing error occurs when the UART2, configured in LIN mode, is in active mode,
both the LHE and LHDF flags are set at the end of the LIN header with an ID framing error.
Workaround
The LIN software driver can handle this case by checking both LHE and LHDF flags upon
header reception.
2.4.6 LIN mode: parity error when receiving an identifier (ID)
Description
If an ID parity error occurs, the UART2, configured in LIN mode, wakes up from mute mode
and both LHE and LHDF are set at the end of the LIN header with parity error. The PE flag is
also set.
Workaround
The LIN software driver can handle this case by checking all flags upon header reception.
No fix is planned for this limitation.
2.4.7 LIN mode: OR flag not correctly set in LIN Master mode
Description
When the UART operates in LIN Master mode, the OR flag is not set if an overrun condition
occurs.
14/21 ES0536 Rev 1
STM8AF6366 Description of device errata
Workaround
The LIN software driver can detect this case through a LIN protocol error. No fix is planned
for this limitation.
2.5 I2C peripheral limitations
2.5.1 I2C event management
Description
As described in the I2C section of the microcontroller reference manual, the application
firmware has to manage several software events before the current byte is transferred. If the
EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events are not managed before the
current byte is transferred, problems may occur such as receiving an extra byte, reading the
same data twice, or missing data.
Workaround
When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events cannot be managed
before the current byte transfer, and before the acknowledge pulse when the ACK control bit
changes, it is recommended to use I
uninterruptible by increasing their priority to the highest priority in the application.
2
C interrupts in nested mode and to make them
No fix is planned for this limitation.
2.5.2 Corrupted last received data in I2C Master Receiver mode
Conditions
In Master Receiver mode, when the communication is closed using method 2, the content of
the last read data may be corrupted. The following two sequences are concerned by the
limitation:
• Sequence 1: transfer sequence for master receiver when N = 2
a) BTF = 1 (Data N-1 in DR and Data N in shift register)
b) Program STOP = 1
c) Read DR twice (Read Data N-1 and Data N) just after programming the STOP bit.
• Sequence 2: transfer sequence for master receiver when N > 2
a) BTF = 1 (Data N-2 in DR and Data N-1 in shift register)
b) Program ACK = 0
c) Read Data N-2 in DR
d) Program STOP bit to 1
e) Read Data N-1.
Description
The content of the shift register (data N) is corrupted (data N is shifted 1 bit to the left) if the
user software is not able to read data N-1 before the STOP condition is generated on the
bus. In this case, reading data N returns a wrong value.
ES0536 Rev 1 15/21
20
Description of device errata STM8AF6366
Workarounds
• Workaround 1
– Sequence 1
When sequence 1 is used to close communication using method 2, mask all active
interrupts between STOP bit programming and Read data N-1.
– Sequence 2
When sequence 2 is used to close communication using method 2, mask all active
interrupts between Read data N-2, STOP bit programming and Read data N-1.
• Workaround 2
Manage I2C RxNE and TxE events with interrupts of the highest priority level, so that
the condition BTF = 1 never occurs.
2.5.3 Wrong behavior of I2C peripheral in Master mode after misplaced STOP
Description
The I2C peripheral does not enter Master mode properly if a misplaced STOP is generated
on the bus. This can happen in the following conditions:
• If a void message is received (START condition immediately followed by a STOP): the
BERR (bus error) flag is not set, and the I2C peripheral is not able to send a START
condition on the bus after writing to the START bit in the I2C_CR2 register.
• In the other cases of a misplaced STOP, the BERR flag is set in the IC2_CR2 register.
If the START bit is already set in I2C_CR2, the START condition is not correctly
generated on the bus and can create bus errors.
Workaround
In the I2C standard, it is not allowed to send a STOP before the full byte is transmitted (8
bits + acknowledge). Other derived protocols like CBUS allow it, but they are not supported
by the I²C peripheral.
In case of noisy environment in which unwanted bus errors can occur, it is recommended to
implement a timeout to ensure that the SB (start bit) flag is set after the START control bit is
set. In case the timeout has elapsed, the peripheral must be reset by setting the SWRST bit
in the I2C_CR2 control register. The I
BERR is detected while the START bit is set in I2C_CR2.
No fix is planned for this limitation.
2
C peripheral should be reset in the same way if a
2.5.4 Violation of I2C “setup time for repeated START condition” parameter
Description
In case of a repeated Start, the “setup time for repeated START condition” parameter
(named t
violated when the I2C operates in Master Standard mode at a frequency ranging from 88 to
100
SU(STA)
kHz. t
in the datasheet and t
SU(STA)
minimum value may be 4 µs instead of 4.7 µs.
SU(STA)
in the I2C specifications) may be slightly
16/21 ES0536 Rev 1
STM8AF6366 Description of device errata
The issue occurs under the following conditions:
1. The I2C peripheral operates in Master Standard mode at a frequency ranging from 88
to 100
kHz (no issue in Fast mode)
2. and the SCL rise time meets one of the following conditions:
– The slave does not stretch the clock and the SCL rise time is more than 300 ns
(the issue cannot occur when the SCL rise time is less than 300 ns).
– or the slave stretches the clock.
Workaround
Reduce the frequency down to 88 kHz or use the I2C Fast mode if it is supported by the
slave.
2.5.5 In I2C slave “NOSTRETCH” mode, underrun errors may not be detected and may generate bus errors
Description
The data valid time (t
well as the maximum current data hold time (t
VD;DAT
, t
VD;ACK
) described by the I2C specifications may be violated as
) under the conditions described below.
HD;DAT
In addition, if the data register is written too late and close to the SCL rising edge, an error
may be generated on the bus: SDA toggles while SCL is high. These violations cannot be
detected because the OVR flag is not set (no transmit buffer underrun is detected).
This issue occurs under the following conditions:
1. The I2C peripheral operates In Slave transmit mode with clock stretching disabled
(NOSTRETCH=1)
2. and the application is late to write the DR data register, but not late enough to set the
OVR flag (the data register is written before the SCL rising edge).
Workaround
If the master device supports it, use the clock stretching mechanism by programming the bit
NOSTRETCH
If the master device does not support it, ensure that the write operation to the data register
is performed just after TXE or ADDR events. The user can use an interrupt on the TXE or
ADDR flag and boost its priority to the higher level.
Using the “NOSTRETCH” mode with a slow I2C bus speed can prevent the application from
being late to write the DR register (second condition).
Note: The first data to be transmitted must be written into the data register after the ADDR flag is
cleared, and before the next SCL rising edge, so that the time window to write the first data
into the data register is less than t
If this is not possible, a possible workaround can be the following:
1. Clear the ADDR flag
2. Wait for the OVR flag to be set
3. Clear OVR and write the first data.
The time window for writing the next data is then the time to transfer one byte. In that case,
the master must discard the first received data.
= 0 in the I2C_CR1 register.
.
LOW
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Description of device errata STM8AF6366
2.5.6 I2C pulse missed
Description
When the I2C interface is used for long transmit/receive transactions, the MCU may return a
NACK somewhere during the transaction instead of returning an ACK for all data. The
received data may also be corrupted. In Master mode the I2C may not detect an incoming
ACK. This is due to a weakness in the noise filter of the I/O pad which in certain conditions
may cause the STM8 I2C to miss a pulse.
This limitation is fixed in revisions X and W.
Workaround
Since data corruption is caused by noise generated by the CPU, CPU activity should be
minimized during data reception and/or transmission. This is done by performing physical
data transmission (Master mode) and reception (slave mode) in WFI state (wait for
interrupt).
To allow the device to be woken up from WFI, I2C transmission and reception routines must
be implemented through interrupt routines instead of polling mechanisms. Receive and
transmit interrupts (received data processing) must be triggered only by the BTF bit flag
(byte transfer finished) in the I2C_SR1 register. This flag indicates that the I
stretched state (data transfers are stretched on the bus).
2
C is in
Clock stretching must be enabled to allow data transfers from the slave to be stopped and to
allow the CPU to be woken up to read the received byte.
To recover from possible errors, periodically check if the I2C does not remain in busy state
for too long (BUSY bit set in I2C_SR3 register). If so, it should be reinitialized.
Example of I2C slave code:
//...
//-----------------------------------------------------------------
void main()
{
Init_I2C(); // init I2C to use interrupts: ITBUFEN=0, ITEVTEN=1,
ITERREN=1
while(1)
2.6 SPI peripheral limitations
2.6.1 Last bit too short if SPI is disabled during communication
Description
When the SPI interface operates in Master mode and the baud rate generator prescaler is
equal to 2, the SPI is disabled during ongoing communications, and the data and clock
output signals are switched off at the last strobing edge of the SPI clock.
As a consequence the length of the last bit is out of range and its reception on the bus is not
ensured.
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STM8AF6366 Description of device errata
Workaround
Check if a communication is ongoing before disabling the SPI interface. This can be done
by monitoring the BSY bit in the SPI_SR register.
2.6.2 Busy flag is not reliable when the SPI is a master simplex receiver
Description
When the master is receiver only, it provides the clock immediately after setting the SPE bit
in the SPI_CR1 register. In this case, the clock is provided until the SPE bit is disabled,
meaning that the SPI is always busy because it is in receiver mode only and continuously
receives data from the clock. There is no need to read the BUSY bit to know the SPI status
because as soon the SPI is enabled, it is BUSY.
Note: The SPE bit has no meaning when the SPI is in master receiver only mode.
Workaround
No workaround available.
No fix is planned for this limitation.
2.7 ADC peripheral limitation
2.7.1 EOC interrupt triggered when AWDIE and EOCIE set to 1
Description
When the analog watchdog is enabled and AWDIE and EOCIE are both set to 1, the ADC
interrupt should only be triggered when the conversion result exceeds one of the analog
watchdog thresholds.
However, for the devices covered by this datasheet, the interrupt is triggered after each
conversion, thus leading to a high interrupt load.
Workaround
Set AWDIE to 1 and EOCIE to 0 instead and stop the conversions inside the ISR by
resetting the CONT bit. However the latest conversion result having triggered the watchdog
may be overwritten.
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Revision history STM8AF6366
3 Revision history
Date Revision Changes
24-Aug-2020 1 Initial release.
Table 4. Document revision history
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STM8AF6366
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