STMicroelectronics STM690A, STM692A, STM703, STM704, STM802 Technical data
...
STM690A, STM692A, STM703
STM704, STM802, STM805, STM817/8/9
5V Supervisor with Battery Switchover
FEAT URES SUMMARY
■ 5V OPERATING VOLTAGE
■ NVRAM SUPERVISO R FOR EXTERNAL
LPSRAM
■ CHIP-ENABLE GATING (STM818 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY)
■ RST AND RST OUTPUTS
■ 200ms (TYP) t
■ WATCHDOG TIMER - 1.6sec (TYP)
■ AUTOMATIC BATTERY SWITCHOVER
■ LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP)
■ POWER-FAIL COMPARATOR (PFI/P FO )
■ LOW SUPPLY CURRENT - 40µA (TYP)
■ GUARANTEED RST (RST) ASSERTION
DOWN TO V
■ OPERATING TEMPERAT UR E:
–40°C to 85°C (Industrial Grade)
rec
= 1.0V
CC
Figure 1. Packages
8
1
SO8 (M)
TSSOP8 3x3 (DS)*
Table 1. Device Options
(1)
Active-
High
(1)
RST
Manual
Reset
Input
Battery
Switch-
over
Power-fail
Comparator
ChipEnable
Gating
Battery
Freshness
Seal
Watchdog
Input
STM690A ✔✔ ✔ ✔
STM692A ✔✔ ✔ ✔
STM703 ✔✔✔✔
STM704 ✔✔✔✔
STM802L/M ✔✔ ✔ ✔
STM805L ✔✔✔✔
STM817L/M ✔✔ ✔ ✔ ✔
STM818L/M ✔✔ ✔ ✔✔
STM819L/M ✔✔✔✔ ✔
Note: 1. All RST and RST outp uts are push-pull.
Active-
Low
RST
* Contact local ST sales office for availability.
1/37March 2005
STM690A/692A/703/704/802/805/817/818/819
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM690A/692A/802/805/ 817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Logic Diagram (STM818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. STM690A/692A/802/ 805/817 Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM703/704/819 Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM818 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM690A/692A/802/805/ 817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Block Diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (NOT available on STM703/704/ 819 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip-Enable Gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Input (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable Output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Chip-Enable Gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Figure 13.Chip Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-fail Input/Output (NOT available on STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figu r e 1 4 .Power - fail Co mpara tor Wa veform (STM 8 1 7/81 8 /8 19) . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Figure 15.Power-fail Comparator Waveform (STM690A/692A/703/704/ 802/805) . . . . . . . . . . . . . 13
Using a SuperCap™ as a Backup Power Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Negativ e- Go in g V
Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Battery Freshness Seal (STM817/8 18/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Figure 17.Freshness Seal Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18.V
Figure 19.V
2/37
CC
BAT
-to-V
-to-V
On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUT
On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUT
STM690A/692A/703/704/802/805/817/818/819
Figure 20.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21.Battery Current vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22.V
Figure 23.Reset Comparator Propagation Delay vs. Temperature (Other than STM817/818/819) 17
Figure 24.Reset Comparator Propagation Delay vs. Temperature (V
Figure 25.Power-up t
Figure 26.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28.E
Figure 29.PFI to PFO
Figure 30.Output Voltage vs. Load Current (V
Figure 31.Output Voltage vs. Load Current (V
Figure 32.RST
Figure 33.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 34.RST
Figure 35.RST Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 36.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 37.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 38.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 25
Figure 39.E
Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PFI
=3.0V; STM817/818/819)18
BAT
vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
rec
to E
On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CON
Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
= 5V; V
CC
= 0V; V
CC
= 2.8V; TA = 25°C). . . . . . . . . . . . . . 21
BAT
= 2.8V; TA = 25°C). . . . . . . . . . . . . . 21
BAT
Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
to E
Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CON
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 40.E
to ECON Propagation Delay Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 41.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 42.MR
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 43.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. DC and A C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 44.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 32
Table 8. S O8 – 8-lead Plast ic Small Outline, 150 mils body widt h, Package Mechanical Data . . 32
Figure 45.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 33
Table 9. TS SOP 8 – 8-lead, Thin Shrink Smal l Outline, 3x3mm body size , Mechanical Data . . . . 33
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11.Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
STM690A/692A/703/704/802/805/817/818/819
SUMMARY DESCRIPTION
The STM690A/692A/703/704/802/805/817/818/
819 Supervisors are self-contained devices which
provide microprocessor supervisory functions with
the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and
comparator monitors the V
tolerance condition. When an invalid V
tion occurs, the reset output (RST
(or high in the ca se of RST). These devices also
input for an out-of-
CC
CC
condi-
) is forced low
offer a watchdog timer (excep t for STM703/704/
819) as well as a power-fail comparator (except for
STM818) to provide the system with an early
warning of impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM690A/692A/802/ 805/817)
VCCV
WDI
PFI
Note: 1. For STM805, reset output i s active-h i gh.
BAT
STM690A/
692A/802/
805/817
V
SS
V
OUT
RST(RST)
PFO
AI07894
(1)
Figure 3. Logic Diagram (STM703/704/819)
VCCV
BAT
Figure 4. Logic Diagram (STM818)
VCCV
WDI
E
STM818
V
SS
BAT
Table 2. Signal Names
MR Pus h-button Rese t Input
WDI Watchdog Input
RST
RST Active-High Reset Output
Active-Low Reset Output
V
OUT
RST
E
CON
AI07896
4/37
MR
PFI
STM703/
704/819
V
SS
V
OUT
RST
PFO
AI07895
(1)
E
(1)
E
CON
V
OUT
V
CC
V
BA T
PFI Power-fail Input
PFO
V
SS
Note: 1. STM818
Chip Enable Input
Conditioned Chip Enable Output
Supply Voltage Output
Supply Voltage
Back-up Supply Voltage
Power-fail Output
Ground
STM690A/692A/703/704/802/805/817/818/819
Figure 5. STM690A/692A/802/805/817 Connections
SO8/TSSOP8
V
OUT
V
V
PFI
Note: 1. For STM805, reset output i s active-h i gh.
CC
SS
1
2
3
4
8
7
6
5
V
BAT
RST(RST)
WDI
PFO
AI07889
(1)
Figure 6. STM703/704/819 Connections
SO8/TSSOP8
V
OUT
V
CC
V
PFI
SS
1
2
3
4
V
8
7
6
5
BAT
RST
MR
PFO
AI07890
Figure 7. STM818 Connections
SO8/TSSOP8
V
OUT
V
CC
V
SS
1
2
3
E
4
V
8
7
6
5
BAT
RST
WDI
E
CON
AI07892
5/37
STM690A/692A/703/704/802/805/817/818/819
Pin Descrip tio ns
. A logic low on /MR as serts the reset output.
MR
Reset remains asserted as long as MR
after MR returns high. This active-low input
for t
rec
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and res et is triggered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or falling edge.
The watchdog function can be di sabled by allowing the WDI pin to float.
. Pulses low for t
RST
low whenever V
when MR
either V
is a logic low. It remains low for t
rises above the reset threshold, the
CC
CC
when triggered, and stays
rec
is below the reset t hreshol d or
watchdog triggers a reset, or MR
high.
RST. Pulses high for t
stays high whenever V
threshold or when MR
high for t
after either VCC falls below the reset
rec
when triggered, and
rec
is above the reset
CC
is a logic high. It remains
threshold, the watchdog triggers a reset, or MR
goes from high to low.
is low and
after
rec
goes from low to
V
. When VCC is above the switchover voltage
OUT
), V
(V
SO
channel MOSFET switch. Whe n V
, V
V
SO
is connected to VCC through a P-
OUT
connects to V
BAT
. Connect to VCC if no
OUT
CC
falls be low
battery is used.
. When VCC falls below VSO, V
V
BAT
from V
hysteresis, V
ceed V
. The input to the chip-enable gating circuit. Con-
E
to V
CC
. Connect to VCC if no battery is used.
CC
. Whe n VCC rises above VSO +
BAT
reconnects to VCC. V
OUT
OUT
BAT
switches
may ex-
nect to ground if unused.
. E
E
CON
set is not asserted. If E
serted, E
goes low only when E is low a nd re-
CON
will remain low for 15µs or until E
CON
is low when reset is as-
CON
goes high, whichever occurs first. In the disabled
mode, E
is pulled up to V
CON
PFI. When PFI is less than V
below 2.4V (or V
remains high. Connect to ground if unused.
PFO
PFO
. When PFI is less than V
low 2.4V (or V
), PFO goes low; otherwise,
SO
), PFO goes low; otherwise, PFO
SO
.
OUT
or when VCC falls
PFI
, or VCC falls be-
PFI
remains high. Leave open if unused.
Table 3. Pin Description
Pin Name Function
STM690A
STM818
––6–MR
66–6WDIWatchdog Input
777–RST
–––7RSTActive-High Reset Output
1111
2222
8888
4–––EChip Enable Input
5–––
–444PFIPFI Power-fail Input
–555PFO
3333
STM692A
STM802
STM817
STM703
STM704
STM819
STM805
V
E
Push-button Reset Input
Active-Low Reset Output
Supply Output for External LPSRAM
OUT
V
Supply Voltage
CC
V
Backup-Battery Input
BA T
Conditioned Chip Enable Output
CON
PFO Power-fail Output
V
Ground
SS
6/37
STM690A/692A/703/704/802/805/817/818/819
Figure 8. Block Diagram (STM690A/692A/802/805 /817)
V
CC
V
BAT
V
OUT
COMPARE
COMPARE
WATCHDOG
COMPARE
WDI
PFI
V
SO
V
RST
V
PFI
Note: 1. For STM805, reset output i s active-h i gh.
Figure 9. Block Diagram (STM703/704/819)
V
CC
V
BAT
V
SO
TIMER
COMPARE
t
rec
Generator
RST(RST)
PFO
AI07897
V
(1)
OUT
MR
PFI
V
RST
V
PFI
COMPARE
COMPARE
t
rec
Generator
RST
PFO
AI07898
7/37
STM690A/692A/703/704/802/805/817/818/819
Figure 10. Block Diagram (STM818)
V
CC
V
BAT
WDI
E
Figure 11. Hardware Hookup
Unregulated
Voltage
Regulator
V
IN
V
OUT
V
SO
V
RST
COMPARE
COMPARE
WATCHDOG
TIMER
E
CON
OUTPUT
t
rec
Generator
RST
CONTROL
E
CON
AI07899a
V
CC
V
CC
V
OUT
V
CC
From Microprocessor
R1
R2
Note: 1. For STM690A/ 692A/802/805/817/818.
2. For STM818 only.
3. Not availab l e on S T M 818.
4. For STM703/ 704/819.
0.1µF
Push-Button
STM690A/692A/
703/704/802/805/
817/818/819
(1)
WDI
(2)
E
PFI
MR
V
BAT
E
CON
(3)
PFO
(4)
RST
V
CC
LPSRAM
E
E
0.1µF
(2)
(3)
To Microprocessor NMI
To Microprocessor Reset
AI07893
8/37
OPERATION
Reset Output
The STM690A/692A/703/704/802/805/817/818/
819 Supervisor asserts a reset signal to the MCU
whenever V
), a watchdog time-out occ urs, or when the
(V
RST
Push-button Reset Input (MR
guaranteed to be a logic low (logic high for
STM805) for 0V < V
than 1V. Without a back-up battery, RST
anteed valid down to V
During power-up, once V
threshold an internal timer keeps RST
reset time-out period, t
returns high.
drops below the reset threshold, RST goes
If V
CC
low. Each time RST
least the reset time-out period (t
goes below the reset threshold the internal timer
clears. The reset timer starts when V
above the reset threshold.
Push-button Reset Input (STM703/704/819)
A logic low on MR
asserted while MR
42., page 28) after it returns high. The MR
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary switch from MR
ual reset function; external debounce circuitry is
goes below the reset threshold
CC
) is taken low. RST is
CC
< V
RST
if V
is greater
BAT
is guar-
=1V.
CC
exceeds the reset
CC
low for the
. After this interval RST
rec
is asserted, it stays low for at
). Any time V
rec
returns
CC
asserts reset. Reset remains
is low, and for t
(see Figure
rec
to GND to create a man-
CC
input
STM690A/692A/703/704/802/805/817/818/819
not required. If MR
the device is used in a noisy environment, connect
a 0.1µF capacitor from M R
ditional noise immunity. MR
when not used.
V
CC
Watchdog Input (NOT available on STM703/ 704/819)
The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
reset is asserted. The internal watchdog timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (t
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure
43., page 28).
Note: The watchdog function may be disabled by
floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10uA and the
maximum allowable load capacitance is 200pF.
Note: Input frequency greater than 20ns (50MHz)
will be filte re d.
is driven from long cables or
to GND to provide ad-
may float, or be tied to
(1.6sec typ), th e
WD
+ t
rec
).
WD
9/37
STM690A/692A/703/704/802/805/817/818/819
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through V
voltage V
SRAM to the back-up supply when V
. With a backup battery installed with
OUT
, the devices automatically switch the
BAT
CC
falls .
Note: If back-up battery is not used, connect both
V
BAT
and V
OUT
to VCC.
This family of Supervisors does not always connect V
BAT
connects to V
V
BAT
when V
CC
to V
is below V
OUT
when V
OUT
RST
is greater than VCC.
BAT
(through a 100Ω switch)
and V
. This is done to
BAT
allow the back-up battery (e.g., a 3.6V lithium cell)
to have a higher voltage than V
Assuming V
> 2.0V, switchover at VSO ensures
BAT
that battery back-up mode is entered before V
CC
.
OUT
gets too close to the 2.0V minimum required to reliably retain data in most external SRAMs. When
recovers, hysteresis is used to avoid oscilla-
V
CC
tion around the V
through a 3Ω PMOS power switch.
V
CC
point. V
SO
is connected to
OUT
Note: The back-up battery may be removed while
is valid, ass uming V
V
CC
is adequately decou-
BAT
pled (0.1µF typ), without danger of triggering a reset.
Table 4. I/O Status in Battery Back-up
Pin Status
V
V
PFO
E
WDI Watchdog timer is disabled
WDO
RST
RST Logic high
V
Connected to V
OUT
Disconnected from V
CC
PFI Disabled
Logic low
E
High impedance
Logic high
CON
Logic low
MR
Disabled
Logic low
Connected to V
BA T
through internal switch
BAT
OUT
OUT
Chip -Enable Gati ng (STM81 8 only)
Internal gating of the chip enable (E
) signal prevents erroneous data from co rrupting th e exte rnal
CMOS RAM in the event of an undervoltage condition. The STM818 uses a series transmission
gate from E
to E
(see Figure 12., page 11).
CON
During normal operation (reset not asserted), the
transmission gate is enabled and passes all E
E
transitions. When reset is asserted, this pat h becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short E
tion d e l a y fr o m E
to E
be used with mos t µP s. If E
sert s, E
remains low for typically 15µs to per-
CON
enables the STM818 to
CON
is low when reset as-
propaga-
mit the current WRITE cycle to complete. Connect
to VSS if unused.
E
Chip Enable Input (STM818 only)
The chip-enable transmission gate is disabled and
is high impedance (disabled mode) while reset
E
is asserted. During a power-down sequence when
passes the reset threshold, the chip-enable
V
CC
transmission gate disables and E
comes high impedance if the voltage at E
is low when reset asserts, the chip-enable
If E
immediately be-
is high.
transmission gate will disable 15µs a fter reset asserts (see Figure 13., page 11). This permits the
current WRITE cycle to complete during powerdown.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E
high impedance (regardless of E
acti vity) f or the
remains
reset time-out period. When the chip enable transmission gate is enabled, the impeda nce of E
ap-
pears as a 40Ω resi stor in series with the load at
. The propagation delay through the chip-en-
E
CON
able transmission gate depends on V
CC
, the
source impedance of the drive connected to E
and the loading on E
. The chip ena ble propa-
CON
gation delay is production tested from the 50%
point on E
to the 50% point on E
using a 50Ω
CON
driver and a 5 0pF load cap acitance (see Figure
40., page 28). For minimum propagation delay,
minimize the capacitive load at E
and use a
CON
low-output impedance driver.
Chip Enable Output (STM818 only)
When the chip-enable transmission gate is enabled, the impedance of E
40Ω resistor in series with the source driving E
is equ ivalent to a
CON
. In
the disabled mode, the transmission gate is off
and an active pull-up connects E
CON
to V
OUT
(see
Figure 12., page 11). This pull-up turns off when
the transmission gate is enabled.
,
10/37
Figure 12. Chip-Enable Gating
V
CC
V
RST
COMPARE
STM690A/692A/703/704/802/805/817/818/819
t
E
OUTPUT
CON
CONTROL
rec
Generator
RST
V
OUT
E
AI08802
Figure 13. Chip Enable Waveform
V
E
RST
E
CC
CON
V
RST
V
BAT
trec trec15µs
E
CON
AI08803b
11/37
STM690A/692A/703/704/802/805/817/818/819
Power-fail Input/Output (NOT available on STM818)
The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the V
RST
comparator). If PFI is less than the power-fail
threshold (V
), the Power-Fail Output (PFO) will
PFI
go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external
voltage divider (see Figure 11. , pag e 8) to either
the unregulated DC input (if it is a vailable) or the
regulated output of the V
regulator. The voltage
CC
divider can be set up such that the voltage at PFI
falls below V
regulated V
several milliseconds before the
PFI
input to the STM690A/692A/703/
CC
704/802/805/817/818/819 Supervisor or the microprocessor drops below the m inimum o perating
voltage.
Figure 14. Power-fail Comparator Waveform (STM817/818/ 819)
V
CC
V
RST
During battery back-up, the power-fail comparator
turns off and PFO
ure 14 and Figure 15., page 13). This occurs after
drops below 2.4V (or VSO). When power re-
V
CC
turns, PFO
spec tiv e o f V
At the end of this time, the power-fail comparator
is enabled and PFO
is unused, PFI should be connected to V
left unconnected. PFO may be connec ted t o
PFO
on the STM703/704/818 so that a low voltage
MR
on PFI will generate a reset output.
Applications Information
These Supervisor circuits are not short-circuit protected. Shorting V
er-up transients such as charging a decoupling
capacitor - destroys the device. Decouple both
and V
V
CC
pacitors as close to the device as possible.
goes (or remains) low (see Fig-
is forced high (STM817/819 only), irre-
for the WRITE protect time (t
PFI
rec
follows PFI. If the comparator
and
SS
to ground - excluding pow-
OUT
pins to ground by placing 0.1µF ca-
BAT
).
VSO (or 2.4V)
PFO
(STM817/819)
RST
(STM818)
E
CON
trec
PFO follows PFI PFO follows PFI
RST to E
Delay (STM818)
CON
AI08804a
12/37
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